TWI500163B - 低溫多晶矽薄膜電晶體、其製備方法及顯示裝置 - Google Patents
低溫多晶矽薄膜電晶體、其製備方法及顯示裝置 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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Description
本發明係關於一種低溫多晶矽薄膜電晶體、其製備方法、及顯示裝置,尤指一種於製程中減少退火次數以及降低製程溫度的低溫多晶矽薄膜電晶體之製備方法。
現今平面顯示器多使用液晶顯示器,由於液晶顯示器具有省電、低輻射、質輕等優點,在市面上已成為主流商品,而現今之液晶顯示器中的薄膜電晶體係主要分為兩種:由非晶矽(Amorphous-Silicon;a-Si)所製成、或由多晶矽(Poly-Silicon;p-Si)所製成,而目前薄膜電晶體係以非晶矽之製程為主流,相關技術相較之下也較為成熟。然而,由於多晶矽之載體移動度(Mobility)係非晶矽之100倍以上,且具有高亮度、高解析度、低耗電,輕薄等優點,因此,多晶矽液晶顯示器之製造技術被大量的研究。
多晶矽液晶顯示器技術中,以低溫多晶矽(Low Temperature Poly Silicon;LTPS)為新一代主要製造技術。由於低溫多晶矽製程之顯示器更為輕薄,可將組件微小化,並整合更多電子電路,使低溫多晶矽薄膜電晶體小型化,因此可降低產品之重量且製造成本更低廉,故在液晶顯示器市場上受到矚目。
然而,習知的低溫多晶矽薄膜電晶體製程中包括氫化(hydrogenation)、去氫化(dehydrogenation)、以及摻雜活化(dopant activation)過程,皆需要再經由熱或雷射能量處
理。其中,摻雜活化係將摻雜之不純物活化,使多晶矽層之源極和汲極低電阻化,使關閉電壓值提高。然而,使用雷射活化的成本相當高,且高溫的製程則會限制基板材料的選擇而限制低溫多晶矽薄膜電晶體的應用。因此目前急需一種能替代使用雷射活化摻雜區以及高溫製程之低溫多晶矽薄膜電晶體製備方法,除了節省成本,更可擴大低溫多晶矽薄膜電晶體之應用方式。
本發明之主要目的係在提供一種低溫多晶矽薄膜電晶體、其製備方法、及顯示裝置,本發明之特色在於不需使用雷射活化摻雜其他原子之源極以及汲極,而是在製備過程中,於源極及汲極以及第一導電層間形成一金屬薄膜層,此金屬薄膜層係選自鎳、鈦、鈷、以及鎢金屬所組成之群組,經由此金屬薄膜層與源極以及汲極產生反應,形成金屬矽化物層,則可於低溫下活化源極以及汲極,不但可省去使用雷射活化之成本,整體製程的溫度最高可控制於350℃以下,如此一來,由於整體製程溫度的降低,增加了基板材料的選擇,可利用於未來更多種類的液晶顯示面板的製程上。
本發明之低溫多晶矽薄膜電晶體之製備方法,其方法至少包括以下步驟:(A)提供一低溫多晶矽薄膜電晶體基板,其結構包括:基板;形成於基板上之緩衝層;形成於緩衝層上之多晶矽層,其中,多晶矽層係具有源極、汲極、以及通道;第一絕緣層部分形成於多晶矽層上,並暴露出
多晶矽層之源極以及汲極;部分形成於第一絕緣層上之閘極;部分形成於閘極以及部分第一絕緣層上之第二絕緣層;(B)於低溫多晶矽薄膜電晶體結構中暴露該源極及汲極上形成一金屬薄膜層;(C)於金屬薄膜層上形成第一導電層,且第一導電層係凸出於第二絕緣層上,並進行退火製程時同時活化該摻雜物質,使金屬薄膜層與源極及汲極反應形成金屬矽化物層,而該金屬矽化物層存在於該源極、汲極與該金屬薄膜層;以及(D)形成保護層於第一導電層以及第二絕緣層上,以形成低溫多晶矽薄膜電晶體。
如上所述之步驟(A)中,多晶矽層之厚度較佳為30 nm-100 nm,且多晶矽層係經由非晶矽層雷射退火之多結晶化處理後形成。緩衝層之厚度係為100 nm-400 nm,且其材料係至少一選自氧化矽、及氮化矽所組成之群組。而第一絕緣層之厚度係為40 nm-300 nm,其材料亦係至少一選自氧化矽、及氮化矽所組成之群組。閘極係使用鉬、鎢或其合金等金屬材料所製成,較佳為使用鉬金屬。
再者,於步驟(B)中,金屬薄膜層之材料係由至少一選自鎳、鈦、鈷、以及鎢金屬所組成之群組,其中以鎳金屬為較佳。金屬薄膜層可使用濺射法將厚度約為數十到數百奈米之金屬薄膜鍍於源極以及汲極上。而於步驟(C)中,第一導電層係為鉬、鉬/鋁/鉬、或鈦/鋁/鈦其中之一所組成,而形成於源極之金屬矽化物層以及汲極之金屬矽化物層間之最小距離(D min)或等於2μm。
本發明更包括一種顯示裝置,該顯示面板裝置係包括低溫多晶矽薄膜電晶體,其中該低溫多晶矽薄膜電晶體基板包括:基板;緩衝層,形成於基板上;多晶矽層,形成於緩衝層上,其中,多晶矽層係具有完成摻雜物質之源極、汲極、以及通道;第一絕緣層,係形成於多晶矽層上;閘極,係形成於第一絕緣層上且相對應於該通道,而該閘極係被圖案化;第二絕緣層,形成於閘極以及第一絕緣層上;連接孔,係貫穿該第二絕緣層與第一絕緣層且相對形成於源極以及汲極處;金屬薄膜層,形成於源極以及汲極上處之連接孔;第一導電層,形成於該金屬薄膜層上,且第一導電層係凸出於第二絕緣層上;其中,金屬薄膜層與多晶矽層之源極與汲極之間具有一金屬矽化物層;以及,保護層形成於第一導電層以及第二絕緣層上。
在上述之顯示裝置中,於低溫多晶矽薄膜電晶體中,基板係為玻璃基板或塑膠基板,而金屬矽化物層係由至少一選自鎳、鈦、鈷、以及鎢金屬所組成之群組與源極以及汲極反應而形成,且位於源極之金屬矽化物層與汲極之金屬矽化物層間的最小距離(D min)需大於或等於2μm。
形成於源極以及汲極與金屬薄膜層之間之金屬矽化物層係由至少一選自鎳、鈦、鈷、以及鎢金屬所組成之群組與源極以及汲極之多晶矽層反應而形成,且位於該源極之該金屬矽化物層與該汲極之該金屬矽化物層間的最小距離(D min)大於或等於2μm。再者,第一導電層係為鉬、鉬/鋁/鉬、或鈦/鋁/鈦其中之一所組成
源極與汲極之間之金屬薄膜層與形成源極與汲極的多晶矽可於退火製程時反應成為金屬矽化物,而該金屬矽化物分布於重摻雜之多晶矽層,或是擴散到輕摻雜之多晶矽層,但該金屬矽化物係不可擴散到多晶矽之通道區,然而金屬矽化物之間之距離可經由控制退火之溫度及時間,使該金屬矽化物並不會被擴散到該通道區,如退火溫度係為330℃,時間為1至2小時,而調控位於該通道區兩側之該源極與該汲區之該金屬矽化物之間須至少保持2到3μm的間隔,以維持通道之操作功能。而該金屬矽化物可降低該源極與該汲極進行摻雜物質活化時所需要之活化能量,因此可降低活化之溫度,將低溫多晶矽薄膜電晶體的製程溫度降低,對於低溫多晶矽薄膜電晶體製程係一重大改良。
本發明之低溫多晶矽薄膜電晶體結構之較佳實施態樣如圖1O所示,而該結構之較佳製程係如圖1A-1O所示。
本發明之低溫多晶矽薄膜電晶體結構如圖1M所示,包括控制區以及像素區,控制區包括NMOS電晶體區以及PMOS電晶體區,畫素區包括了NMOS電晶體區,其製備方法如下所述。
首先,如圖1A所示,提供一基板,該基板包括基板100、形成於基板上之氮化矽緩衝層101、以及形成於氮化矽緩衝層101上之氧化矽緩衝層102,非晶矽層103形成於該基板上,非晶矽層103之厚度約為30 nm~100 nm。經雷射退火將非晶矽層103轉換成多晶矽層104,如圖1B所示,利用微影
蝕刻製程形成一第一光阻105於多晶矽層104上,蝕刻多晶矽層104後,再以化學溶劑去除第一光阻105得到如圖1C所示之結構,其中,左方多晶矽層區域係成為一控制區10之NMOS電晶體區1041與PMOS電晶體區1042,而右方多晶矽層係成為一畫素區11之NMOS電晶體區1043。
接者,形成一第二光阻106於控制區10之PMOS電晶體區1042,如圖1D所示,對基板植入硼之摻雜物質以形成通道(Channel doping),劑量約為1E11~1E12。如圖1E所示,再於控制區10之NMOS電晶體區1041以及畫素區11之NMOS電晶體區1043上部分形成第三光阻107,對暴露之多晶矽層植入重濃度之磷之摻雜物質,其劑量約為1E14~1E15,於控制區10之NMOS電晶體1041以及畫素區11之NMOS電晶體1043形成源極104a、104c以及汲極104b、104e後,移除第三光阻107。
如圖1F所示,於多晶矽層以及氧化矽緩衝層102上形成第一氧化矽絕緣層108以及第一氮化矽絕緣層109後,再於第一氮化矽絕緣層109上形成一閘極導電層110,該閘極導電層110係為鉬金屬所構成,並於閘極導電層110上形成第三光阻111,利用微影與蝕刻製程,形成閘極112,如圖1G所示,再利用閘極112作為光阻,對於該結構植入輕濃度之磷之摻雜物質(Light Doping Drain),其劑量約為1E12~1E14,形成輕摻雜區104f、104g、104h、104i、104j、104k、104l、以及104l’。接者,如圖1H所示,形成一第四光阻113於控制區10之NMOS電晶體區1041以及畫素區11之
NMOS電晶體區1043上,暴露出控制區10之PMOS電晶體區1042,並對其結構植入重濃度之硼摻雜,其劑量約為1E14~1E15,以形成控制區10之PMOS電晶體區1042之源極104m及汲極104n。
接著,如圖1I所示,移除第四光阻113後,於閘極112以及之第一氮化矽絕緣層109上形成之第二氮化矽絕緣層114,其厚度約為數百奈米,再於第二氮化矽絕緣層114上形成第二氧化矽絕緣層115,其厚度約為數百奈米,以及於第二氧化矽絕緣層上115形成第五光阻116。如圖1J所示,利用微影與蝕刻製程,形成複數個連接孔117以暴露出控制區10之NMOS電晶體區1041,控制區10之PMOS電晶體區1042、以及畫素區11之NMOS電晶體區1043之源極104a、104m、104c及汲極104b、104n、104b,接者,於暴露出之源極(104a、104m、104c)、汲極(104b、104n、104b)、以及連接孔117上形成一層鎳金屬薄膜層118後,再依序於鎳金屬薄膜層118上沈積形成一第一導電層119,該第一導電層119係為鉬/鋁/鉬之多層金屬沈積而成。
其形態如圖2A,於該鎳金屬薄膜層118與該第一導電層119沈積完成後,其會進行退火製程,而退火製程係先提高環境溫度到預定要進行退火之溫度後,再快速降低溫度到環境溫度,藉此,於退火製程中可活化多晶矽層20其重摻雜區、輕摻雜區與通道區之摻雜物質,如圖2A及2B所示,其中包括第一導電層22、使鎳金屬薄膜層23、以及經由與其所接觸之源極與汲極產生反應而形成之一鎳矽化物層
24,並控制其退火製程之時間使該鎳矽化物24可於重摻雜之多晶矽層20之該源極與該汲極處及該鎳金屬薄膜層處層擴散,而形成於該源極與該汲極間之鎳矽化物之間之最小距離(D min)至少需距離2~3μm(含)以上,以保持良好的電晶體性質。由於鎳金屬薄膜層118的存在,可降低多晶矽層之重摻雜區、輕摻雜區、以及通道區域中摻雜物質之活化溫度。
接著,如圖1K所示該第一導電層119上形成第六光阻121,再利用微影與蝕刻製程,圖案化第一導電層119以,如圖1L所示,形成控制區10以及畫素區11源極104a、104m、104c及汲極104b、104n、104d電性連接的第一導電層119。
接著,如圖1M所示,形成一保護層123於第一導電層119與第二氧化矽絕緣層115上,並形成連接孔124於畫素區11之保護層123,再著,如圖1N所示,形成由銦錫氧化物(ITO)
所組成之第二導電層125,而本案之該第二導電層125係為ITO導電層,該第二導電層125設於保護層123上,並可填滿連接孔124,之後再形成一第七光阻126於畫素區11。如圖1O所示,利用微影與蝕刻製程移除控制區10上方之第二導電層125,而形成如圖1O所示之低溫多晶矽薄膜電晶體。
經由上述製備方法所製造出的低溫多晶矽薄膜電晶體包括:基板;緩衝層,形成於基板上;多晶矽層,形成於緩衝層上,其中,多晶矽層係具有源極、汲極、以及通道;第一絕緣層,部分形成於多晶矽層上,並暴露出多晶矽層之源極以及汲極;閘極,部分形成於第一絕緣層上;第二絕緣層,部分形成於閘極以及部分第一絕緣層上;第一導電層,形成於源極以及汲極上,且源極以及汲極與第一導電層間形成一金屬薄膜層,該金屬薄膜層與該源極與該汲極並形成一金屬矽化物層,且第一導電層係凸出於第二絕緣層上;保護層形成於第一導電層以及第二絕緣層上;第二導電層,形成於畫素區之保護層上。
上述實施例僅係為了方便說明而舉例而已,本發明所主張之權利範圍自應以申請專利範圍所述為準,而非僅限於上述實施例。
100‧‧‧基板
101‧‧‧氮化矽緩衝層
102‧‧‧氧化矽緩衝層
103‧‧‧非晶矽層
104‧‧‧多晶矽層
105‧‧‧第一光阻
10‧‧‧控制區
11‧‧‧畫素區
1041,1043‧‧‧NMOS電晶體區
1042‧‧‧PMOS電晶體區
104a,104c,104m‧‧‧源極
104b,104d,104n‧‧‧汲極
104f,104g,104h,104i,104j,104k,104l,104l’‧‧‧輕摻雜區
106‧‧‧第二光阻
107‧‧‧第三光阻
108‧‧‧第一氧化矽絕緣層
109‧‧‧第一氮化矽絕緣層
110‧‧‧閘極導電層
111‧‧‧第三光阻
112‧‧‧閘極
113‧‧‧第四光阻
114‧‧‧第二氮化矽絕緣層
115‧‧‧第二氧化矽絕緣層
116‧‧‧第五光阻
117,124‧‧‧連接孔
118‧‧‧鎳金屬薄膜層
119‧‧‧第一導電層
121‧‧‧第六光阻
123‧‧‧保護層
125‧‧‧第二導電層
126‧‧‧第七光阻
20‧‧‧多晶矽層
21‧‧‧輕摻雜區
22‧‧‧第一導電層
23‧‧‧鎳金屬薄膜層
24‧‧‧鎳矽化物層
圖1A~1O係本發明之低溫多晶矽薄膜電晶體的製作流程。
圖2A及圖2B係本發明中金屬矽化物層之態樣。
100‧‧‧基板
101‧‧‧氮化矽緩衝層
102‧‧‧氧化矽緩衝層
10‧‧‧控制區
11‧‧‧畫素區
108‧‧‧第一氧化矽絕緣層
109‧‧‧第一氮化矽絕緣層
112‧‧‧閘極
114‧‧‧第二氮化矽絕緣層
115‧‧‧第二氧化矽絕緣層
123‧‧‧保護層
119‧‧‧第一導電層
125‧‧‧第二導電層
Claims (16)
- 一種低溫多晶矽薄膜電晶體之製備方法,該方法至少包括:(A)提供一低溫多晶矽薄膜電晶體基板,包括:一基板;一緩衝層形成於該基板上;一多晶矽層形成於該緩衝層上,其中,該多晶矽層係具有一源極、一汲極、以及一通道;一第一絕緣層部分形成於該多晶矽層上,並暴露出該多晶矽層之該源極以及該汲極;一閘極,部分形成於該第一絕緣層上;一第二絕緣層部分形成於該閘極以及部分該第一絕緣層上;(B)於該低溫多晶矽薄膜電晶體結構中暴露之該源極及汲極上形成一金屬薄膜層;(C)於該金屬薄膜層上形成一第一導電層,且該第一導電層係凸出於該第二絕緣層上,並進行一退火製程,使該金屬薄膜層與該源極及該汲極反應形成一金屬矽化物層,其中,該金屬矽化物層係位於該金屬薄膜層與該源極及該汲極處,並控制該退火製程時間,使該源極之該金屬矽化物層及該汲極之該金屬矽化物層間之最小距離係大於或等於2μm;以及(D)形成一保護層於該第一導電層以及該第二絕緣層上,以形成一低溫多晶矽薄膜電晶體。
- 如申請專利範圍第1項所述之方法,其中,步驟(A)中,該緩衝層係至少一選自氧化矽、及氮化矽所組成之群組。
- 如申請專利範圍第1項所述之方法,其中,步驟(A)中,該第一絕緣層係至少一選自氧化矽層、及氮化矽層所組成之群組。
- 如申請專利範圍第1項所述之方法,其中,步驟(A)中,該閘極係為鉬、鎢或其合金。
- 如申請專利範圍第1項所述之方法,其中,步驟(C)中,該第二絕緣層係至少一選自氧化矽層、及氮化矽層所組成之群組。
- 如申請專利範圍第1項所述之方法,其中,步驟(B)中,該金屬薄膜層之材料係由至少一選自鎳、鈦、鈷、以及鎢金屬所組成之群組。
- 如申請專利範圍第1項所述之方法,其中,步驟(C)中,該第一導電層係為鉬、鉬/鋁/鉬、或鈦/鋁/鈦其中之一所組成。
- 一種顯示裝置,包括:一顯示面板,係顯示由一低溫多晶矽薄膜電晶體基板所提供之影像,而該低溫多晶矽薄膜電晶體基板更包括:一基板;一緩衝層,形成於該基板上;一多晶矽層,形成於該緩衝層上,其中,該多晶矽層係具有完成摻雜物質之一源極、一汲極、以及一通道;一第一絕緣層,係形成於該多晶矽層上,;一閘極,係形成於該第一絕緣層上且相對應於該通道,而該閘極係被圖案化; 一第二絕緣層,形成於該閘極以及該第一絕緣層上;一連接孔,係貫穿該第二絕緣層與該第一絕緣層且相對形成於該源極以及該汲極處;一金屬薄膜層,形成於該源極以及該汲極處之該連接孔;一第一導電層,形成於該金屬薄膜層上,且該第一導電層係凸出於該第二絕緣層上;其中,一金屬矽化物層係位於該金屬薄膜層與多晶矽層之該源極與該汲極之間,且該源極之該金屬矽化物層及該汲極之該金屬矽化物層間之最小距離係大於或等於2μm;以及一保護層形成於該第一導電層以及該第二絕緣層上。
- 如申請專利範圍第8項所述之顯示裝置,其中,該基板係為玻璃基板或塑膠基板。
- 如申請專利範圍第8項所述之顯示裝置,其中,該緩衝層係至少一選自氧化矽、及氮化矽所組成之群組。
- 如申請專利範圍第8項所述之顯示裝置,其中,該第一絕緣層係至少一選自氧化矽層、及氮化矽層所組成之群組。
- 如申請專利範圍第8項所述之顯示裝置,其中,該閘極係為鉬、鎢或其合金。
- 如申請專利範圍第8項所述之顯示裝置,其中,該第二絕緣層係至少一選自氧化矽層、及氮化矽層所組成之群組。
- 如申請專利範圍第8項所述之顯示裝置,其中,該金屬矽化物層係由至少一選自鎳、鈦、鈷、以及鎢金屬所組成之群組與該源極以及該汲極反應而形成。
- 如申請專利範圍第8項所述之顯示裝置,其中,該金屬矽化物層間的距離大於或等於2μm。
- 如申請專利範圍第8項所述之顯示裝置,其中,該第一導電層係為鉬、鉬/鋁/鉬、或鈦/鋁/鈦其中之一所組成。
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KR100875432B1 (ko) * | 2007-05-31 | 2008-12-22 | 삼성모바일디스플레이주식회사 | 다결정 실리콘층의 제조 방법, 이를 이용하여 형성된박막트랜지스터, 그의 제조방법 및 이를 포함하는유기전계발광표시장치 |
KR100889626B1 (ko) * | 2007-08-22 | 2009-03-20 | 삼성모바일디스플레이주식회사 | 박막트랜지스터, 그의 제조방법, 이를 구비한유기전계발광표시장치, 및 그의 제조방법 |
US20130189838A1 (en) * | 2012-01-20 | 2013-07-25 | Makoto Honda | Semiconductor manufacturing apparatus and method of manufacturing semiconductor device |
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2012
- 2012-10-15 TW TW101137900A patent/TWI500163B/zh active
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2013
- 2013-10-07 US US14/047,164 patent/US20140103351A1/en not_active Abandoned
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JP2007333808A (ja) * | 2006-06-12 | 2007-12-27 | Mitsubishi Electric Corp | アクティブマトリクス表示装置 |
TW200939317A (en) * | 2008-03-08 | 2009-09-16 | Advance Design Technology Inc | A processing method of low temperature poly silicon based thin film induced by nano-metallic thin film |
US20120171822A1 (en) * | 2010-12-29 | 2012-07-05 | Boe Technology Group Co., Ltd. | Manufacturing method for ltps tft array substrate |
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US20140103351A1 (en) | 2014-04-17 |
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