WO2014063376A1 - 一种主动矩阵式平面显示装置、薄膜晶体管及其制作方法 - Google Patents

一种主动矩阵式平面显示装置、薄膜晶体管及其制作方法 Download PDF

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WO2014063376A1
WO2014063376A1 PCT/CN2012/083735 CN2012083735W WO2014063376A1 WO 2014063376 A1 WO2014063376 A1 WO 2014063376A1 CN 2012083735 W CN2012083735 W CN 2012083735W WO 2014063376 A1 WO2014063376 A1 WO 2014063376A1
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oxide
buffer layer
layer
oxide semiconductor
drain
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PCT/CN2012/083735
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English (en)
French (fr)
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江政隆
陈柏林
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深圳市华星光电技术有限公司
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Priority to US13/700,658 priority Critical patent/US20140117348A1/en
Publication of WO2014063376A1 publication Critical patent/WO2014063376A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/263—Amorphous materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an active matrix type flat display device, a thin film transistor, and a method of fabricating the same.
  • Oxide TFT Oxide Thin Film Transistor
  • Oxide TFT technology is originally applied to a-Si
  • the silicon semiconductor material of the TFT is partially replaced with an oxide semiconductor such as IGZO (Indium Gallium Zinc Oxide) to form a TFT.
  • IGZO Indium Gallium Zinc Oxide
  • Semiconductor layer Currently, Oxide TFTs mainly have BCE type (Back Channel Etched) and ES type (Etch). Stopper, etch barrier type), in which the BCE type Oxide TFT has the advantages of simple process and high channel width to length ratio with respect to the ES type Oxide TFT.
  • the oxide semiconductor layer is easily damaged by subsequent processes. For example, when the source and drain are etched or the protective layer is deposited, the oxide semiconductor layer is easily damaged, thereby causing deterioration and instability of the Oxide TFT characteristics.
  • the technical problem to be solved by the present invention is to provide an active matrix type flat display device, a thin film transistor and a manufacturing method thereof, which can prevent damage of an oxide semiconductor layer by a subsequent process, thereby ensuring stability of the TFT and ensuring an active matrix type.
  • the display quality of the flat display device is to provide an active matrix type flat display device, a thin film transistor and a manufacturing method thereof, which can prevent damage of an oxide semiconductor layer by a subsequent process, thereby ensuring stability of the TFT and ensuring an active matrix type.
  • a technical solution adopted by the present invention is to provide a method for fabricating a thin film transistor, the manufacturing method comprising the steps of: providing a gate on a substrate; and providing a first insulating layer on the gate; An oxide semiconductor layer and a buffer layer are sequentially stacked on an insulating layer, wherein the buffer layer is composed of a transparent conductive oxide; a source and a drain are disposed on the oxide semiconductor layer and the buffer layer; and the source and the drain are not
  • the buffer layer in direct contact is subjected to plasma treatment or heat treatment in an oxygen-containing atmosphere, so that the buffer layer not directly in contact with the source and the drain has an oxygen content higher than that of the buffer layer directly contacting the source and the drain.
  • the composition of the oxide semiconductor layer includes at least one of an oxide of zinc, an oxide of tin, an oxide of indium, and an oxide of gallium.
  • the material of the buffer layer includes at least one of indium tin oxide, indium zinc oxide, aluminum zinc oxide, and gallium zinc oxide.
  • the thickness of the oxide semiconductor layer is greater than the thickness of the buffer layer.
  • the oxide semiconductor layer and the buffer layer are in ohmic contact.
  • a thin film transistor including: a gate; a first insulating layer disposed on the gate; an oxide semiconductor layer and a buffer layer, Laidly disposed on the first insulating layer, wherein the buffer layer is composed of a transparent conductive oxide; the source and the drain are respectively disposed on the oxide semiconductor layer and the buffer layer, wherein the source and the drain are not in direct contact
  • the buffer layer has an oxygen content higher than that of the buffer layer in direct contact with the source and the drain.
  • the composition of the oxide semiconductor layer includes at least one of an oxide of zinc, an oxide of tin, an oxide of indium, and an oxide of gallium.
  • the material of the buffer layer includes at least one of indium tin oxide, indium zinc oxide, aluminum zinc oxide, and gallium zinc oxide.
  • the thickness of the oxide semiconductor layer is greater than the thickness of the buffer layer.
  • the oxide semiconductor layer and the buffer layer are in ohmic contact.
  • an active matrix type flat display device including an array substrate, the array substrate comprising: a substrate; a gate disposed on the substrate a first insulating layer disposed on the gate electrode; an oxide semiconductor layer and a buffer layer sequentially stacked on the first insulating layer, wherein the buffer layer is composed of a transparent conductive oxide; the source and the drain are respectively disposed On the oxide semiconductor layer and the buffer layer; the second insulating layer is disposed on the source and the drain, and a via hole is disposed at a position corresponding to the drain of the second insulating layer; and the transparent conductive layer is disposed in the second On the insulating layer, and connected to the drain through the via hole; wherein the material of the buffer layer and the material of the transparent conductive layer are the same, and the oxygen content of the buffer layer not directly in contact with the source and the drain is higher than the source The oxygen content of the buffer layer in which the pole and the drain are in direct contact.
  • the thickness of the oxide semiconductor layer is greater than the thickness of the buffer layer.
  • the material of the buffer layer includes at least one of indium tin oxide, indium zinc oxide, aluminum zinc oxide, and gallium zinc oxide.
  • the composition of the oxide semiconductor layer includes at least one of an oxide of zinc, an oxide of tin, an oxide of indium, and an oxide of gallium.
  • the oxide semiconductor layer and the buffer layer are in ohmic contact.
  • the invention has the beneficial effects that the oxide semiconductor layer and the buffer layer are sequentially stacked on the first insulating layer, and the source and the drain are respectively disposed on the oxide semiconductor layer and the buffer layer.
  • the buffer layer not in direct contact with the source and the drain is subjected to plasma treatment or heat treatment in an oxygen-containing atmosphere, so that the buffer layer not in direct contact with the source and the drain has a higher oxygen content than the source and The oxygen content of the buffer layer directly in contact with the drain electrode, therefore, the buffer layer functions to protect the oxide semiconductor layer, prevent damage to the oxide semiconductor layer by subsequent processes, ensure stability of the thin film transistor, and ensure active The display quality of the matrix type flat display device.
  • FIG. 1 is a flow chart showing a method of fabricating a thin film transistor according to a first embodiment of the present invention
  • FIG. 2 is a process diagram of a thin film transistor of the present invention
  • FIG. 3 is a schematic structural view of a thin film transistor according to a second embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of an active matrix type flat display device according to a third embodiment of the present invention.
  • FIG. 5 is a schematic structural view of an array substrate in the active matrix type flat display device shown in FIG. 4.
  • FIG. 5 is a schematic structural view of an array substrate in the active matrix type flat display device shown in FIG. 4.
  • FIG. 1 is a flowchart of a method for fabricating a thin film transistor according to a first embodiment of the present invention
  • FIG. 2 is a process diagram corresponding to the method for fabricating the thin film transistor of FIG.
  • the manufacturing method of the thin film transistor of the present invention comprises the following steps:
  • Step S1 providing a gate electrode 101 on the substrate 100;
  • step S1 a substrate 100 is first provided, and a gate electrode 101 is disposed on the substrate 100.
  • the gate electrode 101 serves as a control electrode of the thin film transistor for controlling the thin film transistor to be turned on after receiving an external signal.
  • Step S2 providing a first insulating layer 102 on the gate electrode 101;
  • a first insulating layer 102 is provided on the gate electrode 101, and the first insulating layer 102 is used to insulate the electrical properties of the other layers from the gate electrode 101.
  • Step S3 sequentially laying an oxide semiconductor layer 103 and a buffer layer 104 on the first insulating layer 102;
  • step S3 an oxide semiconductor layer 103 is provided on the first insulating layer 102, and a buffer layer 104 is provided on the oxide semiconductor layer 103.
  • the lamination of the buffer layer 104 and the oxide semiconductor layer 103 can be performed by continuous film formation by sputtering, and etching can be simultaneously performed by oxalic acid. Therefore, the process can be simplified.
  • the thickness of the oxide semiconductor layer 103 is larger than the thickness of the buffer layer 104.
  • the oxide semiconductor layer 103 is preferably an IGZO layer whose composition includes at least one of zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), and gallium oxide (GaOx).
  • the buffer layer 104 is a conductive layer, preferably composed of a transparent conductive oxide, and the material thereof includes indium tin oxide.
  • the buffer layer 104 of the present embodiment is preferably ITO.
  • the buffer layer 104 serves to prevent damage to the oxide semiconductor layer 103 by subsequent processes.
  • Step S4 A source 105 and a drain 106 are provided on the oxide semiconductor layer 103 and the buffer layer 104, respectively.
  • step S4 the oxide semiconductor layer 103 and the buffer layer 104 are sequentially stacked between the source 105 and the drain 106 and the first insulating layer 102, and the buffer layer 104 is not in direct contact with the source 105 and the drain 106.
  • the portion is the buffer layer 141, and the portion in direct contact with the source 105 and the drain 106 is the buffer layer 142.
  • the oxide semiconductor layer 103 and the buffer layer 104 are in ohmic contact, thereby reducing the interface resistance between the source 105, the drain 106, and the buffer layer 104 to the semiconductor layer 103.
  • Step S5 The buffer layer 141 not in direct contact with the source 105 and the drain 106 is subjected to plasma treatment or heat treatment in an oxygen-containing atmosphere.
  • step S5 after the setting of the source 105 and the drain 106 is completed, the buffer layer 141 is further subjected to plasma treatment or heat treatment of an oxygen-containing atmosphere, so that the oxygen content of the buffer layer 141 is higher than that of the buffer layer 142. the amount.
  • the buffer layer 141 forms a high-impedance protective film, which functions to protect the oxide semiconductor layer 103, thereby reducing the influence of plasma and moisture during the process, thereby preventing subsequent process pairs.
  • the damage of the oxide semiconductor layer 103 ensures the stability of the thin film transistor.
  • the second insulating layer 107 is further provided on the source 105 and the drain 106.
  • the second insulating layer 107 is in contact with the buffer layer 141.
  • the second insulating layer 107 serves to protect the source 105, the drain 106, the buffer layer 104, and the oxide semiconductor layer 103 from external damage.
  • FIG. 3 is a schematic structural diagram of a thin film transistor according to a second embodiment of the present invention.
  • the thin film transistor 300 of the present invention includes a gate 301, a first insulating layer 302, an oxide semiconductor layer 303, a buffer layer 304, a source 305, a drain 306, and a second insulating layer 307.
  • the first insulating layer 302 is a gate insulating layer disposed on the gate 301.
  • the oxide semiconductor layer 303 and the buffer layer 304 are sequentially stacked on the first insulating layer 301, wherein the oxide semiconductor layer 303 is disposed adjacent to the first insulating layer 302, and the buffer layer 304 is disposed on the oxide semiconductor layer 303, wherein Buffer layer 304 includes a buffer layer 341 that is not in direct contact with source 305 and drain 306 and a buffer layer 342 that is in direct contact with source 305 and drain 306.
  • the lamination of the buffer layer 304 and the oxide semiconductor layer 303 can be performed by continuous film formation by sputtering, and can be simultaneously etched by oxalic acid. This simplifies the process.
  • the source 305 and the drain 306 are made of the same metal, and the source 305 and the drain 306 are respectively disposed on the oxide semiconductor layer 303 and the buffer layer 304.
  • the buffer layer 341 not in direct contact with the source 305 and the drain 306 has an oxygen content higher than that of the buffer layer 342 which is in direct contact with the source 305 and the drain 306.
  • the buffer layer 341 is treated by plasma treatment or heat treatment in an oxygen-containing atmosphere to increase the oxygen content of the buffer layer 341.
  • the buffer layer 341 forms a high-impedance protective film, which functions to protect the oxide semiconductor layer 303, thereby reducing the influence of plasma and moisture during the process, thereby preventing subsequent process pairs.
  • the damage of the oxide semiconductor layer 303 ensures the stability of the thin film transistor.
  • connection between the buffer layer 304 and the oxide semiconductor layer 303 is an ohmic contact, and therefore, the interface resistance value between the source 305, the drain 306, and the buffer layer 304 to the oxide semiconductor layer 303 is lowered.
  • the thickness of the oxide semiconductor layer 303 is larger than the thickness of the buffer layer 304.
  • the oxide semiconductor layer 303 is preferably an IGZO layer whose composition includes at least one of an oxide of zinc, an oxide of tin, an oxide of indium, and an oxide of gallium.
  • the buffer layer 304 is composed of a transparent conductive oxide, and the material thereof includes at least one of indium tin oxide, indium zinc oxide, aluminum zinc oxide, and gallium zinc oxide.
  • FIG. 4 is a schematic structural diagram of an active matrix type flat display device according to a third embodiment of the present invention.
  • the active matrix type flat display device 400 of the present invention includes a color filter substrate 410 and an array substrate 420 which are disposed opposite each other.
  • the array substrate 420 includes a substrate 421.
  • the material of the substrate 421 is preferably glass.
  • main elements such as scanning lines, data lines, pixel electrodes, and thin film transistors can be formed.
  • FIG. 5 is a schematic structural diagram of the array substrate 420 in the active matrix type flat display device shown in FIG.
  • the array substrate 420 includes a substrate 421, a thin film transistor 422, and a transparent conductive layer 423.
  • the structure of the thin film transistor 422 is the same as that of the thin film transistor 300 shown in FIG.
  • the transparent conductive layer 423 is disposed on the second insulating layer 407, and the second insulating layer 407 is disposed at a position corresponding to the drain 406 such that the transparent conductive layer 423 passes through the via 424 and the thin film transistor.
  • the drain 406 of 422 is electrically connected.
  • the transparent conductive layer 423 serves as a pixel electrode of the array substrate 420.
  • the oxide semiconductor layer 403 and the buffer layer 404 are sequentially stacked on the first insulating layer 402, and the thickness of the oxide semiconductor layer 403 is larger than the thickness of the buffer layer 404.
  • the lamination of the oxide semiconductor layer 403 and the buffer layer 404 can be performed by continuous film formation by sputtering, and can be simultaneously etched by oxalic acid. Therefore, the process can be simplified.
  • a source 405 and a drain 406 are disposed on the oxide semiconductor layer 403 and the buffer layer 404, respectively.
  • the connection between the buffer layer 404 and the oxide semiconductor layer 403 is an ohmic contact, and therefore, the interface resistance value between the source 405, the drain 406, and the buffer layer 404 to the oxide semiconductor layer 403 is lowered.
  • the buffer layer 404 includes a buffer layer 441 not in direct contact with the source electrode 405 and the drain electrode 406, and a buffer layer 442 in direct contact with the source electrode 405 and the drain electrode 406, and the buffer layer 441 has a higher oxygen content than the buffer layer 441.
  • the oxygen content of the buffer layer 442 is such that the buffer layer 441 forms a high-impedance protective film, which functions to protect the oxide semiconductor layer 403, thereby reducing the influence of plasma and moisture during the process, thereby preventing subsequent process oxidation.
  • the damage of the semiconductor layer 403 ensures the stability of the thin film transistor.
  • the buffer layer 404 is composed of a transparent conductive oxide.
  • the material of the buffer layer 404 includes at least one of indium tin oxide, indium zinc oxide, aluminum zinc oxide, and gallium zinc oxide.
  • the embodiment preferably includes ITO.
  • the oxide semiconductor layer 403 is preferably an IGZO layer whose composition includes at least one of an oxide of zinc, an oxide of tin, an oxide of indium, and an oxide of gallium.
  • an oxide semiconductor layer and a buffer layer are sequentially stacked on the first insulating layer, and a source and a drain are respectively disposed on the oxide semiconductor layer and the buffer layer, wherein the source and the drain are respectively
  • the buffer layer not in direct contact is subjected to plasma treatment or heat treatment in an oxygen-containing atmosphere, so that the buffer layer not directly in contact with the source and the drain has an oxygen content higher than that of the buffer layer directly in contact with the source and the drain.
  • the buffer layer functions to protect the oxide semiconductor layer, prevent damage to the oxide semiconductor layer by subsequent processes, ensure the stability of the thin film transistor, and ensure the display quality of the active matrix flat display device;
  • the oxide semiconductor layer of the present invention is in ohmic contact with the buffer layer, thereby reducing the interface resistance between the source, the drain, and the buffer layer to the semiconductor layer;
  • the buffer layer of the present invention is a transparent conductive oxide. It is disposed on the oxide semiconductor layer, and the stack of the buffer layer and the oxide semiconductor layer can be formed by continuous film formation by sputtering, and can be simultaneously etched by oxalic acid, thereby Simplify the manufacturing process.

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Abstract

公开了一种主动矩阵式平面显示装置、薄膜晶体管及其制作方法。该制作方法包括：S2：在栅极（101）上设置第一绝缘层（102）；S3：在第一绝缘层（102）上依次层叠设置氧化物半导体层（103）和缓冲层（10）；S4：在氧化物半导体层（103）和缓冲层（104）上设置源极（105）和漏极（106）；S5：对与源极（105）和漏极（106）未直接接触的缓冲层（104）进行含氧气氛的电浆处理或热处理，使与源极（105）和漏极（106）未直接接触的缓冲层（141）的含氧量高于与源极（105）和漏极（106）直接接触的缓冲层（142）的含氧量。通过以上方式，该制造方法可防止后续的制程对氧化物半导体层的损坏，从而保证薄膜晶体管的稳定性，并保证主动矩阵式平面显示装置的显示品质。

Description

一种主动矩阵式平面显示装置、薄膜晶体管及其制作方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种主动矩阵式平面显示装置、薄膜晶体管及其制作方法。
【背景技术】
目前，Oxide TFT（氧化物薄膜晶体管）的应用已经被实现。Oxide TFT技术是将原本应用于a-Si TFT的硅半导体材料部分置换成氧化物半导体如IGZO(Indium Gallium Zinc Oxide, 铟镓锌氧化物)，以形成TFT 半导体层。目前Oxide TFT主要有BCE型（Back Channel Etched，背沟道刻蚀型）和ES型（Etch Stopper，刻蚀阻挡型）两种结构，其中BCE型的Oxide TFT相对于ES型的Oxide TFT，其具有工艺制程较简单与较高的沟道宽长比等优点。
但是，对于BCE型的Oxide TFT，其氧化物半导体层容易受到后续制程的损伤, 例如在蚀刻源极和漏极或者沉积保护层时，氧化物半导体层容易受到损坏，从而造成Oxide TFT特性劣化以及不稳定。
【发明内容】
本发明主要解决的技术问题是提供一种主动矩阵式平面显示装置、薄膜晶体管及其制作方法，能够防止后续的制程对氧化物半导体层的损坏，从而保证TFT的稳定性，并保证主动矩阵式平面显示装置的显示品质。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种薄膜晶体管的制作方法，该制作方法包括以下步骤：在基底上设置栅极；在栅极上设置第一绝缘层；在第一绝缘层上依次层叠设置氧化物半导体层和缓冲层，其中，缓冲层由透明导电氧化物构成；在氧化物半导体层和缓冲层上设置源极和漏极；对与源极和漏极未直接接触的缓冲层进行含氧气氛的电浆处理或热处理，使与源极和漏极未直接接触的缓冲层的含氧量高于与源极和漏极直接接触的缓冲层的含氧量。
其中，氧化物半导体层的组成成分包括锌的氧化物、锡的氧化物、铟的氧化物以及镓的氧化物中的至少一种。
其中，缓冲层的材料包括铟锡氧化物、铟锌氧化物、铝锌氧化物以及镓锌氧化物中的至少一种。
其中，氧化物半导体层的厚度大于缓冲层的厚度。
其中，氧化物半导体层和缓冲层之间为欧姆接触。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种薄膜晶体管，该薄膜晶体管包括：栅极；第一绝缘层，设置在栅极上；氧化物半导体层和缓冲层, 依次层叠设置在第一绝缘层上，其中，缓冲层由透明导电氧化物构成；源极和漏极，分别设置在氧化物半导体层和缓冲层上，其中，与源极和漏极未直接接触的缓冲层的含氧量高于与源极和漏极直接接触的缓冲层的含氧量。
其中，氧化物半导体层的组成成分包括锌的氧化物、锡的氧化物、铟的氧化物以及镓的氧化物中的至少一种。
其中，缓冲层的材料包括铟锡氧化物、铟锌氧化物、铝锌氧化物以及镓锌氧化物中的至少一种。
其中，氧化物半导体层的厚度大于缓冲层的厚度。
其中，氧化物半导体层和缓冲层之间为欧姆接触。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种主动矩阵式平面显示装置，该主动矩阵式平面显示装置包括阵列基板，该阵列基板包括：基底；栅极，设置在基底上；第一绝缘层，设置在栅极上；氧化物半导体层和缓冲层，依次层叠设置在第一绝缘层上，其中，缓冲层由透明导电氧化物构成；源极和漏极，分别设置在氧化物半导体层和缓冲层上；第二绝缘层，设置在源极和漏极上，在第二绝缘层对应于漏极的位置处设置有一导通孔；透明导电层，设置在第二绝缘层上，且通过导通孔与漏极连接；其中，缓冲层的材料和透明导电层的材料相同，并且，与源极和漏极未直接接触的缓冲层的含氧量高于与源极和漏极直接接触的缓冲层的含氧量。
其中，氧化物半导体层的厚度大于缓冲层的厚度。
其中，缓冲层的材料包括铟锡氧化物、铟锌氧化物、铝锌氧化物以及镓锌氧化物中的至少一种。
其中，氧化物半导体层的组成成分包括锌的氧化物、锡的氧化物、铟的氧化物以及镓的氧化物中的至少一种。
其中，氧化物半导体层和缓冲层之间为欧姆接触。
本发明的有益效果是：区别于现有技术的情况，本发明在第一绝缘层上依次层叠设置氧化物半导体层和缓冲层，在氧化物半导体层和缓冲层上分别设置源极和漏极，其中，对与源极和漏极未直接接触的缓冲层进行含氧气氛的电浆处理或热处理，使与源极和漏极未直接接触的缓冲层的含氧量高于与源极和漏极直接接触的缓冲层的含氧量，因此，缓冲层起到保护氧化物半导体层的作用，可防止后续的制程对氧化物半导体层的损坏，保证了薄膜晶体管的稳定性，并保证主动矩阵式平面显示装置的显示品质。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明第一实施例的一种薄膜晶体管的制作方法的流程图；
图2是本发明的薄膜晶体管的制程图；
图3是本发明第二实施例的一种薄膜晶体管的结构示意图；
图4是本发明第三实施例的一种主动矩阵式平面显示装置的结构示意图；
图5是图4所示的主动矩阵式平面显示装置中阵列基板的结构示意图。
【具体实施方式】
下面结合附图和实施例对本发明进行详细说明。
请一起参阅图1和图2，图1是本发明第一实施例的一种薄膜晶体管的制作方法的流程图，图2是图1所示的薄膜晶体管的制作方法对应的制程图。本发明的薄膜晶体管的制作方法包括以下步骤：
步骤S1：在基底100上设置栅极101；
在步骤S1中，首先提供一基底100，并在基底100上设置栅极101，栅极101作为薄膜晶体管的控制电极，用于接收外部信号后，控制薄膜晶体管开启。
步骤S2：在栅极101上设置第一绝缘层102；
在步骤S2中，在栅极101上设置第一绝缘层102，第一绝缘层102用于绝缘其他层与栅极101的电性。
步骤S3：在第一绝缘层102上依次层叠设置氧化物半导体层103和缓冲层104；
在步骤S3中，在第一绝缘层102上设置氧化物半导体层103，在氧化物半导体层103上设置缓冲层104。
在本实施例中，缓冲层104和氧化物半导体层103的层叠可用溅射连续成膜而制成，并可通过草酸同时进行蚀刻。因此，可简化制程。
在本实施例中，氧化物半导体层103的厚度大于缓冲层104的厚度。氧化物半导体层103优选为IGZO层，其组成成分包括锌的氧化物（ZnOx）、锡的氧化物（SnOx）、铟的氧化物（InOx）以及镓的氧化物（GaOx）中的至少一种。缓冲层104为导电层，优选由透明导电氧化物构成，其材料包括铟锡氧化物 (ITO，Indium Tin Oxides)、铟锌氧化物（IZO，Indium Zinc Oxides）、铝锌氧化物（AZO，Aluminum Zinc Oxides）以及镓锌氧化物（GZO，Gallium Zinc Oxides）中的至少一种，其中，本实施例缓冲层104优选为ITO。缓冲层104用于防止后续的制程对氧化物半导体层103的损坏。
步骤S4：在氧化物半导体层103和缓冲层104上分别设置源极105和漏极106。
在步骤S4中，氧化物半导体层103和缓冲层104依次层叠设置在源极105和漏极106以及第一绝缘层102之间，并且缓冲层104中与源极105和漏极106未直接接触的部分为缓冲层141，与源极105和漏极106直接接触的部分为缓冲层142。
本实施例中，氧化物半导体层103与缓冲层104之间为欧姆接触，从而降低源极105、漏极106和缓冲层104到半导体层103间的界面电阻值。
步骤S5：对与源极105和漏极106未直接接触的缓冲层141进行含氧气氛的电浆处理或热处理。
在步骤S5中，在完成源极105和漏极106的设置之后，进一步对缓冲层141进行含氧气氛的电浆处理或热处理，使得缓冲层141的含氧量高于缓冲层142的含氧量。通过增加缓冲层141的含氧量使得缓冲层141形成了高阻抗保护膜，起到保护氧化物半导体层103的作用，可降低制程过程中电浆以及湿气的影响，从而防止后续的制程对氧化物半导体层103的损坏，保证了薄膜晶体管的稳定性。
在完成对缓冲层104的处理后，进一步在源极105和漏极106上设置第二绝缘层107。其中，第二绝缘层107与缓冲层141接触。第二绝缘层107用于保护源极105、漏极106、缓冲层104以及氧化物半导体层103避免受到外界损坏。
请参阅图3，图3是本发明第二实施例的一种薄膜晶体管的结构示意图。如图3所示，本发明的薄膜晶体管300包括栅极301、第一绝缘层302、氧化物半导体层303、缓冲层304、源极305、漏极306及第二绝缘层307。
本实施例中，第一绝缘层302为栅极绝缘层，其设置在栅极301上。氧化物半导体层303和缓冲层304依次层叠设置在第一绝缘层301上，其中，氧化物半导体层303紧靠第一绝缘层302设置，缓冲层304设置在氧化物半导体层303上，其中，缓冲层304包括与源极305和漏极306未直接接触的缓冲层341和与源极305和漏极306直接接触的缓冲层342两部分。缓冲层304和氧化物半导体层303的层叠可用溅射连续成膜而制成，并可通过草酸同时进行蚀刻。因此可简化制程。
本实施例中，源极305和漏极306由同一金属制成，源极305和漏极306分别设置在氧化物半导体层303和缓冲层304上。本实施例中，与源极305和漏极306未直接接触的缓冲层341的含氧量高于与源极305和漏极306直接接触的缓冲层342的含氧量。
具体而言，通过含氧气氛的电浆处理或热处理对缓冲层341进行处理，以增加缓冲层341的含氧量。通过增加缓冲层341的含氧量使得缓冲层341形成了高阻抗保护膜，起到保护氧化物半导体层303的作用，可降低制程过程中电浆以及湿气的影响，从而防止后续的制程对氧化物半导体层303的损坏，保证了薄膜晶体管的稳定性。
本实施例中，缓冲层304与氧化物半导体层303之间的连接为欧姆接触，因此，降低由源极305、漏极306和缓冲层304到氧化物半导体层303间的界面电阻值。
在本实施例中，氧化物半导体层303的厚度大于缓冲层304的厚度。氧化物半导体层303优选为IGZO层，其组成成分包括锌的氧化物、锡的氧化物、铟的氧化物以及镓的氧化物中的至少一种。缓冲层304由透明导电氧化物构成，其材料包括铟锡氧化物、铟锌氧化物、铝锌氧化物以及镓锌氧化物中的至少一种。
请参阅图4，图4是本发明第三实施例的一种主动矩阵式平面显示装置的结构示意图。如图4所示，本发明的主动矩阵式平面显示装置400包括相对设置的彩色滤光片基板410和阵列基板420。
本实施例中，阵列基板420包括基底421。基底421的材质优选为玻璃，通过在基底421上进行镀膜和蚀刻等工艺，可形成扫描线、数据线、像素电极和薄膜晶体管等主要元件。
请参阅图5，图5是图4所示的主动矩阵式平面显示装置中阵列基板420的结构示意图。如图5所示，阵列基板420包括基底421、薄膜晶体管422以及透明导电层423。其中，薄膜晶体管422的结构与图3所示的薄膜晶体管300的结构相同。
在本实施例中，透明导电层423设置在第二绝缘层407上，并且第二绝缘层407在对应漏极406的位置处设置一通孔424，使得透明导电层423通过通孔424与薄膜晶体管422的漏极406实现电性连接。其中透明导电层423作为阵列基板420的像素电极。
本实施例中，氧化物半导体层403和缓冲层404依次层叠设置在所述第一绝缘层402上，并且氧化物半导体层403的厚度大于缓冲层404的厚度。氧化物半导体层403和缓冲层404的层叠可用溅射连续成膜而制成，并可通过草酸同时进行蚀刻。因此，可简化制程。
源极405和漏极406分别设置在氧化物半导体层403和缓冲层404上。缓冲层404与氧化物半导体层403之间的连接为欧姆接触，因此，降低由源极405、漏极406和缓冲层404到氧化物半导体层403间的界面电阻值。
本实施例中，缓冲层404包括与源极405和漏极406未直接接触的缓冲层441和与源极405和漏极406直接接触的缓冲层442，并且缓冲层441的含氧量高于缓冲层442的含氧量，使得缓冲层441形成了高阻抗保护膜，起到保护氧化物半导体层403的作用，可降低制程过程中电浆以及湿气的影响，从而防止后续的制程对氧化物半导体层403的损坏，保证了薄膜晶体管的稳定性。
本实施例中，缓冲层404的材料和透明导电层423的材料相同。缓冲层404由透明导电氧化物构成，具体地，缓冲层404的材料包括铟锡氧化物、铟锌氧化物、铝锌氧化物以及镓锌氧化物中的至少一种，本实施例优选包括ITO。氧化物半导体层403优选为IGZO层，其组成成分包括锌的氧化物、锡的氧化物、铟的氧化物以及镓的氧化物中的至少一种。
综上所述，本发明在第一绝缘层上依次层叠设置氧化物半导体层和缓冲层，在氧化物半导体层和缓冲层上分别设置源极和漏极，其中，对与源极和漏极未直接接触的缓冲层进行含氧气氛的电浆处理或热处理，使与源极和漏极未直接接触的缓冲层的含氧量高于与源极和漏极直接接触的缓冲层的含氧量，因此，缓冲层起到保护氧化物半导体层的作用，可防止后续的制程对氧化物半导体层的损坏，保证了薄膜晶体管的稳定性，并保证主动矩阵式平面显示装置的显示品质；另外，本发明的氧化物半导体层与缓冲层之间为欧姆接触，从而降低源极、漏极和缓冲层到半导体层间的界面电阻值；再者，本发明的缓冲层为透明导电氧化物，其设置在氧化物半导体层上，并且缓冲层和氧化物半导体层的层叠可用溅射连续成膜而制成，并可通过草酸同时进行蚀刻，因此可简化制程。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种薄膜晶体管的制作方法，其中，所述制作方法包括以下步骤：
    在基底上设置栅极；
    在所述栅极上设置第一绝缘层；
    在所述第一绝缘层上依次层叠设置氧化物半导体层和缓冲层，其中，所述缓冲层由透明导电氧化物构成；
    在所述氧化物半导体层和所述缓冲层上分别设置源极和漏极；
    对与所述源极和漏极未直接接触的所述缓冲层进行含氧气氛的电浆处理或热处理，使与所述源极和漏极未直接接触的所述缓冲层的含氧量高于与所述源极和漏极直接接触的所述缓冲层的含氧量。
  2. 根据权利要求1所述的制作方法，其中，所述氧化物半导体层的组成成分包括锌的氧化物、锡的氧化物、铟的氧化物以及镓的氧化物中的至少一种。
  3. 根据权利要求1所述的制作方法，其中，所述缓冲层的材料包括铟锡氧化物、铟锌氧化物、铝锌氧化物以及镓锌氧化物中的至少一种。
  4. 根据权利要求1所述的制作方法，其中，所述氧化物半导体层的厚度大于所述缓冲层的厚度。
  5. 根据权利要求1所述的制作方法，其中，所述氧化物半导体层和所述缓冲层之间为欧姆接触。
  6. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    栅极；
    第一绝缘层，设置在所述栅极上；
    氧化物半导体层和缓冲层, 依次层叠设置在所述第一绝缘层上，其中，所述缓冲层由透明导电氧化物构成；
    源极和漏极，分别设置在所述氧化物半导体层和所述缓冲层上；
    其中，与所述源极和漏极未直接接触的所述缓冲层的含氧量高于与所述源极和漏极直接接触的所述缓冲层的含氧量。
  7. 根据权利要求6所述的薄膜晶体管，其中，所述氧化物半导体层的组成成分包括锌的氧化物、锡的氧化物、铟的氧化物以及镓的氧化物中的至少一种。
  8. 根据权利要求6所述的薄膜晶体管，其中，所述缓冲层的材料包括铟锡氧化物、铟锌氧化物、铝锌氧化物以及镓锌氧化物中的至少一种。
  9. 根据权利要求6所述的薄膜晶体管，其中，所述氧化物半导体层的厚度大于所述缓冲层的厚度。
  10. 根据权利要求6所述的薄膜晶体管，其中，所述氧化物半导体层和所述缓冲层之间为欧姆接触。
  11. 一种主动矩阵式平面显示装置，其中，所述主动矩阵式平面显示装置包括阵列基板，所述阵列基板包括：
    基底；
    栅极，设置在所述基底上；
    第一绝缘层，设置在所述栅极上；
    氧化物半导体层和缓冲层，依次层叠设置在所述第一绝缘层上，其中，所述缓冲层由透明导电氧化物构成；
    源极和漏极，分别设置在所述氧化物半导体层和所述缓冲层上；
    第二绝缘层，设置在所述源极和漏极上，在所述第二绝缘层对应于所述漏极的位置处设置有一导通孔；
    透明导电层，设置在所述第二绝缘层上，且通过所述导通孔与所述漏极连接；
    其中，所述缓冲层的材料和所述透明导电层的材料相同，并且，与所述源极和漏极未直接接触的所述缓冲层的含氧量高于与所述源极和漏极直接接触的所述缓冲层的含氧量。
  12. 根据权利要求11所述的主动矩阵式平面显示装置，其中，所述氧化物半导体层的厚度大于所述缓冲层的厚度。
  13. 根据权利要求11所述的主动矩阵式平面显示装置，其中，所述缓冲层的材料包括铟锡氧化物、铟锌氧化物、铝锌氧化物以及镓锌氧化物中的至少一种。
  14. 根据权利要求11所述的主动矩阵式平面显示装置，其中，所述氧化物半导体层的组成成分包括锌的氧化物、锡的氧化物、铟的氧化物以及镓的氧化物中的至少一种。
  15. 根据权利要求11所述的主动矩阵式平面显示装置，其中，所述氧化物半导体层和所述缓冲层之间为欧姆接触。
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