WO2022267532A1 - 阵列基板及其制备方法、显示面板 - Google Patents

阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2022267532A1
WO2022267532A1 PCT/CN2022/079200 CN2022079200W WO2022267532A1 WO 2022267532 A1 WO2022267532 A1 WO 2022267532A1 CN 2022079200 W CN2022079200 W CN 2022079200W WO 2022267532 A1 WO2022267532 A1 WO 2022267532A1
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Prior art keywords
transistor
oxide
electrode
substrate
sub
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PCT/CN2022/079200
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English (en)
French (fr)
Inventor
王利忠
宁策
邸云萍
童彬彬
黄睿
周天民
杨维
雷利平
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京东方科技集团股份有限公司
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Priority to US18/021,090 priority Critical patent/US20230317740A1/en
Publication of WO2022267532A1 publication Critical patent/WO2022267532A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/134309—Electrodes characterised by their geometrical arrangement
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Definitions

  • the present application relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display panel.
  • LTPS Low Temperature Polysilicon
  • oxide technology has the characteristics of low leakage (that is, small Ioff), which can solve the leakage problem and achieve low power consumption; therefore, the combination of the two LTPO Technology has become the focus of industry research.
  • the conventional LTPO substrate has reached more than 15 mask (Mask) processes, which has brought great challenges to product cost and yield. .
  • Embodiments of the present application provide an array substrate, a manufacturing method thereof, and a display panel.
  • the array substrate has the characteristics of high aperture ratio, simple manufacturing process, and low production cost.
  • an array substrate including: a display area and a non-display area connected to the display area; the display area includes a plurality of sub-pixels arranged in an array;
  • the non-display area includes at least one polysilicon transistor;
  • the sub-pixel includes an oxide transistor and a pixel electrode;
  • the gate of the oxide transistor is set on the same layer as the first pole and the second pole of the polysilicon transistor; the active layer of the oxide transistor is set on the same layer as the pixel electrode and is in contact; the oxide The active layer of the transistor includes an oxide semiconductor material, and the pixel electrode includes an oxide conductor material.
  • the array substrate further includes a substrate, and the polysilicon transistor and the sub-pixel are arranged on the same side of the substrate;
  • the polysilicon transistor is a top-gate polysilicon transistor, the gate of the oxide transistor is set on the side of the active layer of the oxide transistor away from the substrate, and the gate of the oxide transistor is on the side of the oxide transistor.
  • the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the active layer of the oxide transistor on the substrate.
  • the orthographic projection of the gate of the oxide transistor on the substrate is located within the orthographic projection of the active layer of the oxide transistor on the substrate.
  • the array substrate further includes a gate insulating layer, the gate insulating layer is arranged between the active layer of the oxide transistor and the gate of the oxide transistor, and the gate insulating layer is rich in Oxygen oxide layer.
  • the oxide transistor further includes a connection electrode, the connection electrode is arranged on a side of the gate of the oxide transistor away from the substrate, and is electrically connected to the active layer of the oxide transistor .
  • the sub-pixel further includes a light shielding portion, the light shielding portion is disposed on a side of the active layer of the oxide transistor close to the substrate, and the active layer of the oxide transistor is on the side of the substrate.
  • the orthographic projection on the substrate is located within the orthographic projection of the light shielding portion on the substrate, and the orthographic projection of the pixel electrode on the substrate partially intersects the orthographic projection of the light shielding portion on the substrate. stack.
  • the gate of the polysilicon transistor is disposed on the same layer as the light shielding portion.
  • the sub-pixel further includes an opening area and a non-opening area connected to the opening area;
  • the oxide transistor is arranged in the non-opening area
  • the pixel electrode includes a first sub-electrode and a second sub-electrode, and both sides of the first sub-electrode are respectively connected to the second sub-electrode and the oxide
  • the active layers of the transistors are in contact with each other, the first sub-electrode is arranged in the non-opening area, and the second sub-electrode is arranged in the opening area.
  • the opening area of the sub-pixel further includes a first passivation portion and a common electrode;
  • the first passivation portion covers the second sub-electrode, and the common electrode is disposed on a side of the first passivation portion away from the second sub-electrode.
  • the pixel electrode is a planar electrode
  • the common electrode includes at least one strip-shaped sub-electrode.
  • the array substrate further includes a second passivation portion, and the second passivation portion covers the polysilicon transistor and the oxide transistor.
  • the array substrate further includes a substrate and a flat portion, the flat portion is located on a side of the second passivation portion close to the substrate, and the flat portion is on the substrate.
  • the orthographic projection of and the orthographic projection of the first passivation portion on the substrate do not overlap.
  • the display area further includes a substrate, and a plurality of gate lines and a plurality of data lines arranged on the substrate;
  • the part where the gate line overlaps the active layer of the oxide transistor along the direction perpendicular to the substrate is the gate of the oxide transistor; the gate line and the first electrode of the polysilicon transistor Set on the same layer as the second pole;
  • a portion of the data line overlapping the active layer of the oxide transistor along a direction perpendicular to the substrate is a connection electrode of the oxide transistor.
  • a display panel including the above-mentioned array substrate.
  • a method for preparing an array substrate including:
  • Forming the polysilicon transistor and the sub-pixel includes:
  • the active layer of the oxide transistor and the pixel electrode are formed by one patterning process; wherein, the active layer of the oxide transistor is in contact with the pixel electrode; the active layer of the oxide transistor includes an oxide a material semiconductor material, the pixel electrode includes an oxide conductor material;
  • the gate of the oxide transistor and the first pole and the second pole of the polysilicon transistor are formed by one patterning process.
  • the forming the active layer of the oxide transistor and the pixel electrode by one patterning process includes:
  • the oxide semiconductor layer is formed by one patterning process
  • FIG. 1 is a schematic structural diagram of an array substrate provided in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • Figure 4-13 is a flow chart of the preparation of the structure shown in Figure 13 provided by the embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • words such as “first”, “second”, and “third” are used to distinguish the same or similar items with basically the same functions and functions, only for clearly describing the technology of the embodiments of the present application scheme, and should not be understood as indicating or implying the relative importance or implying the number of indicated technical features.
  • plural means two or more, and “at least one” means one or more, unless otherwise specifically defined.
  • orientations or positional relationships indicated by the terms “upper”, “lower”, etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the application and simplifying the description, rather than indicating or None to imply that a referenced device or element must have a particular orientation, be constructed, and operate in a particular orientation should therefore not be construed as limiting the application.
  • the array substrate includes: a display area (area AA shown in FIG. 1 ) and a non-display area connected to the display area (area OA shown in FIG. 1 ); the display area includes a plurality of sub-pixels 1 arranged in an array.
  • the non-display area includes at least one polysilicon transistor 2 ; the sub-pixel includes an oxide transistor 3 and a pixel electrode 22 .
  • the gate 27 of the oxide transistor 3 is set in the same layer as the first pole 25 and the second pole 26 of the polysilicon transistor 2; the active layer 21 of the oxide transistor 3 is set in the same layer as the pixel electrode 22 Contact; the active layer 21 of the oxide transistor 3 includes an oxide semiconductor material, and the pixel electrode 22 includes an oxide conductor material.
  • the above-mentioned display area refers to the area used to realize display, and the non-display area is generally used to set up drive circuits, for example: GOA (Gate Driver on Array, array substrate row drive) drive circuits, etc.
  • GOA Gate Driver on Array, array substrate row drive
  • the specific positional relationship between the non-display area and the display area is not limited.
  • the non-display area can be set on one side of the display area and connected to one side of the display area as shown in Figure 1; It can be arranged around the display area and connected to the surrounding sides of the display area; of course, other arrangement methods can also be used, which will not be listed here, and the details can be determined according to actual requirements.
  • the above-mentioned polysilicon transistor can be applied in a GOA driving circuit or other driving circuits, which is not limited here.
  • the type of the polysilicon transistor is not limited, and it may be a top-gate polysilicon transistor, or may also be a bottom-gate polysilicon transistor.
  • a top-gate polysilicon transistor is taken as an example for illustration.
  • the polysilicon transistor may include a gate, a source and a drain, and one of the source and the drain is called a first pole, and the other is called a second pole.
  • Transistors can be classified into two types according to the positional relationship of electrodes. One is that the gate is located below the source and drain, which is called a bottom-gate thin film transistor; the other is that the gate is located above the source and drain, and this is called a top-gate thin film transistor.
  • the material of the active layer of the oxide transistor may be a metal oxide such as IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide) or ITZO (Indium Tin Zinc Oxide, indium tin zinc oxide).
  • IGZO Indium Gallium Zinc Oxide, indium gallium zinc oxide
  • ITZO Indium Tin Zinc Oxide, indium tin zinc oxide
  • One patterning process refers to the process of forming the required layer structure after one exposure.
  • a patterning process includes processes such as masking, exposure, development, etching and stripping.
  • the active layer of the oxide transistor includes an oxide semiconductor material
  • the pixel electrode includes an oxide conductor material, wherein the oxide conductor material can be formed by performing a conductor treatment on the oxide semiconductor material. For example, a plasma process can be used to treat the oxide semiconductor material. oxide semiconductor materials.
  • an oxide transistor includes a gate, a source, and a drain, wherein the drain is electrically connected to the pixel electrode, and the source is electrically connected to the data line; under the control of the oxide transistor, the data signal transmission of the data line is realized. to the pixel electrode.
  • the active layer of the oxide transistor and the pixel electrode are arranged on the same layer and are in contact with each other, so that the drain electrode can be avoided.
  • the mask process can be reduced, and the complexity of the manufacturing process can be reduced.
  • the drain is mostly made of opaque metal, thereby reducing the transmittance and aperture ratio; but in this application, there is no need to additionally set the drain, and at the same time, the pixel electrode includes an oxide conductor material, and the oxidized The transmittance of the object conductor material is relatively high, thereby greatly improving the transmittance and aperture ratio.
  • the gate of the oxide transistor is arranged in the same layer as the first electrode and the second electrode of the polysilicon transistor, which can further reduce the Mask process and simplify the process complexity.
  • the array substrate provided by the present application has the characteristics of high aperture ratio, simple manufacturing process and low production cost.
  • the array substrate further includes a substrate, and the polysilicon transistor and the sub-pixels are arranged on the same side of the substrate.
  • the polysilicon transistor 2 is a top-gate polysilicon transistor, and the gate 27 of the oxide transistor 3 is arranged on the side of the active layer 21 of the oxide transistor 3 away from the substrate 11.
  • the orthographic projection E1 of the gate 27 of the oxide transistor 3 on the substrate 11 at least partially overlaps the orthographic projection E2 of the active layer 21 of the oxide transistor 3 on the substrate 11 .
  • the orthographic projection of the gate of the oxide transistor on the substrate and the orthographic projection of the active layer of the oxide transistor on the substrate at least partially overlap include: the orthographic projection of the gate of the oxide transistor on the substrate and the oxidation
  • the orthographic projection of the active layer of the oxide transistor on the substrate partially overlaps, at this time, the gate of the oxide transistor overlaps with the active layer of the oxide transistor along the direction perpendicular to the substrate; or, the gate of the oxide transistor overlaps with the active layer of the oxide transistor
  • the orthographic projection of the gate on the substrate is located within the orthographic projection of the active layer of the oxide transistor on the substrate. overlap.
  • FIG. 13 takes the latter as an example for drawing.
  • the array substrate further includes a gate insulating layer 20, and the gate insulating layer 20 is disposed between the active layer 21 of the oxide transistor 3 and the gate 27 of the oxide transistor 3. between, and the gate insulating layer is an oxygen-rich oxide layer.
  • the material and thickness of the above-mentioned gate insulating layer are not limited.
  • it can be made of silicon dioxide, and the thickness range is
  • the above-mentioned pixel electrode can be formed by performing conductive treatment on the oxide semiconductor material.
  • the oxide semiconductor material can be formed first at the position of the pixel electrode, and then the gate insulating layer can be formed by reducing Plasma treatment is performed with an inert gas (for example: hydrogen gas) to make the oxide semiconductor material conductive, thereby forming the pixel electrode.
  • an oxygen-rich oxide layer can be used to neutralize excess H (hydrogen).
  • the oxide transistor 3 further includes a connection electrode 30, which is arranged on the side of the gate 27 of the oxide transistor 3 away from the substrate 11, and is connected to the active electrode of the oxide transistor 3.
  • Layer 21 is electrically connected.
  • an oxide transistor generally includes three electrodes: a gate, a source, and a drain; however, in this application, an oxide transistor includes two electrodes, a gate and a connecting electrode, and the structure is simpler, thereby reducing process complexity.
  • the sub-pixel further includes a light shielding portion 16.
  • the light shielding portion 16 is disposed on the side of the active layer 21 of the oxide transistor 3 close to the substrate 11, and as shown in FIG.
  • the orthographic projection E2 of the active layer 21 of the oxide transistor 3 on the substrate 11 is located within the orthographic projection E3 of the light-shielding portion 16 on the substrate 11
  • the orthographic projection E4 of the pixel electrode 22 on the substrate 11 is within the same range as the light-shielding portion 16
  • the orthographic projections E3 on the substrate 11 partially overlap.
  • the material of the light-shielding portion can be selected from opaque metals, such as copper, aluminum, silver, and the like.
  • the light-shielding part can block the light incident on the active layer, thereby preventing the active layer from being affected by the light, thereby improving the characteristics of the transistor.
  • the gate of the polysilicon transistor and the light shielding portion are arranged in the same layer, that is, the gate of the polysilicon transistor and the light shielding portion can be formed through one patterning process.
  • the sub-pixel further includes an open area (OC area) and a non-open area (OB area) connected to the open area.
  • OC area open area
  • OB area non-open area
  • the oxide transistor 3 is arranged in the non-opening area (OB area), and the pixel electrode 22 includes a first sub-electrode 221 and a second sub-electrode 222, and the two sides of the first sub-electrode 221 are connected to the second sub-electrode respectively.
  • 222 is in contact with the active layer 21 of the oxide transistor 3 , the first sub-electrode 221 is disposed in the non-open area (OB area), and the second sub-electrode 222 is disposed in the open area (OC area).
  • the above-mentioned pixel electrode can be formed by performing plasma treatment on the oxide semiconductor material.
  • part of the oxide semiconductor material under the gate insulating layer is also conductive, thereby forming the first sub-electrode;
  • the pixel electrode has a larger area, so that a larger overlapping area can be formed with the common electrode, thereby improving the driving effect of capacitance and liquid crystal molecules.
  • the oxide transistor since the oxide transistor includes two electrodes, the gate and the connecting electrode, there is no need to set a third electrode. Therefore, under the condition that the area occupied by the original sub-pixel remains unchanged, the area of the non-opening area can be reduced and the area of the opening area can be increased. area, thereby increasing the aperture ratio.
  • the opening area (OC area) of the sub-pixel also includes a first passivation portion 321 and a common electrode; the first passivation portion 321 covers the second sub-electrode 222, and the common electrode is disposed on the first sub-electrode 222.
  • the passivation portion 321 is away from the side of the second sub-electrode 222 .
  • the above-mentioned common electrode may include at least one strip-shaped sub-electrode.
  • FIG. 2 shows an example where the common electrode includes two strip-shaped sub-electrodes 33 .
  • the present application can control the pixel capacitance by controlling the thickness of the first passivation part.
  • the thickness of the first passivation part is not limited.
  • the thickness range of the first passivation part can be
  • the number of layers of the first passivation part is not limited here.
  • the first passivation part may only include a layer structure, for example: a silicon dioxide layer or a silicon nitride layer; or may also include a multilayer stack structure , For example: a two-layer stack structure of a silicon dioxide layer and a silicon nitride layer.
  • FIG. 2 shows an example in which the first passivation portion includes a one-layer structure.
  • an electric field can be formed between the common electrode and the pixel electrode to drive the deflection of the liquid crystal molecules.
  • the pixel electrode is a planar electrode
  • the common electrode includes at least one strip-shaped sub-electrode.
  • the array substrate further includes a second passivation portion 322 , and the second passivation portion 322 covers the polysilicon transistor 2 and the oxide transistor 3 .
  • the materials of the second passivation portion and the first passivation portion may be the same, and may be formed by one deposition.
  • the orthographic projection of the flat portion 31 on the substrate 11 does not overlap with the orthographic projection of the first passivation portion 321 on the substrate 11 .
  • the above-mentioned orthographic projection of the flat portion on the substrate does not overlap with the orthographic projection of the first passivation portion on the substrate, which means that no flat portion is provided in the opening area.
  • the transparent The pass rate can be increased by about 12%.
  • the display area further includes a substrate (not shown in FIG. 3 ), and a plurality of gate lines 4 and a plurality of data lines 5 disposed on the substrate.
  • the gate line 4 overlaps with the active layer 21 of the oxide transistor along the direction perpendicular to the substrate is the gate 27 of the oxide transistor; Pole same floor setting.
  • the part of the data line 5 overlapping the active layer 21 of the oxide transistor along the direction perpendicular to the substrate is the connection electrode 30 of the oxide transistor.
  • the part of the gate line overlapping with the active layer of the oxide transistor along the direction perpendicular to the substrate is used as the gate of the oxide transistor, and there is no need to set the gate separately, which further simplifies the process, saves space, and facilitates the opening
  • the gate line is arranged in the same layer as the first electrode and the second electrode of the polysilicon transistor, which can reduce the number of Mask processes and further reduce the difficulty of the process.
  • the part of the data line overlapping with the active layer of the oxide transistor along the direction perpendicular to the substrate is used as the connecting electrode of the oxide transistor, and it is not necessary to separately set the connecting electrode, which further simplifies the process, saves space, and facilitates opening rate increase.
  • the above-mentioned array substrate may also include structures such as a buffer layer 12, a first insulating layer 14, a first interlayer dielectric layer 17, and a second interlayer dielectric layer 28, which are only introduced and invented here. Click on the relevant content, and the rest of the structure can be obtained by referring to related technologies, and will not be described in detail here.
  • the embodiment of the present application also provides a display panel, including the above-mentioned array substrate.
  • the display panel can be TN (Twisted Nematic, twisted nematic) type, VA (Vertical Alignment, vertical orientation) type, IPS (In-Plane Switching, plane switching) type or ADS (Advanced Super Dimension Switch, advanced super-dimensional field switching ) type and other liquid crystal display panels, and any products or components with display functions such as TVs, digital cameras, mobile phones, and tablet computers that include these display panels.
  • the display panel may also include other structures of the array substrate such as a color filter substrate and a liquid crystal.
  • other structures can be obtained by referring to related technologies, and will not be described in detail here.
  • the embodiment of the present application further provides a method for preparing an array substrate, including:
  • S01 forming at least one polysilicon transistor and a plurality of sub-pixels arranged in an array; wherein, the polysilicon transistor is disposed in a non-display area of the array substrate, and the sub-pixel is disposed in a display area of the array substrate, and includes an oxide transistor and a pixel electrode.
  • forming polysilicon transistors and sub-pixels includes:
  • the above preparation method is simple and easy to implement.
  • the active layer of the oxide transistor and the pixel electrode are arranged on the same layer and are in contact with each other, so that the drain electrode can be avoided.
  • the mask process can be reduced, and the manufacturing process can be reduced The complexity of the process.
  • the drain is mostly made of opaque metal, which reduces the transmittance and aperture ratio; but in this application, there is no need to additionally set the drain, and at the same time, the pixel electrode includes an oxide conductor material, and the oxidized The transmittance of the object conductor material is relatively high, thereby greatly improving the transmittance and aperture ratio.
  • the gate of the oxide transistor is arranged in the same layer as the first electrode and the second electrode of the polysilicon transistor, which can further reduce the Mask process and simplify the process complexity.
  • the array substrate provided by this application has the characteristics of high aperture ratio, simple manufacturing process and low production cost.
  • S011 forming the active layer and the pixel electrode of the oxide transistor by one patterning process includes:
  • a reducing gas for example, hydrogen gas
  • a reducing gas for example, hydrogen gas
  • the active layer and the pixel electrode of the oxide transistor can be formed. This method is simple, easy to implement, and highly operable.
  • the following will take the array substrate shown in FIG. 13 as an example to illustrate its specific preparation method.
  • the method includes:
  • the aforementioned substrate may be a rigid substrate, such as a glass substrate.
  • the material of the active layer of the above-mentioned polysilicon transistor may be a low temperature polysilicon material.
  • the material of the buffer layer may be silicon oxide or silicon nitride.
  • an amorphous silicon layer (a-Si) can be formed first, and then an excimer laser annealing process (Excimer Laser Annealing, ELA) is used to convert the amorphous silicon layer into polysilicon layer, and then patterned to form the active layer 13 shown in FIG. 4 .
  • ELA excimer Laser Annealing
  • the above-mentioned first interlayer dielectric layer may include a single-layer structure; alternatively, it may also include a multilayer stack structure; for example, the first interlayer dielectric layer includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer three A stacked layer structure, wherein the first silicon oxide layer is closer to the substrate than the second silicon oxide layer; the thickness range of the first silicon oxide layer is The thickness of the silicon nitride layer ranges from The thickness range of the second silicon oxide layer is FIG. 6 shows an example in which the first interlayer dielectric layer includes a single-layer structure.
  • the material of the oxide semiconductor layer 18 can be IGZO, and the thickness range can be
  • the oxide semiconductor layer may include a single-layer structure; or, may also include a multilayer stack structure; for example, the oxide semiconductor layer includes a first oxide semiconductor sublayer and a second oxide semiconductor sublayer, wherein the first oxide semiconductor The material semiconductor sublayer is closer to the substrate than the second oxide semiconductor sublayer, and the first oxide semiconductor sublayer is a dense layer.
  • FIG. 7 shows an example in which the oxide semiconductor layer includes a single-layer structure.
  • the pixel electrode 22 includes a first sub-electrode 221 and a second sub-electrode 222.
  • part of the oxide semiconductor layer 18 can be made conductive, and part of the oxide semiconductor layer under the gate insulating layer 20 is also made conductive due to particle diffusion, thereby forming the first sub-electrode 221; at the same time
  • a first via hole 23 and a second via hole 24 as shown in FIG. 9 are also formed.
  • One Mask is required to form the gate insulating layer, one Mask is required to form the first via hole and the second via hole, and there are 2 Masks in total.
  • S107 forms the gate of the oxide transistor and the first and second electrodes of the polysilicon transistor through a patterning process, which requires a Mask.
  • the second interlayer dielectric layer may include a single-layer structure; alternatively, it may also include a multilayer stack structure; for example, the second interlayer dielectric layer includes a two-layer stack structure of a silicon oxide layer and a silicon nitride layer; FIG.
  • the inter-layer dielectric layer including a single-layer structure is shown as an example.
  • the thickness range of the second interlayer dielectric layer is
  • the present application can control the pixel capacitance by controlling the thickness of the first passivation part.
  • the thickness of the first passivation part is not limited.
  • the thickness range of the first passivation part can be
  • the first passivation portion may only include a one-layer structure, such as a silicon dioxide layer or a silicon nitride layer; or may also include a multi-layer stack structure, such as a two-layer stack structure of a silicon dioxide layer and a silicon nitride layer.
  • FIG. 2 shows an example in which the first passivation portion includes a one-layer structure.
  • S101 uses 1 mask
  • S102 uses 1 mask
  • S104 uses 1 mask
  • S106 uses 2 masks
  • S107 uses 1 mask
  • S108 uses 1 mask
  • S109 uses 1 mask
  • S110 uses 2 masks.
  • Road Mask a total of 10 Masks.

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Abstract

本申请提供了一种阵列基板及其制备方法、显示面板，涉及显示技术领域，该阵列基板具有开口率高，制作工艺简单，生产成本低的特点。阵列基板包括：显示区以及与显示区相连的非显示区；显示区包括阵列排布的多个子像素；非显示区包括至少一个多晶硅晶体管；子像素包括氧化物晶体管和像素电极；氧化物晶体管的栅极与多晶硅晶体管的第一极和第二极同层设置；氧化物晶体管的有源层与像素电极同层设置且相接触；氧化物晶体管的有源层包括氧化物半导体材料，像素电极包括氧化物导体材料。

Description

阵列基板及其制备方法、显示面板
相关申请的交叉引用
本申请要求在2021年06月25日提交中国专利局、申请号为202110714844.2、名称为“一种阵列基板及其制备方法、显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示面板。
背景技术
LTPS(低温多晶硅)技术具有高迁移率，容易实现窄边框；而氧化物技术具有低漏电(即Ioff小)的特点，能够解决漏电问题、实现低功耗；因此将两者结合在一起的LTPO技术，成为行业研究的重点。但目前由于LTPO膜层复杂，且涉及到两种不同的工艺路线，常规的LTPO基板都达到了15道以上的掩膜(Mask)工艺，这对于产品成本和良率都带来了非常大的挑战。
发明内容
本申请的实施例提供一种阵列基板及其制备方法、显示面板，该阵列基板具有开口率高，制作工艺简单，生产成本低的特点。
为达到上述目的，本申请的实施例采用如下技术方案：
一方面，提供了一种阵列基板，包括：显示区以及与所述显示区相连的非显示区；所述显示区包括阵列排布的多个子像素；
其中，所述非显示区包括至少一个多晶硅晶体管；所述子像素包括氧化物晶体管和像素电极；
所述氧化物晶体管的栅极与所述多晶硅晶体管的第一极和第二极同层设置；所述氧化物晶体管的有源层与所述像素电极同层设置且相接触；所述氧化物晶体管的有源层包括氧化物半导体材料，所述像素电极包括氧化物导体材料。
可选的，所述阵列基板还包括衬底，所述多晶硅晶体管和所述子像素设置在所述衬底的同一侧；
所述多晶硅晶体管为顶栅型多晶硅晶体管，所述氧化物晶体管的栅极设置在所述氧化物晶体管的有源层远离所述衬底的一侧，且所述氧化物晶体管的栅极在所述衬底上的正投影与所述氧化物晶体管的有源层在所述衬底上 的正投影至少部分交叠。
可选的，所述氧化物晶体管的栅极在所述衬底上的正投影位于所述氧化物晶体管的有源层在所述衬底上的正投影以内。
可选的，所述阵列基板还包括栅绝缘层，所述栅绝缘层设置在所述氧化物晶体管的有源层和所述氧化物晶体管的栅极之间，且所述栅绝缘层为富氧氧化物层。
可选的，所述氧化物晶体管还包括连接电极，所述连接电极设置在所述氧化物晶体管的栅极远离所述衬底的一侧、且与所述氧化物晶体管的有源层电连接。
可选的，所述子像素还包括遮光部，所述遮光部设置在所述氧化物晶体管的有源层靠近所述衬底的一侧、且所述氧化物晶体管的有源层在所述衬底上的正投影位于所述遮光部在所述衬底上的正投影以内，所述像素电极在所述衬底上的正投影与述遮光部在所述衬底上的正投影部分交叠。
可选的，所述多晶硅晶体管的栅极与所述遮光部同层设置。
可选的，所述子像素还包括开口区以及与所述开口区相连的非开口区；
所述氧化物晶体管设置在所述非开口区，所述像素电极包括第一子电极和第二子电极，所述第一子电极的两侧分别与所述第二子电极和所述氧化物晶体管的有源层相接触，所述第一子电极设置在所述非开口区，所述第二子电极设置在所述开口区。
可选的，所述子像素的所述开口区还包括第一钝化部和公共电极；
所述第一钝化部覆盖所述第二子电极，所述公共电极设置在所述第一钝化部远离所述第二子电极一侧。
可选的，所述像素电极为面状电极，所述公共电极包括至少一个条形子电极。
可选的，所述阵列基板还包括第二钝化部，所述第二钝化部覆盖所述多晶硅晶体管和所述氧化物晶体管。
可选的，所述阵列基板还包括衬底和平坦部，所述平坦部位于设置在所述第二钝化部靠近所述衬底的一侧，且所述平坦部在所述衬底上的正投影与所述第一钝化部在所述衬底上的正投影不交叠。
可选的，所述显示区还包括衬底、以及设置在所述衬底上的多条栅线和多条数据线；
所述栅线沿垂直于所述衬底的方向与所述氧化物晶体管的有源层交叠 的部分为所述氧化物晶体管的栅极；所述栅线与所述多晶硅晶体管的第一极和第二极同层设置；
所述数据线沿垂直于所述衬底的方向与所述氧化物晶体管的有源层交叠的部分为所述氧化物晶体管的连接电极。
另一方面，提供了一种显示面板，包括上述的阵列基板。
再一方面，提供了一种阵列基板的制备方法，包括：
形成至少一个多晶硅晶体管和阵列排布的多个子像素；其中，所述多晶硅晶体管设置在所述阵列基板的非显示区，所述子像素设置在所述阵列基板的显示区、且包括氧化物晶体管和像素电极；
形成所述多晶硅晶体管和所述子像素包括：
采用一次构图工艺形成所述氧化物晶体管的有源层与所述像素电极；其中，所述氧化物晶体管的有源层与所述像素电极相接触；所述氧化物晶体管的有源层包括氧化物半导体材料，所述像素电极包括氧化物导体材料；
采用一次构图工艺形成所述氧化物晶体管的栅极与所述多晶硅晶体管的第一极和第二极。
可选的，所述采用一次构图工艺形成所述氧化物晶体管的有源层与所述像素电极包括：
采用一次构图工艺形成氧化物半导体层；
对所述氧化物半导体层中待导体化的部分进行导体化处理，形成所述氧化物晶体管的有源层与所述像素电极。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种阵列基板的结构示意图；
图2为本申请实施例提供的另一种阵列基板的结构示意图；
图3为本申请实施例提供的又一种阵列基板的结构示意图；
图4-13为本申请实施例提供的一种制备如图13结构的流程结构图；
图14为本申请实施例提供的再一种阵列基板的结构示意图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的实施例中，采用“第一”、“第二”、“第三”等字样对功能和作用基本相同的相同项或相似项进行区分，仅为了清楚描述本申请实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
在本申请的实施例中，“多个”的含义是两个或两个以上，“至少一个”的含义是一个或一个以上，除非另有明确具体的限定。
在本申请的实施例中，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
本申请实施例提供了一种阵列基板，参考图1所示，该阵列基板包括：显示区(图1所示的AA区)以及与显示区相连的非显示区(图1所示的OA区)；显示区包括阵列排布的多个子像素1。
其中，参考图2所示，非显示区包括至少一个多晶硅晶体管2；子像素包括氧化物晶体管3和像素电极22。
参考图2所示，氧化物晶体管3的栅极27与多晶硅晶体管2的第一极25和第二极26同层设置；氧化物晶体管3的有源层21与像素电极22同层设置且相接触；氧化物晶体管3的有源层21包括氧化物半导体材料，像素电极22包括氧化物导体材料。
上述显示区是指用于实现显示的区域，非显示区一般用于设置驱动电路，例如：GOA(Gate Driver on Array，阵列基板行驱动)驱动电路等。非显示区和显示区的具体位置关系不做限定，示例的，非显示区可以如图1所示，设置在显示区的一侧、且与显示区的一侧相连；或者，非显示区还可以围绕显示区设置、与显示区的周侧均相连；当然，还可以是其它设置方式，这里不再一一列举，具体可以根据实际要求确定。
上述多晶硅晶体管可以应用在GOA驱动电路，或者其它驱动电路，这 里不做限定。另外，多晶硅晶体管的类型不做限定，其可以是顶栅型多晶硅晶体管，或者，还可以是底栅型多晶硅晶体管。图2中以顶栅型多晶硅晶体管为例进行绘示。该多晶硅晶体管可以包括栅极、源极和漏极，将源极和漏极中的一个称为第一极、另一个称为第二极。根据电极的位置关系可以将晶体管分为两类。一类是栅极位于源极和漏极的下面，这类称之为底栅型薄膜晶体管；一类是栅极位于源极和漏极的上面，这类称之为顶栅型薄膜晶体管。
该氧化物晶体管的有源层的材料可以是IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)或者ITZO(Indium Tin Zinc Oxide，铟锡锌氧化物)等金属氧化物。
上述同层设置是指采用一次构图工艺制作。一次构图工艺是指经过一次曝光形成所需要的层结构工艺。一次构图工艺包括掩膜、曝光、显影、刻蚀和剥离等工艺。
上述氧化物晶体管的有源层包括氧化物半导体材料，像素电极包括氧化物导体材料，其中，氧化物导体材料可以通过对氧化物半导体材料进行导体化处理后形成，示例的，可以采用等离子工艺对氧化物半导体材料进行处理。
相关技术中，氧化物晶体管包括栅极、源极和漏极，其中漏极与像素电极电连接，源极与数据线电连接；在氧化物晶体管的控制下，实现将数据线的数据信号传输至像素电极。
本申请中，氧化物晶体管的有源层与像素电极同层设置且相接触，那么可以避免设置漏极，一方面可以减少Mask工艺，降低了制作工艺的复杂度。另一方面，相关技术中漏极多采用不透光金属制作，从而降低了透过率和开口率；而本申请中，无需额外设置漏极，同时，像素电极包括氧化物导体材料，而氧化物导体材料的透过率较高，从而大幅提升了透过率和开口率。另外，本申请中氧化物晶体管的栅极与多晶硅晶体管的第一极和第二极同层设置，可以进一步减少Mask工艺，简化工艺复杂度。本申请提供的阵列基板具有开口率高，制作工艺简单，生产成本低的特点。
可选的，阵列基板还包括衬底，多晶硅晶体管和子像素设置在衬底的同一侧。
为了进一步简化结构，参考图2所示，多晶硅晶体管2为顶栅型多晶硅晶体管，氧化物晶体管3的栅极27设置在氧化物晶体管3的有源层21远离衬底11的一侧，且参考图13所示，氧化物晶体管3的栅极27在衬底11上的正投影E1与氧化物晶体管3的有源层21在衬底11上的正投影E2至少 部分交叠。
上述氧化物晶体管的栅极在衬底上的正投影与氧化物晶体管的有源层在衬底上的正投影至少部分交叠包括：氧化物晶体管的栅极在衬底上的正投影与氧化物晶体管的有源层在衬底上的正投影部分交叠，此时，氧化物晶体管的栅极沿垂直于衬底方向与氧化物晶体管的有源层部分交叠；或者，氧化物晶体管的栅极在衬底上的正投影位于氧化物晶体管的有源层在衬底上的正投影以内，此时，氧化物晶体管的栅极沿垂直于衬底方向与氧化物晶体管的有源层完全交叠。图13以后者为例进行绘示。
可选的，为了增加沟道长度，以提高氧化物晶体管的性能，参考图13所示，氧化物晶体管3的栅极27在衬底11上的正投影E1位于氧化物晶体管3的有源层21在衬底11上的正投影E2以内。
可选的，为了保护有源层，参考图2所示，阵列基板还包括栅绝缘层20，栅绝缘层20设置在氧化物晶体管3的有源层21和氧化物晶体管3的栅极27之间，且栅绝缘层为富氧氧化物层。
上述栅绝缘层的材料和厚度均不作限定，示例的，可以采用二氧化硅制作，厚度范围为
Figure PCTCN2022079200-appb-000001
上述像素电极可以通过对氧化物半导体材料进行导体化处理后形成，在上述阵列基板的制作工艺中，可以在像素电极所在位置先形成氧化物半导体材料，接着在形成栅绝缘层的同时，采用还原性气体(例如：氢气)完成等离子处理，以使得氧化物半导体材料导体化，从而形成像素电极。为了避免氧化物晶体管的有源层导体化，可以采用富氧氧化物层以中和多余的H(氢)。
可选的，参考图2所示，氧化物晶体管3还包括连接电极30，连接电极30设置在氧化物晶体管3的栅极27远离衬底11的一侧、且与氧化物晶体管3的有源层21电连接。
相关技术中，氧化物晶体管一般包括栅极、源极、漏极三个电极；而本申请中，氧化物晶体管包括栅极和连接电极两个电极，结构更加简单，从而降低工艺复杂度。
该阵列基板应用在液晶显示面板时，背光模组发出的光线会照射到氧化物晶体管的有源层上，而氧化物晶体管的有源层容易受光照影响从而降低晶体管的特性，为了防止光线影响有源层，可选的，参考图2所示，子像素还包括遮光部16，遮光部16设置在氧化物晶体管3的有源层21靠近衬底11的一侧、且参考图13所示，氧化物晶体管3的有源层21在衬底11上的正 投影E2位于遮光部16在衬底11上的正投影E3以内，像素电极22在衬底11上的正投影E4与遮光部16在衬底11上的正投影E3部分交叠。
上述遮光部的材料可以选择不透光的金属，例如：铜、铝、银等。
该遮光部能够阻挡射向有源层的光线，从而避免有源层受到光线影响，进而提高了晶体管特性。
进一步可选的，为了进一步简化工艺，减少Mask工艺次数，多晶硅晶体管的栅极与遮光部同层设置，即可以通过一次构图工艺形成多晶硅晶体管的栅极与遮光部。
在一个或者多个实施例中，参考图2所示，子像素还包括开口区(OC区)以及与开口区相连的非开口区(OB区)。
参考图2所示，氧化物晶体管3设置在非开口区(OB区)，像素电极22包括第一子电极221和第二子电极222，第一子电极221的两侧分别与第二子电极222和氧化物晶体管3的有源层21相接触，第一子电极221设置在非开口区(OB区)，第二子电极222设置在开口区(OC区)。
上述像素电极可以通过对氧化物半导体材料进行等离子处理后形成，在等离子处理过程中，由于离子扩散作用，使得栅绝缘层下方的部分氧化物半导体材料也发生导体化，从而形成第一子电极；相较于仅在开口区设置像素电极的基板，本申请中，像素电极的设置面积更大，从而可以与公共电极形成更大的交叠面积，进而提高电容和液晶分子的驱动效果。另外，由于氧化物晶体管包括栅极和连接电极两个电极，无需设置第三个电极，因此，在原有子像素所占面积不变的情况下，可以减少非开口区的面积，增加开口区的面积，从而提高开口率。
可选的，参考图2所示，子像素的开口区(OC区)还包括第一钝化部321和公共电极；第一钝化部321覆盖第二子电极222，公共电极设置在第一钝化部321远离第二子电极222一侧。
上述公共电极可以包括至少一个条形子电极，图2以公共电极包括2个条形子电极33为例进行绘示。
本申请可以通过控制第一钝化部的厚度来控制像素电容，上述第一钝化部的厚度不做限定，示例的，该第一钝化部的厚度范围可以是
Figure PCTCN2022079200-appb-000002
这里对于第一钝化部的层数也不做限定，示例的，第一钝化部可以仅包括一层结构，例如：二氧化硅层或者氮化硅层；或者还可以包括多层叠层结构，例如：二氧化硅层和氮化硅层两层叠层结构。图2以第一钝化部包括一 层结构为例进行绘示。
将上述阵列基板应用在液晶显示面板中，公共电极和像素电极之间可以形成电场，以驱动液晶分子的偏转。
可选的，为了提高像素电极和公共电极之间的电场强度，像素电极为面状电极，公共电极包括至少一个条形子电极。
这里对于条形子电极的数量不做限定，具体可以根据实际要求选择。
可选的，为了更好地保护多晶硅晶体管和氧化物晶体管，参考图2所示，阵列基板还包括第二钝化部322，第二钝化部322覆盖多晶硅晶体管2和氧化物晶体管3。
为了简化工艺，上述第二钝化部和第一钝化部的材料可以相同，且可以通过一次沉积形成。
可选的，为了获得平坦化的表面，以利于后续工艺，参考图2所示，阵列基板还包括衬底11和平坦部31，平坦部31位于设置在第二钝化部322靠近衬底11的一侧，且平坦部31在衬底11上的正投影与第一钝化部321在衬底11上的正投影不交叠。
上述平坦部在衬底上的正投影与第一钝化部在衬底上的正投影不交叠，即说明在开口区不设置平坦部，相较于在开口区设置平坦部的基板，透过率可以提高约12％。
需要说明的是，形成上述平坦部需要一道Mask，为了进一步简化工艺，参考图14所示，在第二钝化部322靠近衬底11的一侧不再设置平坦部31。
在一个或者多个实施例中，参考图3所示，显示区还包括衬底(图3未示出)、以及设置在衬底上的多条栅线4和多条数据线5。
参考图3所示，栅线4沿垂直于衬底的方向与氧化物晶体管的有源层21交叠的部分为氧化物晶体管的栅极27；栅线与多晶硅晶体管的第一极和第二极同层设置。
参考图3所示，数据线5沿垂直于衬底的方向与氧化物晶体管的有源层21交叠的部分为氧化物晶体管的连接电极30。
上述栅线沿垂直于衬底的方向与氧化物晶体管的有源层交叠的部分作为氧化物晶体管的栅极，可以不用再单独设置栅极，进一步简化了工艺，同时节省空间，有利于开口率的提高；同时，栅线与多晶硅晶体管的第一极和第二极同层设置，可以减少Mask工艺次数，进一步降低工艺难度。
上述数据线沿垂直于衬底的方向与氧化物晶体管的有源层交叠的部分 作为氧化物晶体管的连接电极，可以不用再单独设置连接电极，进一步简化了工艺，同时节省空间，有利于开口率的提高。
需要说明的是，参考图2所示，上述阵列基板还可以包括缓冲层12、第一绝缘层14、第一层间介质层17、第二层间介质层28等结构，这里仅介绍与发明点相关的内容，其余结构可以参考相关技术获取，这里不再详细说明。
本申请实施例还提供了一种显示面板，包括上述的阵列基板。该显示面板可以是TN(Twisted Nematic，扭曲向列)型、VA(Vertical Alignment，垂直取向)型、IPS(In-Plane Switching，平面转换)型或ADS(Advanced Super Dimension Switch，高级超维场转换)型等液晶显示面板、以及包括这些显示面板的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
另外，显示面板还可以包括彩膜基板、液晶等该阵列基板其他结构，这里仅介绍与发明点相关的内容，其余结构可以参考相关技术获取，这里不再详细说明。
本申请实施例又提供了一种的阵列基板的制备方法，包括：
S01、形成至少一个多晶硅晶体管和阵列排布的多个子像素；其中，多晶硅晶体管设置在阵列基板的非显示区，子像素设置在阵列基板的显示区、且包括氧化物晶体管和像素电极。
上述S01中，形成多晶硅晶体管和子像素包括：
S011、采用一次构图工艺形成氧化物晶体管的有源层与像素电极；其中，氧化物晶体管的有源层与像素电极相接触；氧化物晶体管的有源层包括氧化物半导体材料，像素电极包括氧化物导体材料。
S012、采用一次构图工艺形成氧化物晶体管的栅极与多晶硅晶体管的第一极和第二极。
上述制备方法简单易实现，通过上述方法形成的阵列基板中，氧化物晶体管的有源层与像素电极同层设置且相接触，那么可以避免设置漏极，一方面可以减少Mask工艺，降低了制作工艺的复杂度。另一方面，相关技术中漏极多采用不透光金属制作，从而降低了透过率和开口率；而本申请中，无需额外设置漏极，同时，像素电极包括氧化物导体材料，而氧化物导体材料的透过率较高，从而大幅提升了透过率和开口率。另外，本申请中氧化物晶体管的栅极与多晶硅晶体管的第一极和第二极同层设置，可以进一步减少Mask工艺，简化工艺复杂度。本申请提供的阵列基板具有开口率高，制作工 艺简单，生产成本低的特点。
进一步可选的，S011、采用一次构图工艺形成氧化物晶体管的有源层与像素电极包括：
S0111、采用一次构图工艺形成氧化物半导体层。
S0112、对氧化物半导体层中待导体化的部分进行导体化处理，形成氧化物晶体管的有源层与像素电极。
这里对于导体化处理的具体工艺不做限定，示例的，采用还原性气体(例如：氢气)完成等离子处理，以使得氧化物半导体中待导体化的部分导体化。
通过执行S0111和S0112，可以形成氧化物晶体管的有源层与像素电极，该方法简单易实现，可操作性强。
下面以图13所示的阵列基板为例，说明其具体的制备方法。该方法包括：
S101、参考图4所示，在衬底11上依次形成缓冲层12、多晶硅晶体管的有源层13。
上述衬底可以是刚性衬底，例如：玻璃衬底。上述多晶硅晶体管的有源层材料可以是低温多晶硅材料。上述缓冲层的材料可以是氧化硅或者氮化硅等。
形成上述有源层的具体方法不做限定，示例的，可以先形成非晶硅层(a-Si)，然后采用准分子激光退火工艺(Excimer Laser Annealing，ELA)使得非晶硅层转换为多晶硅层，接着图案化后形成图4所示的有源层13。
S101中，形成多晶硅晶体管的有源层需要一道Mask。
S102、参考图5所示，在多晶硅晶体管的有源层13上形成第一绝缘层14、多晶硅晶体管的栅极15和遮光部16。
S102中，采用一次构图工艺形成多晶硅晶体管的栅极15和遮光部16，需要一道Mask。
S103、参考图6所示，形成第一层间介质层17，其中，该第一层间介质层覆盖多晶硅晶体管的栅极15和遮光部16。
上述第一层间介质层可以包括单层结构；或者，还可以包括多层叠层结构；示例的，第一层间介质层包括第一氧化硅层、氮化硅层和第二氧化硅层三层叠层结构，其中，第一氧化硅层相较第二氧化硅层靠近衬底；第一氧化硅层的厚度范围为
Figure PCTCN2022079200-appb-000003
氮化硅层的厚度范围为
Figure PCTCN2022079200-appb-000004
第二氧化硅层的厚度范围为
Figure PCTCN2022079200-appb-000005
图6以第一层间介质层包括单层结构 为例进行绘示。
S104、参考图7所示，在第一层间介质层17上形成氧化物半导体层18。
该氧化物半导体层18的材料可以是IGZO，厚度范围可以是
Figure PCTCN2022079200-appb-000006
该氧化物半导体层可以包括单层结构；或者，还可以包括多层叠层结构；示例的，氧化物半导体层包括第一氧化物半导体子层和第二氧化物半导体子层，其中，第一氧化物半导体子层相较第二氧化物半导体子层靠近衬底，第一氧化物半导体子层为致密层。图7以氧化物半导体层包括单层结构为例进行绘示。
S104形成氧化物半导体层需要一道Mask。
S105、参考图8所示，沉积一层栅绝缘薄膜19；其中，该栅绝缘薄膜的材料为二氧化硅，厚度范围为
Figure PCTCN2022079200-appb-000007
S106、对图8所示的栅绝缘薄膜19进行刻蚀工艺，以形成图9所示的栅绝缘层20、以及像素电极22；其中，像素电极22包括第一子电极221和第二子电极222。
在上述刻蚀工艺中，能够使得氧化物半导体层18的部分导体化，由于粒子扩散作用，使得栅绝缘层20下方的部分氧化物半导体层也导体化，从而形成了第一子电极221；同时经过刻蚀工艺后，还形成了如图9所示的第一过孔23和第二过孔24。
S106形成栅绝缘层需要一道Mask，形成第一过孔和第二过孔需要一道Mask，共计2道Mask。
S107、参考图10所示，形成氧化物晶体管3的栅极27与多晶硅晶体管2的第一极25和第二极26。
S107通过一次构图工艺形成氧化物晶体管的栅极与多晶硅晶体管的第一极和第二极，需要一道Mask。
S108、形成如图11所示的第二层间介质层28。
该第二层间介质层可以包括单层结构；或者，还可以包括多层叠层结构；示例的，第二层间介质层包括氧化硅层和氮化硅层两层叠层结构；图11以第二层间介质层包括单层结构为例进行绘示。第二层间介质层的厚度范围为
Figure PCTCN2022079200-appb-000008
在S108中，在形成第二层间介质层28的同时，还形成了第三过孔29。S108形成第二层间介质层需要一道Mask。
S109、形成如图12所示的氧化物晶体管的连接电极30；该步骤需要一 道Mask。
S110、形成如图13所示的平坦部31、第一钝化部321、第二钝化部322和公共电极，其中，公共电极包括2个条形子电极33。
本申请可以通过控制第一钝化部的厚度来控制像素电容，上述第一钝化部的厚度不做限定，示例的，该第一钝化部的厚度范围可以是
Figure PCTCN2022079200-appb-000009
第一钝化部可以仅包括一层结构，例如：二氧化硅层或者氮化硅层；或者还可以包括多层叠层结构，例如：二氧化硅层和氮化硅层两层叠层结构。图2以第一钝化部包括一层结构为例进行绘示。
在S110中，形成平坦部需要一道Mask，形成公共电极需要一道Mask，共计两道Mask。
上述制备方法中，S101采用1道Mask，S102采用1道Mask，S104采用1道Mask，S106采用2道Mask，S107采用1道Mask，S108采用1道Mask，S109采用1道Mask，S110采用2道Mask，总共10道Mask。相比相关技术中采用15道以上Mask形成阵列基板，该制备方法的工艺复杂度和生产成本大幅降低，同时形成的阵列基板的开口率和透过率均有所提升。
需要说明的是，本申请实施例中涉及的阵列基板的相关结构说明，可以参考前述实施例，这里不再赘述。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本申请的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本申请的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (16)

  1. 一种阵列基板，其中，包括：显示区以及与所述显示区相连的非显示区；所述显示区包括阵列排布的多个子像素；
    其中，所述非显示区包括至少一个多晶硅晶体管；所述子像素包括氧化物晶体管和像素电极；
    所述氧化物晶体管的栅极与所述多晶硅晶体管的第一极和第二极同层设置；所述氧化物晶体管的有源层与所述像素电极同层设置且相接触；所述氧化物晶体管的有源层包括氧化物半导体材料，所述像素电极包括氧化物导体材料。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括衬底，所述多晶硅晶体管和所述子像素设置在所述衬底的同一侧；
    所述多晶硅晶体管为顶栅型多晶硅晶体管，所述氧化物晶体管的栅极设置在所述氧化物晶体管的有源层远离所述衬底的一侧，且所述氧化物晶体管的栅极在所述衬底上的正投影与所述氧化物晶体管的有源层在所述衬底上的正投影至少部分交叠。
  3. 根据权利要求2所述的阵列基板，其中，所述氧化物晶体管的栅极在所述衬底上的正投影位于所述氧化物晶体管的有源层在所述衬底上的正投影以内。
  4. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括栅绝缘层，所述栅绝缘层设置在所述氧化物晶体管的有源层和所述氧化物晶体管的栅极之间，且所述栅绝缘层为富氧氧化物层。
  5. 根据权利要求2所述的阵列基板，其中，所述氧化物晶体管还包括连接电极，所述连接电极设置在所述氧化物晶体管的栅极远离所述衬底的一侧、且与所述氧化物晶体管的有源层电连接。
  6. 根据权利要求2所述的阵列基板，其中，所述子像素还包括遮光部，所述遮光部设置在所述氧化物晶体管的有源层靠近所述衬底的一侧、且所述氧化物晶体管的有源层在所述衬底上的正投影位于所述遮光部在所述衬底上的正投影以内，所述像素电极在所述衬底上的正投影与述遮光部在所述衬底上的正投影部分交叠。
  7. 根据权利要求6所述的阵列基板，其中，所述多晶硅晶体管的栅极与所述遮光部同层设置。
  8. 根据权利要求1所述的阵列基板，其中，所述子像素还包括开口区 以及与所述开口区相连的非开口区；
    所述氧化物晶体管设置在所述非开口区，所述像素电极包括第一子电极和第二子电极，所述第一子电极的两侧分别与所述第二子电极和所述氧化物晶体管的有源层相接触，所述第一子电极设置在所述非开口区，所述第二子电极设置在所述开口区。
  9. 根据权利要求8所述的阵列基板，其中，所述子像素的所述开口区还包括第一钝化部和公共电极；
    所述第一钝化部覆盖所述第二子电极，所述公共电极设置在所述第一钝化部远离所述第二子电极一侧。
  10. 根据权利要求9所述的阵列基板，其中，所述像素电极为面状电极，所述公共电极包括至少一个条形子电极。
  11. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括第二钝化部，所述第二钝化部覆盖所述多晶硅晶体管和所述氧化物晶体管。
  12. 根据权利要求11所述的阵列基板，其中，所述阵列基板还包括衬底和平坦部，所述平坦部位于设置在所述第二钝化部靠近所述衬底的一侧，且所述平坦部在所述衬底上的正投影与所述第一钝化部在所述衬底上的正投影不交叠。
  13. 根据权利要求1所述的阵列基板，其中，所述显示区还包括衬底、以及设置在所述衬底上的多条栅线和多条数据线；
    所述栅线沿垂直于所述衬底的方向与所述氧化物晶体管的有源层交叠的部分为所述氧化物晶体管的栅极；所述栅线与所述多晶硅晶体管的第一极和第二极同层设置；
    所述数据线沿垂直于所述衬底的方向与所述氧化物晶体管的有源层交叠的部分为所述氧化物晶体管的连接电极。
  14. 一种显示面板，其中，包括权利要求1-13任一项所述的阵列基板。
  15. 根据权利要求1-13任一项所述的阵列基板的制备方法，其中，包括：
    形成至少一个多晶硅晶体管和阵列排布的多个子像素；其中，所述多晶硅晶体管设置在所述阵列基板的非显示区，所述子像素设置在所述阵列基板的显示区、且包括氧化物晶体管和像素电极；
    形成所述多晶硅晶体管和所述子像素包括：
    采用一次构图工艺形成所述氧化物晶体管的有源层与所述像素电极； 其中，所述氧化物晶体管的有源层与所述像素电极相接触；所述氧化物晶体管的有源层包括氧化物半导体材料，所述像素电极包括氧化物导体材料；
    采用一次构图工艺形成所述氧化物晶体管的栅极与所述多晶硅晶体管的第一极和第二极。
  16. 根据权利要求15所述的方法，其中，所述采用一次构图工艺形成所述氧化物晶体管的有源层与所述像素电极包括：
    采用一次构图工艺形成氧化物半导体层；
    对所述氧化物半导体层中待导体化的部分进行导体化处理，形成所述氧化物晶体管的有源层与所述像素电极。
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