WO2017049664A1 - 一种tft基板、tft开关管及其制造方法 - Google Patents

一种tft基板、tft开关管及其制造方法 Download PDF

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Publication number
WO2017049664A1
WO2017049664A1 PCT/CN2015/091283 CN2015091283W WO2017049664A1 WO 2017049664 A1 WO2017049664 A1 WO 2017049664A1 CN 2015091283 W CN2015091283 W CN 2015091283W WO 2017049664 A1 WO2017049664 A1 WO 2017049664A1
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Prior art keywords
disposed
semiconductor layer
storage electrode
insulating layer
gate
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PCT/CN2015/091283
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English (en)
French (fr)
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武岳
周志超
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深圳市华星光电技术有限公司
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Priority to US14/786,123 priority Critical patent/US20170160613A1/en
Publication of WO2017049664A1 publication Critical patent/WO2017049664A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
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    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
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    • G02F2202/00—Materials and properties
    • G02F2202/16—Materials and properties conductive
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2203/00—Function characteristic
    • G02F2203/01—Function characteristic transmissive

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT substrate, a TFT switch tube, and a method of fabricating the same.
  • TFT-LCD Thin Film Transistor Liquid Crystal
  • the electric field generated by the upper and lower substrates is controlled by a TFT switch tube to change the deflection direction of the liquid crystal molecules, thereby realizing the control of the light intensity of the transparent pixels.
  • a commonly used TFT switch tube is usually composed of three electrodes (gate, source, and drain), a gate insulating layer, and a semiconductor active layer. In actual production, considering the cycle of device performance, process and cost, four reticle or five reticle processes are generally used.
  • the source and drain electrodes are formed by the same mask. Since the industrial etching of metals is usually carried out by chemical methods, that is, using an etching solution, the distance between the source and drain electrodes is set too large, which may cause the TFT switch tube. The resistance is increased, the charging current is lowered, and the distance between the source and drain electrodes is set too small, which may cause a short circuit in the process of wet etching.
  • the technical problem to be solved by the present invention is to provide a TFT substrate, a TFT switch tube, and a manufacturing method thereof, which can reduce the risk of short circuit in the source and drain etching processes while ensuring low resistance of the TFT switch tube.
  • a technical solution adopted by the present invention is to provide a method for manufacturing a TFT switch tube, the method comprising: providing a substrate; providing a gate on the substrate; and providing a semiconductor layer above the gate; a semiconductor layer is provided with a source electrically connected to the semiconductor layer; a first insulating layer is disposed on the source, and a pixel electrode is disposed on the first insulating layer, and the pixel electrode is further disposed as a drain through the first insulating layer The first via is electrically connected to the semiconductor layer.
  • the step of disposing a gate on the substrate includes: disposing a first storage electrode disposed on the substrate in the same layer and spaced apart from the gate.
  • the step of disposing a semiconductor layer over the gate includes: disposing a second insulating layer on the gate, wherein a region of the second insulating layer corresponding to the first storage electrode is not covered by the semiconductor layer.
  • the step of disposing a source electrically connected to the semiconductor layer on the semiconductor layer further comprises: providing a second storage electrode in a region on the second insulating layer not covered by the semiconductor layer, such that the second storage electrode corresponds to the first storage electrode Settings.
  • the method further includes: the pixel electrode is further electrically connected to the second storage electrode through the second via hole disposed on the first insulating layer to charge the storage capacitor formed by the first storage electrode and the second storage electrode .
  • a TFT switch tube including: a substrate; a gate disposed on the substrate; a semiconductor layer disposed above the gate; a source, And disposed on the semiconductor layer and electrically connected to the semiconductor layer; the first insulating layer is disposed on the source, and the first via hole is disposed at a position corresponding to the semiconductor layer; the pixel electrode is disposed on the first insulating layer, and the pixel electrode is further The drain is electrically connected to the semiconductor layer through the first via.
  • the TFT switch tube further includes: a second insulating layer disposed on the gate.
  • the TFT switch tube further includes: a first storage electrode disposed on the substrate and disposed in the same layer and spaced apart from the gate, wherein the region of the second insulating layer corresponding to the first storage electrode is not covered by the semiconductor layer; the second storage The electrode is disposed on the second insulating layer in a region not covered by the semiconductor layer such that the second storage electrode is disposed corresponding to the first storage electrode.
  • the first insulating layer further defines a second via hole corresponding to the position of the second storage electrode, and the pixel electrode is further electrically connected to the second storage electrode through the second via hole to be used by the first storage electrode and the second storage electrode The formed storage capacitor is charged.
  • a TFT substrate including a TFT switch tube
  • the TFT switch tube includes: a substrate; a gate electrode disposed on the substrate; and a semiconductor layer disposed on the Above the gate; a source disposed on the semiconductor layer and electrically connected to the semiconductor layer; a first insulating layer disposed on the source and having a first via at a position corresponding to the semiconductor layer; and a pixel electrode disposed at the first On the insulating layer, the pixel electrode is further electrically connected to the semiconductor layer through the first via hole as a drain.
  • the TFT switch tube further includes: a second insulating layer disposed on the gate.
  • the TFT switch tube further includes: a first storage electrode disposed on the substrate and disposed in the same layer and spaced apart from the gate, wherein the region of the second insulating layer corresponding to the first storage electrode is not covered by the semiconductor layer; the second storage The electrode is disposed on the second insulating layer in a region not covered by the semiconductor layer such that the second storage electrode is disposed corresponding to the first storage electrode.
  • the first insulating layer further defines a second via hole corresponding to the position of the second storage electrode, and the pixel electrode is further electrically connected to the second storage electrode through the second via hole to be used by the first storage electrode and the second storage electrode The formed storage capacitor is charged.
  • the present invention provides a method for manufacturing a TFT switch tube.
  • the method is specifically: firstly, a gate is disposed on the substrate, and a semiconductor layer is further disposed above the gate. Then, a source electrically connected to the semiconductor layer is disposed on the semiconductor layer, and finally a first insulating layer is disposed on the source, and a pixel electrode is disposed on the first insulating layer, and the pixel electrode is further disposed as a drain through the first insulating layer The first via on the layer is electrically connected to the semiconductor layer.
  • the source and the drain of the TFT switch of the present invention are disposed in different layers, so that the distance between the source and the drain is relatively close, and there is no risk of etching short circuit, so the present invention ensures the TFT.
  • the risk of short circuit in the source and drain etching processes can be reduced at the same time.
  • the first insulating layer is added between the drain and the gate, the insulation between the drain and the gate is increased, thereby reducing the parasitic capacitance between the drain and the gate.
  • FIG. 1 is a flowchart of a method for manufacturing a TFT switch tube according to an embodiment of the present invention
  • FIG. 2 is a process flow diagram corresponding to the manufacturing method shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a TFT switch tube according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a display device according to an embodiment of the present invention.
  • FIG. 1 is a flowchart of a method for manufacturing a TFT switch tube according to an embodiment of the present invention. As shown in FIG. 1, the method of this embodiment includes the following steps:
  • Step S1 providing a substrate 11.
  • the substrate 11 is preferably a glass substrate, and the glass substrate is further cleaned and dried before the glass substrate is provided to provide a clean glass substrate.
  • Step S2 A gate electrode 121 is provided on the substrate 11.
  • a first storage electrode 122 is disposed on the substrate 11 in the same layer and spaced apart from the gate 121.
  • first pass PVD Physical Vapor Deposition, physical vapor deposition, depositing a metal layer 12, then patterning the metal layer 12 by photolithography, and then forming the same layer and spaced gates 121 and etched by etching and stripping.
  • a storage electrode 122 In order to save cost, the etching used in this step is wet etching.
  • Step S3 A semiconductor layer 131 is disposed over the gate electrode 121.
  • the material of the semiconductor layer 131 is preferably an indium gallium zinc oxide compound (a-IGZO) film.
  • a second insulating layer 17 is further disposed on the gate electrode 121 before this step. Therefore, this step specifically includes disposing the semiconductor layer 131 on the second insulating layer 17.
  • the method of disposing the semiconductor layer 131 is specifically to deposit a layer of the IGZO thin film 13 by means of PVD, and then photolithography, etching and stripping the IGZO thin film 13 to form the semiconductor layer 131. Among them, in order to save cost, the etching used in this step is wet etching. The region of the second insulating layer 17 corresponding to the first storage electrode 122 is not covered by the semiconductor layer 131.
  • Step S4 A source electrode 141 electrically connected to the semiconductor layer 131 is provided on the semiconductor layer 131.
  • the second storage electrode 142 is further disposed on the second insulating layer 17 in a region not covered by the semiconductor layer 131, so that the second storage electrode 142 is disposed corresponding to the first storage electrode 122 to form a storage capacitor.
  • first pass PVD Physical Vapor Deposition, physical vapor deposition, a metal layer 14 is deposited, and then the metal layer 14 is photo-printed to pattern the metal layer 14, and the source electrode 141 and the second storage electrode 142 are formed by etching and stripping.
  • the etching used in this step is wet etching.
  • Step S5 a first insulating layer 15 is disposed on the source 141, and a pixel electrode 161 is disposed on the first insulating layer 15.
  • the pixel electrode 161 further serves as a drain through the first via disposed on the first insulating layer 15.
  • 151 is electrically connected to the semiconductor layer 131.
  • the material of the pixel electrode is preferably ITO (Indium Tin oxide, indium tin oxide) transparent film.
  • the first insulating layer 15 is deposited on the source 141, and the first via hole 151 is formed by photolithography, etching, and stripping at the position of the corresponding semiconductor layer 131 on the first insulating layer 15. Then, an ITO transparent film 16 is deposited on the first insulating layer 15, and the ITO transparent film 16 is patterned by photolithography, and the pixel electrode 161 is formed by etching and stripping. Among them, in order to save cost, the etching used in this step is wet etching.
  • first through hole 151 is disposed on the first insulating layer 15, when the ITO transparent film 16 is deposited on the first insulating layer 15, the ITO transparent film 16 at the position of the first through hole 151 will pass through.
  • the first via hole 151 is electrically connected to the semiconductor layer 131.
  • the second via hole 152 is formed at the position of the corresponding second storage electrode 142 of the first insulating layer 15 by the same process while forming the first via hole 151.
  • the pixel electrode 161 is further electrically connected to the second storage electrode 142 through the second via hole 152 to charge the storage capacitor formed by the first storage electrode 122 and the second storage electrode 142.
  • the source electrode 141 of the TFT switching transistor of the present invention and the pixel electrode 161 as the drain are disposed in different layers such that the distance between the source electrode 141 and the pixel electrode 161 as the drain is set relatively close. There is also no risk of etch shorts, so the present invention can reduce the risk of short circuit during source 141 and drain etching while ensuring low resistance of the TFT switch.
  • first insulating layer 15 and the second insulating layer 17 are disposed between the pixel electrode 161 as the drain and the gate electrode 121, the distance between the two is increased, thereby reducing the gap between the drain and the gate. Parasitic capacitance.
  • the present invention also provides a TFT switch tube which is fabricated by the manufacturing method described above. See Figure 3 for details.
  • the TFT switch 10 of the present embodiment includes a substrate 11, a gate 121, a semiconductor layer 131, a source 141, a first insulating layer 15, and a pixel electrode 16.
  • the gate 121 is disposed on the substrate 11.
  • the semiconductor layer 131 is disposed above the gate electrode 121.
  • the source electrode 141 is disposed on the semiconductor layer 131 and electrically connected to the semiconductor layer 131.
  • the first insulating layer 15 is disposed on the source electrode 141, and a first via hole 151 is disposed at a position corresponding to the semiconductor layer 131.
  • the pixel electrode 161 is disposed on the first insulating layer 15, and the pixel electrode 161 is further electrically connected to the semiconductor layer 131 through the first via hole 151 as a drain.
  • the TFT switch 10 further includes a second insulating layer 17.
  • the second insulating layer 17 is disposed on the gate electrode 121, that is, the semiconductor layer 131 is specifically disposed on the second insulating layer 17.
  • the TFT switch 10 further includes a first storage electrode 122 and a second storage electrode 142.
  • the first storage electrode 122 is disposed on the substrate 11 and is disposed in the same layer and spaced apart from the gate 121 .
  • the region of the second insulating layer 17 corresponding to the first storage electrode 122 is not covered by the semiconductor layer 131 .
  • the second storage electrode 142 is disposed on a region of the second insulating layer 17 that is not covered by the semiconductor layer 131 such that the second storage electrode 142 is disposed corresponding to the first storage electrode 122.
  • the first insulating layer 15 further defines a second via hole 152 corresponding to the position of the second storage electrode 142, and the pixel electrode 161 is further electrically connected to the second storage electrode 142 through the second via hole 152 to be used by the first storage layer
  • the storage capacitor formed by the electrode 122 and the second storage electrode 142 is charged.
  • the embodiment of the invention further provides a display device.
  • FIG. 4 is a schematic structural view of the display device.
  • the display device 40 includes a display panel 41 and a backlight module 42 that provides a backlight source to the display panel 41.
  • the display panel 41 further includes a TFT substrate 411, a color filter substrate 412, and a liquid crystal layer 413 between the TFT substrate 411 and the color filter substrate 412.
  • the TFT substrate 411 of the present embodiment includes the TFT switch tube 10 described above.
  • the source and the drain of the TFT switch of the present invention are disposed in different layers, so that the distance between the source and the drain is relatively close, and there is no risk of etching short circuit, so the present invention
  • the risk of short circuit in the source and drain etching processes can be reduced at the same time.
  • the distance between the drain and the gate is increased, thereby reducing the parasitic capacitance between the drain and the gate.

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Abstract

一种TFT基板（411）、TFT开关管（10）及其制造方法，该方法包括：提供一基板（11）；在基板（11）上设置栅极（121）；在栅极（121）上方设置一半导体层（131）；在半导体层（131）上设置与半导体层（131）电连的源极（141）；在源极（141）上设置一第一绝缘层（15），并在第一绝缘层（15）上设置像素电极（161），像素电极（161）进一步作为漏极通过设置在第一绝缘层（15）上的第一通孔（151）与半导体层（131）电连。通过上述方式，能够在保证TFT开关管（10）的电阻较低的情况下，降低源极（141）和漏极蚀刻过程中的短路风险。

Description

一种TFT基板、TFT开关管及其制造方法
【技术领域】
本发明涉及显示技术领域，尤其是涉及一种TFT基板、TFT开关管及其制造方法。
【背景技术】
在TFT-LCD（Thin Film Transistor Liquid Crystal Display薄膜晶体管液晶显示器）显示技术中，通过TFT开关管控制上、下基板产生的电场来改变液晶分子的偏转方向，从而实现对透明像素的光强的控制。常用的TFT开关管通常由三电极（栅极、源极以及漏极）、栅极绝缘层以及半导体活性层组成。在实际生产中，综合考虑器件性能、制程与成本的周期，一般采用四道光罩或者五道光罩制程。
目前的主流制程中，源、漏电极的形成用同一道光罩，由于工业对于金属的蚀刻通常采用化学方法，即采用蚀刻液进行，源、漏电极间的距离设置过大，会造成TFT开关管的电阻提高，降低充电电流，源、漏电极间的距离设置过小，会造成湿法蚀刻的过程中存在短路的风险。
【发明内容】
本发明主要解决的技术问题是提供一种TFT基板、TFT开关管及其制造方法，能够在保证TFT开关管的电阻较低的情况下，降低源极和漏极蚀刻过程中短路风险。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种TFT开关管的制造方法，该方法包括：提供一基板；在基板上设置栅极；在栅极上方设置一半导体层；在半导体层上设置与半导体层电连的源极；在源极上设置一第一绝缘层，并在第一绝缘层上设置像素电极，像素电极进一步作为漏极通过设置在第一绝缘层上的第一通孔与半导体层电连。
其中，在基板上设置栅极的步骤包括：在基板上设置一与栅极同层且间隔设置的第一存储电极。
其中，在栅极上方设置一半导体层的步骤之前包括：在栅极上设置一第二绝缘层，其中第二绝缘层的对应第一存储电极的区域未被半导体层覆盖。
其中，在半导体层上设置与半导体层电连的源极的步骤进一步包括：在第二绝缘层上的未被半导体层覆盖的区域设置第二存储电极，使得第二存储电极对应第一存储电极设置。
其中，方法还包括：像素电极进一步通过设置在第一绝缘层上的第二导通孔与第二存储电极电连，以向由第一存储电极和第二存储电极所形成的存储电容进行充电。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种TFT开关管，TFT开关管包括：基板；栅极，设置在基板上；半导体层，设置在栅极上方；源极，设置在半导体层上并与半导体层电连；第一绝缘层，设置在源极上，并在对应半导体层的位置设置第一通孔；像素电极，设置在第一绝缘层上，像素电极进一步作为漏极通过第一通孔与半导体层电连。
其中，TFT开关管进一步包括：第二绝缘层，设置在栅极上。
其中，TFT开关管进一步包括：第一存储电极，设置在基板上并与栅极同层且间隔设置，其中，第二绝缘层的对应第一存储电极的区域未被半导体层覆盖；第二存储电极，设置在第二绝缘层上的未被半导体层覆盖的区域，使得第二存储电极对应第一存储电极设置。
其中，第一绝缘层对应第二存储电极的位置进一步设置第二通孔，像素电极进一步通过第二导通孔与第二存储电极电连，以向由第一存储电极和第二存储电极所形成的存储电容进行充电。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种TFT基板，该TFT基板包括TFT开关管，TFT开关管包括：基板；栅极，设置在基板上；半导体层，设置在栅极上方；源极，设置在半导体层上并与半导体层电连；第一绝缘层，设置在源极上，并在对应半导体层的位置设置第一通孔；像素电极，设置在第一绝缘层上，像素电极进一步作为漏极通过第一通孔与半导体层电连。
其中，TFT开关管进一步包括：第二绝缘层，设置在栅极上。
其中，TFT开关管进一步包括：第一存储电极，设置在基板上并与栅极同层且间隔设置，其中，第二绝缘层的对应第一存储电极的区域未被半导体层覆盖；第二存储电极，设置在第二绝缘层上的未被半导体层覆盖的区域，使得第二存储电极对应第一存储电极设置。
其中，第一绝缘层对应第二存储电极的位置进一步设置第二通孔，像素电极进一步通过第二导通孔与第二存储电极电连，以向由第一存储电极和第二存储电极所形成的存储电容进行充电。
本发明的有益效果是：区别于现有技术的情况，本发明提供一种TFT开关管的制造方法，该方法具体为：首先在基板上设置栅极，进一步在栅极上方设置一半导体层，然后在半导体层上设置与半导体层电连的源极，最后在源极上设置一第一绝缘层，并在第一绝缘层上设置像素电极，像素电极进一步作为漏极通过设置在第一绝缘层上的第一通孔与半导体层电连。因此，本发明的TFT开关管的源极和漏极为不同层设置，使得在源极和漏极的距离设置得较近的情况下，也不会存在蚀刻短路的风险，所以本发明在保证TFT开关管的电阻较低的情况下，同时能降低源极和漏极蚀刻过程中短路风险。进一步的，由于漏极与栅极之间增加了第一绝缘层，加大了漏极和栅极之间的绝缘度，因此降低了漏极和栅极之间的寄生电容。
【附图说明】
图1是本发明实施例提供的一种TFT开关管的制造方法的流程图；
图2是对应图1所示的制造方法的工艺制程图；
图3是本发明实施例提供的一种TFT开关管的结构示意图；
图4是本发明实施例提供的一种显示装置的结构示意图。
【具体实施方式】
请参阅图1，图1是本发明实施例提供的一种TFT开关管的制造方法的流程图。如图1所示，本实施例的方法包括以下步骤：
步骤S1：提供一基板11。
本步骤中，基板11优选为玻璃基板，在提供玻璃基板之前进一步将玻璃基板进行清洗和烘干等操作，以提供一干净的玻璃基板。
步骤S2：在基板11上设置栅极121。
本步骤中，进一步在基板11上设置一与栅极121同层且间隔设置的第一存储电极122。
具体为，首先通过PVD(Physical Vapor Deposition，物理气相沉)积沉积一金属层12，然后对该金属层12进行影印方式来图案化该金属层12，进而通过蚀刻和脱膜方式来形成同层且间隔设置的栅极121和第一存储电极122。其中，为了节约成本，本步骤中使用的蚀刻为湿蚀刻。
步骤S3：在栅极121上方设置一半导体层131。
其中，半导体层131的材料优选为铟镓锌氧化合物(a-IGZO)薄膜。
在本步骤之前进一步在栅极121上设置一第二绝缘层17。因此本步骤具体为在第二绝缘层17上设置半导体层131。其中，设置半导体层131的方式具体为：通过PVD的方式沉积一层IGZO薄膜13，然后对该IGZO薄膜13进行影印、蚀刻和脱膜方式来形成半导体层131。其中，为了节约成本，本步骤中使用的蚀刻为湿蚀刻。其中第二绝缘层17的对应第一存储电极122的区域未被半导体层131覆盖。
步骤S4：在半导体层131上设置与半导体层131电连的源极141。
本步骤中，进一步在第二绝缘层17上的未被半导体层131覆盖的区域设置第二存储电极142，使得第二存储电极142对应第一存储电极122设置形成存储电容。
具体为，首先通过PVD(Physical Vapor Deposition，物理气相沉)积沉积一金属层14，然后对该金属层14进行影印方式来图案化该金属层14，进而通过蚀刻和脱膜方式来形成源极141和第二存储电极142。其中，为了节约成本，本步骤中使用的蚀刻为湿蚀刻。
步骤S5：在源极141上设置一第一绝缘层15，并在第一绝缘层15上设置像素电极161，像素电极161进一步作为漏极通过设置在第一绝缘层15上的第一通孔151与半导体层131电连。其中，像素电极的材质优选为ITO（Indium tin oxide，氧化铟锡）透明薄膜。
具体的，在源极141上沉积第一绝缘层15，并在第一绝缘层15上的对应半导体层131的位置通过影印、蚀刻和脱膜方式形成第一通孔151。然后在第一绝缘层15上沉积一层ITO透明薄膜16，并通过影印方式图案化该ITO透明薄膜16，进而通过蚀刻和脱膜方式来形成像素电极161。其中，为了节约成本，本步骤中使用的蚀刻为湿蚀刻。
应理解，由于在第一绝缘层15上设置了第一通孔151，因此在第一绝缘层15上沉积ITO透明薄膜16时，在第一通孔151位置处的ITO透明薄膜16将穿过第一通孔151而与半导体层131电联。
进一步的，在形成第一通孔151的同时还通过同样的工艺在第一绝缘层15的对应第二存储电极142的位置形成第二通孔152。使得像素电极161进一步通过第二导通孔152与第二存储电极142电连，以向由第一存储电极122和第二存储电极142所形成的存储电容进行充电。
承前所述，本发明的TFT开关管的源极141和作为漏极的像素电极161为不同层设置，使得在源极141和作为漏极的像素电极161的距离设置得较近的情况下，也不会存在蚀刻短路的风险，所以本发明在保证TFT开关管的电阻较低的情况下，同时能降低源极141和漏极蚀刻过程中短路风险。
进一步的，由于作为漏极的像素电极161与栅极121之间设置了第一绝缘层15和第二绝缘层17，加大了两者之间距离，因此降低了漏极和栅极之间的寄生电容。
本发明实施还提供了一种TFT开关管，该TFT开关管由前文所述的制造方法制成。具体请参阅图3。
如图3所示，本实施例的TFT开关管10包括基板11、栅极121、半导体层131、源极141、第一绝缘层15以及像素电极16。
其中，栅极121设置在基板11上。半导体层131设置在栅极121上方。源极141设置在半导体层131上并与半导体层131电连。
第一绝缘层15设置在源极141上，并在对应半导体层131的位置设置第一通孔151。像素电极161设置在第一绝缘层15上，像素电极161进一步作为漏极通过第一通孔151与半导体层131电连。
进一步的，TFT开关管10进一步包括第二绝缘层17。第二绝缘层17设置在栅极121上，也就是半导体层131具体是设置在第二绝缘层17上。
进一步的，TFT开关管10进一步包括第一存储电极122和第二存储电极142。其中，第一存储电极122设置在基板11上并与栅极121同层且间隔设置，其中，第二绝缘层17的对应第一存储电极122的区域未被半导体层131覆盖。第二存储电极142设置在第二绝缘层17上的未被半导体层131覆盖的区域，使得第二存储电极142对应第一存储电极122设置。
进一步的，第一绝缘层15对应第二存储电极142的位置进一步设置第二通孔152，像素电极161进一步通过第二导通孔152与第二存储电极142电连，以向由第一存储电极122和第二存储电极142所形成的存储电容进行充电。
本发明实施例还提供了一种显示装置，请参阅图4，图4是显示装置的结构示意图。如图4所示，显示装置40包括显示面板41和背光模组42，背光模组42向显示面板41提供背光光源。其中显示面板41进一步包括相对设置的TFT基板411、彩膜基板412以及TFT基板411和彩膜基板412之间的液晶层413。本实施例的TFT基板411包括前文所述的TFT开关管10。
综上所述，本发明的TFT开关管的源极和漏极为不同层设置，使得在源极和漏极的距离设置得较近的情况下，也不会存在蚀刻短路的风险，所以本发明在保证TFT开关管的电阻较低的情况下，同时能降低源极和漏极蚀刻过程中短路风险。
进一步的，由于漏极与栅极之间包括了第一绝缘层和第二绝缘层，加大了漏极和栅极之间的距离，因此降低了漏极和栅极之间的寄生电容。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种TFT开关管的制造方法，其中，所述方法包括：
    提供一基板；
    在所述基板上设置栅极；
    在所述栅极上方设置一半导体层；
    在所述半导体层上设置与所述半导体层电连的源极；
    在所述源极上设置一第一绝缘层，并在所述第一绝缘层上设置像素电极，所述像素电极进一步作为漏极通过设置在所述第一绝缘层上的第一通孔与所述半导体层电连。
  2. 根据权利要求1所述的方法，其中，所述在所述基板上设置栅极的步骤包括：
    在所述基板上设置一与所述栅极同层且间隔设置的第一存储电极。
  3. 根据权利要求2所述的方法，其中，所述在所述栅极上方设置一半导体层的步骤之前包括：
    在所述栅极上设置一第二绝缘层，其中所述第二绝缘层的对应所述第一存储电极的区域未被所述半导体层覆盖。
  4. 据权利要求3所述的方法，其中，所述在半导体层上设置与所述半导体层电连的源极的步骤进一步包括：
    在所述第二绝缘层上的未被所述半导体层覆盖的区域设置第二存储电极，使得所述第二存储电极对应所述第一存储电极设置。
  5. 根据权利要求4所述的方法，其中，所述方法还包括：所述像素电极进一步通过设置在所述第一绝缘层上的第二导通孔与所述第二存储电极电连，以向由所述第一存储电极和所述第二存储电极所形成的存储电容进行充电。
  6. 一种TFT开关管，其中，所述TFT开关管包括：
    基板；
    栅极，设置在所述基板上；
    半导体层，设置在所述栅极上方；
    源极，设置在所述半导体层上并与所述半导体层电连；
    第一绝缘层，设置在所述源极上，并在对应所述半导体层的位置设置第一通孔；
    像素电极，设置在所述第一绝缘层上，所述像素电极进一步作为漏极通过所述第一通孔与所述半导体层电连。
  7. 根据权利要求6所述的TFT开关管，其中，所述TFT开关管进一步包括：
    第二绝缘层，设置在所述栅极上。
  8. 根据权利要求7所述的TFT开关管，其中，所述TFT开关管进一步包括：
    第一存储电极，设置在所述基板上并与所述栅极同层且间隔设置，其中，所述第二绝缘层的对应所述第一存储电极的区域未被所述半导体层覆盖；
    第二存储电极，设置在所述第二绝缘层上的未被所述半导体层覆盖的区域，使得所述第二存储电极对应所述第一存储电极设置。
  9. 根据权利要求8所述的TFT开关管，其中，所述第一绝缘层对应所述第二存储电极的位置进一步设置第二通孔，所述像素电极进一步通过所述第二导通孔与所述第二存储电极电连，以向由所述第一存储电极和所述第二存储电极所形成的存储电容进行充电。
  10. 一种TFT基板，其中，所述TFT基板包括TFT开关管，所述TFT开关管包括：
    基板；
    栅极，设置在所述基板上；
    半导体层，设置在所述栅极上方；
    源极，设置在所述半导体层上并与所述半导体层电连；
    第一绝缘层，设置在所述源极上，并在对应所述半导体层的位置设置第一通孔；
    像素电极，设置在所述第一绝缘层上，所述像素电极进一步作为漏极通过所述第一通孔与所述半导体层电连。
  11. 根据权利要求10所述的TFT基板，其中，所述TFT开关管进一步包括：
    第二绝缘层，设置在所述栅极上。
  12. 根据权利要求11所述的TFT基板，其中，所述TFT开关管进一步包括：
    第一存储电极，设置在所述基板上并与所述栅极同层且间隔设置，其中，所述第二绝缘层的对应所述第一存储电极的区域未被所述半导体层覆盖；
    第二存储电极，设置在所述第二绝缘层上的未被所述半导体层覆盖的区域，使得所述第二存储电极对应所述第一存储电极设置。
  13. 根据权利要求12所述的TFT基板，其中，所述第一绝缘层对应所述第二存储电极的位置进一步设置第二通孔，所述像素电极进一步通过所述第二导通孔与所述第二存储电极电连，以向由所述第一存储电极和所述第二存储电极所形成的存储电容进行充电。
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