WO2015035684A1 - 一种薄膜晶体管、阵列基板及显示面板 - Google Patents

一种薄膜晶体管、阵列基板及显示面板 Download PDF

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WO2015035684A1
WO2015035684A1 PCT/CN2013/085838 CN2013085838W WO2015035684A1 WO 2015035684 A1 WO2015035684 A1 WO 2015035684A1 CN 2013085838 W CN2013085838 W CN 2013085838W WO 2015035684 A1 WO2015035684 A1 WO 2015035684A1
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layer
disposed
insulating layer
drain
source
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PCT/CN2013/085838
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English (en)
French (fr)
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杜鹏
陈政鸿
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深圳市华星光电技术有限公司
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Priority to KR1020167009188A priority Critical patent/KR20160052714A/ko
Priority to GB1601011.8A priority patent/GB2530956A/en
Priority to US14/233,386 priority patent/US20150069510A1/en
Priority to RU2016113120A priority patent/RU2627934C1/ru
Priority to JP2016537078A priority patent/JP6383420B2/ja
Publication of WO2015035684A1 publication Critical patent/WO2015035684A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor, an array substrate, and a display panel.
  • Thin film transistor used as a switching element in a display panel is a semiconductor device that uses a gate voltage to control current between a source and a drain.
  • the structure of the TFT is: a gate electrode, an insulating layer, and a gate layer are sequentially stacked. a semiconductor layer and a source and a drain.
  • the carriers that conduct electricity in the TFT conductive channel are electrons.
  • the working principle of the TFT is that when the Gate is applied with a high voltage, electrons in the region near the Gate side of the semiconductor layer are concentrated, and the electron concentration is increased, thereby forming a conductive front conductive channel between the Source and the Drain.
  • the front conductive channel is located below the Source and Drain.
  • the current between the Source and the Drain needs to pass through the semiconductor layer before reaching the front conductive channel.
  • the resistance of the semiconductor layer itself is relatively large.
  • the off state the semiconductor layer is away from the Gate side, that is, near the Source/Drain side, an electron-accumulated back conduction channel is formed. Channel), a leakage current is generated, the off-state current of the TFT is increased, and the switching ratio is lowered (Ion/Ioff).
  • the technical problem to be solved by the present invention is to provide a thin film transistor, an array substrate and a display panel, which can reduce the resistance of the conductive channel when the state is on, increase the switching current, and reduce the concentration of electrons in the conductive channel in the off state. , reduce the off-state current, thereby increasing the switching ratio.
  • a technical solution adopted by the present invention is to provide a thin film transistor including a gate electrode; a first insulating layer disposed on the gate; and a second insulating layer disposed at the source and the drain a semiconductor layer, a source and a drain, disposed between the first insulating layer and the second insulating layer; and a conductive layer disposed on the second insulating layer and electrically connected to the gate so that the thin film transistor is turned on In the state, the on-state current formed in the conductive channel of the semiconductor layer is increased, and in the off state, the off-state current in the conductive channel is reduced.
  • a first opening is disposed above the gate, the first opening penetrates the first insulating layer and the second insulating layer, and the gate is exposed, and the conductive layer is connected to the gate through the first opening.
  • the conductive layer is an ITO film or a metal layer.
  • the semiconductor layer is disposed on the first insulating layer
  • the source and the drain are disposed on the semiconductor layer
  • the thin film transistor further includes an ohmic contact layer disposed between the semiconductor layer and the source and the drain, and on the ohmic contact layer
  • a second opening is provided, the second opening passes through a gap between the source and the drain and penetrates the ohmic contact layer, and exposes the semiconductor layer
  • the second insulating layer is connected to the semiconductor layer through the second opening.
  • the source and the drain are disposed on the first insulating layer
  • the semiconductor layer is disposed on the source and the drain
  • the thin film transistor further includes an ohmic contact layer disposed between the semiconductor layer and the source and the drain, and in the ohm a second opening is disposed on the contact layer, the second opening penetrates the ohmic contact layer and passes through a gap between the source and the drain, and exposes the first insulating layer, and the semiconductor layer is connected to the first insulating layer through the second opening .
  • an array substrate comprising a substrate and a thin film transistor disposed on the substrate, the thin film transistor comprising: a gate disposed on a surface of the substrate; a first insulating layer disposed on the gate; a second insulating layer disposed on the source and the drain; a semiconductor layer, a source and a drain disposed between the first insulating layer and the second insulating layer; and a conductive layer Provided on the second insulating layer and electrically connected to the gate, so that the thin film transistor increases the on-state current formed in the conductive channel of the semiconductor layer when in the open state, and decreases in the conductive channel when in the off state. The off state current.
  • a first opening is disposed above the gate, the first opening penetrates the first insulating layer and the second insulating layer, and the gate is exposed, and the conductive layer is connected to the gate through the first opening.
  • the conductive layer is an ITO film or a metal layer.
  • the semiconductor layer is disposed on the first insulating layer
  • the source and the drain are disposed on the semiconductor layer
  • the thin film transistor further includes an ohmic contact layer disposed between the semiconductor layer and the source and the drain, and on the ohmic contact layer
  • a second opening is provided, the second opening passes through a gap between the source and the drain and penetrates the ohmic contact layer, and exposes the semiconductor layer
  • the second insulating layer is connected to the semiconductor layer through the second opening.
  • the source and the drain are disposed on the first insulating layer
  • the semiconductor layer is disposed on the source and the drain
  • the thin film transistor further includes an ohmic contact layer disposed between the semiconductor layer and the source and the drain, and in the ohm a second opening is disposed on the contact layer, the second opening penetrates the ohmic contact layer and passes through a gap between the source and the drain, and exposes the first insulating layer, and the semiconductor layer is connected to the first insulating layer through the second opening .
  • a display panel including an array substrate and a color filter substrate disposed oppositely, wherein the array substrate includes a substrate and a thin film transistor disposed on the substrate
  • the thin film transistor includes: a gate disposed on a surface of the substrate; a first insulating layer disposed on the gate; a second insulating layer disposed on the source and the drain; a semiconductor layer, a source and a drain, Provided between the first insulating layer and the second insulating layer; the conductive layer is disposed on the second insulating layer and is electrically connected to the gate, so that the thin film transistor increases the conductive trench formed in the semiconductor layer when the thin film transistor is in an open state The on-state current in the channel, when in the off state, reduces the off-state current in the conductive channel.
  • a first opening is disposed above the gate, the first opening penetrates the first insulating layer and the second insulating layer, and the gate is exposed, and the conductive layer is connected to the gate through the first opening.
  • the conductive layer is an ITO film or a metal layer.
  • the semiconductor layer is disposed on the first insulating layer
  • the source and the drain are disposed on the semiconductor layer
  • the thin film transistor further includes an ohmic contact layer disposed between the semiconductor layer and the source and the drain, and on the ohmic contact layer
  • a second opening is provided, the second opening passes through a gap between the source and the drain and penetrates the ohmic contact layer, and exposes the semiconductor layer
  • the second insulating layer is connected to the semiconductor layer through the second opening.
  • the source and the drain are disposed on the first insulating layer
  • the semiconductor layer is disposed on the source and the drain
  • the thin film transistor further includes an ohmic contact layer disposed between the semiconductor layer and the source and the drain, and in the ohm a second opening is disposed on the contact layer, the second opening penetrates the ohmic contact layer and passes through a gap between the source and the drain, and exposes the first insulating layer, and the semiconductor layer is connected to the first insulating layer through the second opening .
  • the thin film transistor of the present invention includes a gate, a first insulating layer, a semiconductor layer, a source and a drain, a second insulating layer, and a conductive layer, wherein The insulating layer is disposed on the gate, the second insulating layer is disposed above the first insulating layer, the semiconductor layer, the source and the drain are disposed between the first insulating layer and the second insulating layer, and the conductive layer is disposed on the second insulating layer Up and parallel to the gate.
  • the gate and the conductive layer of the present invention can simultaneously receive the turn-on signal and the turn-off signal.
  • the gate and the conductive layer When the turn-on signal is simultaneously received, the gate and the conductive layer respectively form two conductive channels in the semiconductor layer, which is reduced. Conductive channel impedance, thereby increasing the on-state current.
  • the gate and the conductive layer When receiving the turn-off signal at the same time, the gate and the conductive layer simultaneously remove electrons in the conductive channel, thereby reducing the off-state current, that is, reducing the leakage current.
  • the present invention can increase the switching ratio.
  • FIG. 1 is a schematic structural view of an embodiment of a thin film transistor of the present invention.
  • FIG. 2 is a schematic structural view of the thin film transistor shown in FIG. 1 in an open state
  • FIG. 3 is a schematic structural view of the thin film transistor shown in FIG. 1 in a closed state
  • FIG. 4 is a schematic structural view of another embodiment of a thin film transistor of the present invention.
  • FIG. 5 is a schematic structural view of an embodiment of an array substrate according to the present invention.
  • FIG. 6 is a schematic structural view of an embodiment of a display panel of the present invention.
  • FIG. 1 is a schematic structural view of an embodiment of a thin film transistor of the present invention.
  • the thin film transistor 10 of the present invention includes a gate electrode 11, a first insulating layer 12, a semiconductor layer 13, a source electrode 14, a drain electrode 15, a second insulating layer 16, and a conductive layer 17.
  • the first insulating layer 12 is disposed on the gate electrode 11.
  • the second insulating layer 16 is disposed above the first insulating layer 12.
  • the semiconductor layer 13, the source 14 and the drain 15 are disposed between the first insulating layer 12 and the second insulating layer 16.
  • the conductive layer 17 is disposed on the second insulating layer 16 and is electrically connected to the gate electrode 11 such that the thin film transistor 10 increases the on-state current formed in the conductive channel of the semiconductor layer 13 when in the open state, in the off state. The off-state current in the conductive channel of the semiconductor layer 13 is reduced.
  • the conductive layer 17 and the gate 11 are electrically connected to each other.
  • the first opening 110 is disposed above the gate 11.
  • the first opening 110 penetrates the first insulating layer 12 and the second insulating layer.
  • the layer 16 is exposed and the gate 11 is exposed.
  • the conductive layer 17 is connected to the gate 11 through the first opening 110.
  • the conductive layer 17 is ITO (Indium Tin Oxide, tin-doped indium oxide) film or metal layer.
  • the conductive layer 17 can also be other conductive materials, as long as the electrical connection between the gate 11 and the conductive layer 17 can be electrically connected to each other, which is not limited herein.
  • the semiconductor layer 13 is disposed on the first insulating layer 12, and the source 14 and the drain 15 are disposed on the semiconductor layer 13 and are located on both sides of the semiconductor layer 13.
  • the thin film transistor 10 further includes an ohmic contact layer 18 disposed between the semiconductor layer 13 and the source 14 and the drain 15, and a second opening 111 is disposed on the ohmic contact layer 18, and the second opening 111 passes through the source 14 The gap between the drain electrode 15 and the ohmic contact layer 18 is penetrated, and the semiconductor layer 13 is exposed, and the second insulating layer 16 is connected to the semiconductor layer 13 through the second opening 111.
  • FIG. 2 is a schematic structural view of the thin film transistor 10 in an open state
  • FIG. 3 is a schematic structural view of the thin film transistor 10 in a closed state.
  • the gate 11 of the thin film transistor 10 receives an open signal such as a high voltage
  • the thin film transistor 10 is in an on state (on state)
  • the source 14 and the drain 15 are electrically connected through the semiconductor layer 13, wherein The carriers that conduct electricity are electrons.
  • the conductive layer 17 and the gate electrode 11 are connected through the first opening 110, the gate electrode 11 and the conductive layer 17 simultaneously receive an open signal.
  • conductive channels 133 and 134 are formed in the semiconductor layer 13 near the side 131 of the gate 11 and the side 132 close to the conductive layer 17, respectively, and the current between the source 14 and the drain 15 passes through the conductive channel 133. And 134 for transmission.
  • the gate 11 of the thin film transistor 10 receives a turn-off signal such as a low voltage
  • the thin film transistor 10 is in an off state (off state).
  • the semiconductor layer 13 electrically insulates the source 14 and the drain 15.
  • the conductive layer 17 simultaneously receives the turn-off signal, and at this time, the electrons formed in the conductive channels 133 and 134 are respectively removed by the gate electrode 11 and the conductive layer 17, so that between the source 14 and the drain 15 No current transmission.
  • the thin film transistor 10 in this embodiment forms two conductive channels 133 and 134 in an on state, which reduces the impedance of the conductive channel, thereby increasing the on-state current.
  • the electrons formed in the conductive channels 133 and 134 are respectively removed by the gate electrode 11 and the conductive layer 17, which reduces the off-state current, that is, reduces the leakage current. Therefore, the present invention can improve the switching ratio (on-state current and off) The ratio of the state current).
  • FIG. 4 is a schematic structural view of another embodiment of a thin film transistor of the present invention.
  • the thin film transistor 40 of the present embodiment still includes a gate electrode 41, a first insulating layer 42, a semiconductor layer 43, a source electrode 44, a drain electrode 45, a second insulating layer 46, a conductive layer 47, and an ohmic contact layer. 48.
  • the thin film transistor 40 of the present embodiment is different from the thin film transistor 10 of FIG. 1 in that the source electrode 44 and the drain electrode 45 in this embodiment are disposed on the first insulating layer 42, and the semiconductor layer 43 is disposed on the source.
  • an ohmic contact layer 48 is disposed between the semiconductor layer 43 and the source 44 and the drain 45, and a second opening 441 is provided on the ohmic contact layer 48, and the second opening 441 penetrates the ohmic
  • the contact layer 48 passes through the gap between the source electrode 44 and the drain electrode 45, and exposes the first insulating layer 42, and the semiconductor layer 43 is connected to the first insulating layer 42 through the second opening 441.
  • the thin film transistor 40 of the present embodiment has the same principle as the thin film transistor 10 of the above embodiment, and details are not described herein again.
  • FIG. 5 is a schematic structural view of an embodiment of an array substrate according to the present invention.
  • the array substrate 50 of the present invention includes a substrate 51 and a plurality of thin film transistors 52 disposed on the substrate 51.
  • the thin film transistor 52 is the thin film transistor 10 or 40 of the previous embodiment, and details are not described herein.
  • FIG. 6 is a schematic structural diagram of an embodiment of a display panel according to the present invention.
  • the display panel 60 of the present embodiment includes an array substrate 61 , a color filter substrate 62 , and a liquid crystal layer 63 disposed between the array substrate 61 and the color filter substrate 62 , wherein the array substrate 61 and the color
  • the film substrate 62 collectively controls the inversion of the liquid crystal 631 in the liquid crystal layer 63 to control the light passing through the liquid crystal layer 63, thereby obtaining a desired picture.
  • the array substrate 61 is the array substrate 50 of the previous embodiment, and details are not described herein again.
  • a conductive layer is disposed on the second insulating layer, so that the thin film transistor forms two conductive channels in the on state, which reduces the impedance of the conductive channel, thereby increasing the on state.
  • the current, in the off state the electrons formed in the two conductive channels are respectively removed by the gate and the conductive layer, reducing the off-state current, that is, reducing the leakage current, and therefore, the present invention can improve the switching ratio.

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种薄膜晶体管（10）、阵列基板及显示面板，薄膜晶体管包括栅极（11，41）、第一绝缘层（12，42）、第二绝缘层（16，46）、半导体层（13，43）、源极（14，44）和漏极（15，45）以及导电层（17，47），第一绝缘层设置在栅极上，第二绝缘层设置在第一绝缘层上方，半导体层、源极和漏极设置在第一绝缘层和第二绝缘层之间，导电层设置在第二绝缘层上，并与栅极相互导通，使得薄膜晶体管在打开状态时，增大形成在半导体层的导电沟道中的开态电流，在关闭状态时，减小导电沟道的关态电流。通过上述方式，能够提高开关比。

Description

一种薄膜晶体管、阵列基板及显示面板
【技术领域】
本发明涉及显示技术领域，特别是涉及一种薄膜晶体管、阵列基板及显示面板。
【背景技术】
显示面板中用作开关元件的薄膜晶体管（Thin Film Transistor，TFT）是利用栅极（Gate）电压来控制源极（Source）和漏极（Drain）间电流的一种半导体器件，其中，TFT的结构为：依次层叠设置的栅极、绝缘层、半导体层以及源极和漏极。在TFT导电沟道（Channel）中起导电作用的载流子为电子。
TFT的工作原理为：在Gate加高电压时，半导体层中靠近Gate侧的区域的电子聚集，电子浓度升高，从而在Source和Drain之间形成一个导电的前导电沟道。前导电沟道位于Source和Drain的下方，在工作时Source和Drain之间的电流需要穿过半导体层之后才能到达前导电沟道，半导体层本身的电阻比较大。在关态时，半导体层远离Gate侧，即靠近Source/Drain侧会形成电子积累的背导电沟道（Back Channel），产生漏电流，使TFT的关态电流变大，开关比降低（Ion/Ioff）。
【发明内容】
本发明主要解决的技术问题是提供一种薄膜晶体管、阵列基板及显示面板，能够在开态时，减小导电沟道电阻，增大开关电流，在关态时减小导电沟道中电子的浓度，降低关态电流，从而提高开关比。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种薄膜晶体管，该薄膜晶体管包括栅极；第一绝缘层，设置在栅极上；第二绝缘层，设置在源极和漏极上；半导体层、源极和漏极，设置在第一绝缘层和第二绝缘层之间；导电层，设置在第二绝缘层上，并与栅极相互导通，使得薄膜晶体管在打开状态时，增大形成在半导体层的导电沟道中的开态电流，在关闭状态时，减小导电沟道中的关态电流。
其中，在栅极的上方设置第一开孔，第一开孔穿透第一绝缘层和第二绝缘层，并露出栅极，导电层通过第一开孔与栅极连接。
其中，导电层为ITO膜或金属层。
其中，半导体层设置在第一绝缘层上，源极和漏极设置在半导体层上，薄膜晶体管还包括欧姆接触层，设置在半导体层和源极和漏极之间，并且在欧姆接触层上设置第二开孔，第二开孔经过源极和漏极之间的空隙并穿透欧姆接触层，并露出半导体层，第二绝缘层通过第二开孔与半导体层连接。
其中，源极和漏极设置在第一绝缘层上，半导体层设置在源极和漏极上，薄膜晶体管还包括欧姆接触层，设置在半导体层和源极和漏极之间，并且在欧姆接触层上设置第二开孔，第二开孔穿透欧姆接触层并经过源极和漏极之间的空隙，并露出第一绝缘层，半导体层通过第二开孔与第一绝缘层连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，阵列基板包括基板和设置在基板上的薄膜晶体管，该薄膜晶体管包括：栅极，设置在基板的表面上；第一绝缘层，设置在栅极上；第二绝缘层，设置在源极和漏极上；半导体层、源极和漏极，设置在第一绝缘层和第二绝缘层之间；导电层，设置在第二绝缘层上，并与栅极相互导通，使得薄膜晶体管在打开状态时，增大形成在半导体层的导电沟道中的开态电流，在关闭状态时，减小导电沟道中的关态电流。
其中，在栅极的上方设置第一开孔，第一开孔穿透第一绝缘层和第二绝缘层，并露出栅极，导电层通过第一开孔与栅极连接。
其中，导电层为ITO膜或金属层。
其中，半导体层设置在第一绝缘层上，源极和漏极设置在半导体层上，薄膜晶体管还包括欧姆接触层，设置在半导体层和源极和漏极之间，并且在欧姆接触层上设置第二开孔，第二开孔经过源极和漏极之间的空隙并穿透欧姆接触层，并露出半导体层，第二绝缘层通过第二开孔与半导体层连接。
其中，源极和漏极设置在第一绝缘层上，半导体层设置在源极和漏极上，薄膜晶体管还包括欧姆接触层，设置在半导体层和源极和漏极之间，并且在欧姆接触层上设置第二开孔，第二开孔穿透欧姆接触层并经过源极和漏极之间的空隙，并露出第一绝缘层，半导体层通过第二开孔与第一绝缘层连接。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种显示面板，该显示面板包括相对设置的阵列基板和彩膜基板，其中，阵列基板包括基板和设置在基板上的薄膜晶体管，该薄膜晶体管包括：栅极，设置在基板的表面上；第一绝缘层，设置在栅极上；第二绝缘层，设置在源极和漏极上；半导体层、源极和漏极，设置在第一绝缘层和第二绝缘层之间；导电层，设置在第二绝缘层上，并与栅极相互导通，使得薄膜晶体管在打开状态时，增大形成在半导体层的导电沟道中的开态电流，在关闭状态时，减小导电沟道中的关态电流。
其中，在栅极的上方设置第一开孔，第一开孔穿透第一绝缘层和第二绝缘层，并露出栅极，导电层通过第一开孔与栅极连接。
其中，导电层为ITO膜或金属层。
其中，半导体层设置在第一绝缘层上，源极和漏极设置在半导体层上，薄膜晶体管还包括欧姆接触层，设置在半导体层和源极和漏极之间，并且在欧姆接触层上设置第二开孔，第二开孔经过源极和漏极之间的空隙并穿透欧姆接触层，并露出半导体层，第二绝缘层通过第二开孔与半导体层连接。
其中，源极和漏极设置在第一绝缘层上，半导体层设置在源极和漏极上，薄膜晶体管还包括欧姆接触层，设置在半导体层和源极和漏极之间，并且在欧姆接触层上设置第二开孔，第二开孔穿透欧姆接触层并经过源极和漏极之间的空隙，并露出第一绝缘层，半导体层通过第二开孔与第一绝缘层连接。
本发明的有益效果是：区别于现有技术的情况，本发明的薄膜晶体管包括栅极、第一绝缘层、半导体层、源极和漏极、第二绝缘层以及导电层，其中，第一绝缘层设置在栅极上，第二绝缘层设置在第一绝缘层的上方，半导体层、源极和漏极设置第一绝缘层和第二绝缘层之间，导电层设置在第二绝缘层上，并与栅极相互导通。通过上述方式，本发明的栅极和导电层能够同时接收到开启信号和关闭信号，在同时接收到开启信号时，栅极和导电层分别在半导体层中形成两个导电沟道，减小了导电沟道阻抗，从而增大了开态电流，在同时接收到关闭信号时，栅极和导电层同时排走导电沟道中的电子，减小了关态电流，即减小漏电流，因此，本发明能够提高开关比。
【附图说明】
图1是本发明一种薄膜晶体管一实施例的结构示意图；
图2是图1所示的薄膜晶体管在打开状态时的结构示意图；
图3是图1所示的薄膜晶体管在关闭状态时的结构示意图；
图4是本发明一种薄膜晶体管另一实施例的结构示意图；
图5是本发明一种阵列基板一实施例的结构示意图；
图6是本发明一种显示面板一实施例的结构示意图。
【具体实施方式】
下面结合附图和实施例对本发明进行详细的说明。
请参阅图1，图1是本发明一种薄膜晶体管一实施例的结构示意图。如图1所示，本发明的薄膜晶体管10包括栅极11、第一绝缘层12、半导体层13、源极14、漏极15、第二绝缘层16以及导电层17。其中，第一绝缘层12设置在栅极11上。第二绝缘层16设置在第一绝缘层12上方。半导体层13、源极14和漏极15设置在第一绝缘层12和第二绝缘层16之间。导电层17设置在第二绝缘层16上，并与栅极11相互导通，使得薄膜晶体管10在打开状态时，增大形成在半导体层13的导电沟道中的开态电流，在关闭状态时，减小半导体层13的导电沟道中的关态电流。
本实施例中，导电层17与栅极11相互导通的具体实现方式为：在栅极11的上方设置第一开孔110，第一开孔110穿透第一绝缘层12和第二绝缘层16，并露出栅极11，导电层17通过第一开孔110与栅极11连接。其中，导电层17为ITO(Indium Tin Oxide，掺锡氧化铟)膜或金属层。导电层17还可以为其他导电材料，只要能使栅极11和导电层17的电性相互导通即可，在此不作限制。
本实施例中，半导体层13设置在第一绝缘层12上，源极14和漏极15设置在半导体层13上，并位于半导体层13的两侧。薄膜晶体管10还包括欧姆接触层18，其设置在半导体层13和源极14和漏极15之间，并且在欧姆接触层18上设置第二开孔111，第二开孔111经过源极14和漏极15之间的空隙并穿透欧姆接触层18，并露出半导体层13，第二绝缘层16通过第二开孔111与半导体层13连接。
以下将介绍本发明的薄膜晶体管10的工作原理：
请参阅图2和图3，图2是薄膜晶体管10在打开状态时的结构示意图；图3是薄膜晶体管10在关闭状态时的结构示意图。首先如图2所示，在薄膜晶体管10的栅极11接收到打开信号例如高电压时，薄膜晶体管10处于打开状态（开态），源极14和漏极15通过半导体层13电连接，其中起导电作用的载流子为电子。本实施例中，因为导电层17和栅极11通过第一开孔110连接，因此，栅极11和导电层17同时接收到打开信号。此时，在半导体层13中靠近栅极11的一侧131和靠近导电层17的一侧132分别形成导电沟道133和134，源极14和漏极15之间的电流通过导电沟道133和134进行传输。
再如图3所示，在薄膜晶体管10的栅极11接收到关闭信号例如低电压时，薄膜晶体管10处于关闭状态（关态）。此时，半导体层13使源极14和漏极15电性绝缘。具体而言，导电层17同时接收到该关闭信号，此时，形成在导电沟道133和134中的电子分别被栅极11和导电层17排走，使得源极14和漏极15之间的无电流传输。
综上所述，本实施例中的薄膜晶体管10在开态时形成了两个导电沟道133和134，减小了导电沟道的阻抗，从而增大了开态电流，在关态时，形成在导电沟道133和134中的电子分别被栅极11和导电层17排走，减小了关态电流，即减小漏电流，因此，本发明能够提高开关比（开态电流与关态电流的比值）。
请参阅图4，图4是本发明一种薄膜晶体管另一实施例的结构示意图。如图4所示，本实施例的薄膜晶体管40依然包括栅极41、第一绝缘层42、半导体层43、源极44、漏极45、第二绝缘层46、导电层47以及欧姆接触层48。其中，本实施例的薄膜晶体管40与图1中的薄膜晶体管10的不同之处在于：本实施例中的源极44和漏极45设置在第一绝缘层42上，半导体层43设置在源极44和漏极45上，欧姆接触层48设置在半导体层43和源极44和漏极45之间，并且在欧姆接触层48上设置第二开孔441，第二开孔441穿透欧姆接触层48并经过源极44和漏极45之间的空隙，并露出第一绝缘层42，半导体层43通过第二开孔441与第一绝缘层42连接。
其中，本实施例的薄膜晶体管40与上述实施例的薄膜晶体管10的原理相同，在此不再赘述。
请参阅图5，图5是本发明一种阵列基板一实施例的结构示意图。如图5所示，本发明的阵列基板50包括基板51和设置在基板51上的多个薄膜晶体管52，其中薄膜晶体管52为前文实施例的薄膜晶体管10或40，在此不再赘述。
请参阅图6，图6是本发明一种显示面板一实施例的结构示意图。如图6所示，本实施例的显示面板60包括相对设置的阵列基板61、彩膜基板62以及设置于阵列基板61和彩膜基板62之间的液晶层63，其中，阵列基板61和彩膜基板62共同控制液晶层63中的液晶631的翻转，以控制穿过液晶层63中的光线，从而得到所需的画面。本实施例中，阵列基板61为前文实施例的阵列基板50，在此不再赘述。
综上所述，本实施例在第二绝缘层上设置了一层导电层，使得薄膜晶体管在开态时形成两个导电沟道，减小了导电沟道的阻抗，从而增大了开态电流，在关态时，形成在两个导电沟道中的电子分别被栅极和导电层排走，减小了关态电流，即减小漏电流，因此，本发明能够提高开关比。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    栅极；
    第一绝缘层，设置在所述栅极上；
    第二绝缘层，设置在所述第一绝缘层上方；
    半导体层、源极和漏极，设置在所述第一绝缘层和所述第二绝缘层之间；
    导电层，设置在所述第二绝缘层上，并与所述栅极相互导通，使得所述薄膜晶体管在打开状态时，增大形成在所述半导体层的导电沟道中的开态电流，在关闭状态时，减小所述导电沟道中的关态电流。
  2. 根据权利要求1所述的薄膜晶体管，其中，在所述栅极的上方设置第一开孔，所述第一开孔穿透所述第一绝缘层和所述第二绝缘层，并露出所述栅极，所述导电层通过所述第一开孔与所述栅极连接。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述导电层为ITO膜或金属层。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述半导体层设置在所述第一绝缘层上，所述源极和漏极设置在所述半导体层上，所述薄膜晶体管还包括欧姆接触层，设置在所述半导体层和所述源极和漏极之间，并且在所述欧姆接触层上设置第二开孔，所述第二开孔经过所述源极和漏极之间的空隙并穿透所述欧姆接触层，并露出所述半导体层，所述第二绝缘层通过所述第二开孔与所述半导体层连接。
  5. 根据权利要求1所述的薄膜晶体管，其中，所述源极和漏极设置在所述第一绝缘层上，所述半导体层设置在所述源极和漏极上，所述薄膜晶体管还包括欧姆接触层，设置在所述半导体层和所述源极和漏极之间，并且在所述欧姆接触层上设置第二开孔，所述第二开孔穿透所述欧姆接触层并经过所述源极和漏极之间的空隙，并露出所述第一绝缘层，所述半导体层通过所述第二开孔与所述第一绝缘层连接。
  6. 一种阵列基板，所述阵列基板包括基板和设置在所述基板上的薄膜晶体管，其中，所述薄膜晶体管包括：
    栅极，设置在所述基板的表面上；
    第一绝缘层，设置在所述栅极上；
    第二绝缘层，设置在所述源极和漏极上；
    半导体层、源极和漏极，设置在所述第一绝缘层和所述第二绝缘层之间；
    导电层，设置在所述第二绝缘层上，并与所述栅极相互导通，使得所述薄膜晶体管在打开状态时，增大形成在所述半导体层的导电沟道中的开态电流，在关闭状态时，减小所述导电沟道中的关态电流。
  7. 根据权利要求6所述的阵列基板，其中，在所述栅极的上方设置第一开孔，所述第一开孔穿透所述第一绝缘层和所述第二绝缘层，并露出所述栅极，所述导电层通过所述第一开孔与所述栅极连接。
  8. 根据权利要求6所述的阵列基板，其中，所述导电层为ITO膜或金属层。
  9. 根据权利要求6所述的阵列基板，其中，所述半导体层设置在所述第一绝缘层上，所述源极和漏极设置在所述半导体层上，所述薄膜晶体管还包括欧姆接触层，设置在所述半导体层和所述源极和漏极之间，并且在所述欧姆接触层上设置第二开孔，所述第二开孔经过所述源极和漏极之间的空隙并穿透所述欧姆接触层，并露出所述半导体层，所述第二绝缘层通过所述第二开孔与所述半导体层连接。
  10. 根据权利要求6所述的阵列基板，其中，所述源极和漏极设置在所述第一绝缘层上，所述半导体层设置在所述源极和漏极上，所述薄膜晶体管还包括欧姆接触层，设置在所述半导体层和所述源极和漏极之间，并且在所述欧姆接触层上设置第二开孔，所述第二开孔穿透所述欧姆接触层并经过所述源极和漏极之间的空隙，并露出所述第一绝缘层，所述半导体层通过所述第二开孔与所述第一绝缘层连接。
  11. 一种显示面板，其中，所述显示面板包括相对设置的阵列基板和彩膜基板，其中，所述阵列基板包括基板和设置在所述基板上的薄膜晶体管，其中，所述薄膜晶体管包括：
    栅极，设置在所述基板的表面上；
    第一绝缘层，设置在所述栅极上；
    第二绝缘层，设置在所述源极和漏极上；
    半导体层、源极和漏极，设置在所述第一绝缘层和所述第二绝缘层之间；
    导电层，设置在所述第二绝缘层上，并与所述栅极相互导通，使得所述薄膜晶体管在打开状态时，增大形成在所述半导体层的导电沟道中的开态电流，在关闭状态时，减小所述导电沟道中的关态电流。
  12. 根据权利要求11所述的显示面板，其中，在所述栅极的上方设置第一开孔，所述第一开孔穿透所述第一绝缘层和所述第二绝缘层，并露出所述栅极，所述导电层通过所述第一开孔与所述栅极连接。
  13. 根据权利要求11所述的显示面板，其中，所述导电层为ITO膜或金属层。
  14. 根据权利要求11所述的显示面板，其中，所述半导体层设置在所述第一绝缘层上，所述源极和漏极设置在所述半导体层上，所述薄膜晶体管还包括欧姆接触层，设置在所述半导体层和所述源极和漏极之间，并且在所述欧姆接触层上设置第二开孔，所述第二开孔经过所述源极和漏极之间的空隙并穿透所述欧姆接触层，并露出所述半导体层，所述第二绝缘层通过所述第二开孔与所述半导体层连接。
  15. 根据权利要求11所述的显示面板，其中，所述源极和漏极设置在所述第一绝缘层上，所述半导体层设置在所述源极和漏极上，所述薄膜晶体管还包括欧姆接触层，设置在所述半导体层和所述源极和漏极之间，并且在所述欧姆接触层上设置第二开孔，所述第二开孔穿透所述欧姆接触层并经过所述源极和漏极之间的空隙，并露出所述第一绝缘层，所述半导体层通过所述第二开孔与所述第一绝缘层连接。
PCT/CN2013/085838 2013-09-10 2013-10-24 一种薄膜晶体管、阵列基板及显示面板 WO2015035684A1 (zh)

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