CN103474472B - 一种薄膜晶体管、阵列基板及显示面板 - Google Patents
一种薄膜晶体管、阵列基板及显示面板 Download PDFInfo
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Abstract
本发明公开了一种薄膜晶体管、阵列基板及显示面板。该薄膜晶体管包括栅极、第一绝缘层、第二绝缘层、半导体层、源极和漏极以及导电层。第一绝缘层设置在栅极上,第二绝缘层设置在第一绝缘层上方,半导体层、源极和漏极设置在第一绝缘层和第二绝缘层之间,导电层设置在第二绝缘层上,并与栅极相互导通,使得薄膜晶体管在打开状态时,增大形成在半导体层的导电沟道中的开态电流,在关闭状态时,减小导电沟道的关态电流。通过上述方式,本发明能够提高开关比。
Description
技术领域
本发明涉及显示技术领域,特别是涉及一种薄膜晶体管、阵列基板及显示面板。
背景技术
显示面板中用作开关元件的薄膜晶体管(ThinFilmTransistor,TFT)是利用栅极(Gate)电压来控制源极(Source)和漏极(Drain)间电流的一种半导体器件,其中,TFT的结构为:依次层叠设置的栅极、绝缘层、半导体层以及源极和漏极。在TFT导电沟道(Channel)中起导电作用的载流子为电子。
TFT的工作原理为:在Gate加高电压时,半导体层中靠近Gate侧的区域的电子聚集,电子浓度升高,从而在Source和Drain之间形成一个导电的前导电沟道。前导电沟道位于Source和Drain的下方,在工作时Source和Drain之间的电流需要穿过半导体层之后才能到达前导电沟道,半导体层本身的电阻比较大。在关态时,半导体层远离Gate侧,即靠近Source/Drain侧会形成电子积累的背导电沟道(BackChannel),产生漏电流,使TFT的关态电流变大,开关比降低(Ion/Ioff)。
发明内容
本发明主要解决的技术问题是提供一种薄膜晶体管、阵列基板及显示面板,能够在开态时,减小导电沟道电阻,增大开关电流,在关态时减小导电沟道中电子的浓度,降低关态电流,从而提高开关比。
为解决上述技术问题,本发明采用的一个技术方案是:提供一种薄膜晶体管,该薄膜晶体管包括栅极;第一绝缘层,设置在栅极上;第二绝缘层,设置在源极和漏极上;半导体层、源极和漏极,设置在第一绝缘层和第二绝缘层之间;导电层,设置在第二绝缘层上,并与栅极相互导通,使得薄膜晶体管在打开状态时,增大形成在半导体层的导电沟道中的开态电流,在关闭状态时,减小导电沟道中的关态电流;其中,半导体层的宽度大于源极到漏极的宽度,并且栅极的宽度大于半导体层的宽度,其中,源极到漏极的宽度为源极远离漏极的一端到漏极远离源极的一端的宽度。
其中,在栅极的上方设置第一开孔,第一开孔穿透第一绝缘层和第二绝缘层,并露出栅极,导电层通过第一开孔与栅极连接。
其中,导电层为ITO膜或金属层。
其中,半导体层设置在第一绝缘层上,源极和漏极设置在半导体层上,薄膜晶体管还包括欧姆接触层,设置在半导体层和源极和漏极之间,并且在欧姆接触层上设置第二开孔,第二开孔经过源极和漏极之间的空隙并穿透欧姆接触层,并露出半导体层,第二绝缘层通过第二开孔与半导体层连接。
其中,源极和漏极设置在第一绝缘层上,半导体层设置在源极和漏极上,薄膜晶体管还包括欧姆接触层,设置在半导体层和源极和漏极之间,并且在欧姆接触层上设置第二开孔,第二开孔穿透欧姆接触层并经过源极和漏极之间的空隙,并露出第一绝缘层,半导体层通过第二开孔与第一绝缘层连接。
为解决上述技术问题,本发明采用的另一个技术方案是:提供一种阵列基板,阵列基板包括基板和设置在基板上的薄膜晶体管,该薄膜晶体管包括:栅极,设置在基板的表面上;第一绝缘层,设置在栅极上;第二绝缘层,设置在源极和漏极上;半导体层、源极和漏极,设置在第一绝缘层和第二绝缘层之间;导电层,设置在第二绝缘层上,并与栅极相互导通,使得薄膜晶体管在打开状态时,增大形成在半导体层的导电沟道中的开态电流,在关闭状态时,减小导电沟道中的关态电流;其中,半导体层的宽度大于源极到漏极的宽度,并且栅极的宽度大于半导体层的宽度,其中,源极到漏极的宽度为源极远离漏极的一端到漏极远离源极的一端的宽度。
其中,在栅极的上方设置第一开孔,第一开孔穿透第一绝缘层和第二绝缘层,并露出栅极,导电层通过第一开孔与栅极连接。
其中,导电层为ITO膜或金属层。
其中,半导体层设置在第一绝缘层上,源极和漏极设置在半导体层上,薄膜晶体管还包括欧姆接触层,设置在半导体层和源极和漏极之间,并且在欧姆接触层上设置第二开孔,第二开孔经过源极和漏极之间的空隙并穿透欧姆接触层,并露出半导体层,第二绝缘层通过第二开孔与半导体层连接。
为解决上述技术问题,本发明采用的又一个技术方案是:提供一种显示面板,该显示面板包括相对设置的阵列基板和彩膜基板,其中,阵列基板为上述所述的阵列基板。
本发明的有益效果是:区别于现有技术的情况,本发明的薄膜晶体管包括栅极、第一绝缘层、半导体层、源极和漏极、第二绝缘层以及导电层,其中,第一绝缘层设置在栅极上,第二绝缘层设置在第一绝缘层的上方,半导体层、源极和漏极设置第一绝缘层和第二绝缘层之间,导电层设置在第二绝缘层上,并与栅极相互导通。通过上述方式,本发明的栅极和导电层能够同时接收到开启信号和关闭信号,在同时接收到开启信号时,栅极和导电层分别在半导体层中形成两个导电沟道,减小了导电沟道阻抗,从而增大了开态电流,在同时接收到关闭信号时,栅极和导电层同时排走导电沟道中的电子,减小了关态电流,即减小漏电流,因此,本发明能够提高开关比。
附图说明
图1是本发明一种薄膜晶体管一实施例的结构示意图;
图2是图1所示的薄膜晶体管在打开状态时的结构示意图;
图3是图1所示的薄膜晶体管在关闭状态时的结构示意图;
图4是本发明一种薄膜晶体管另一实施例的结构示意图;
图5是本发明一种阵列基板一实施例的结构示意图;
图6是本发明一种显示面板一实施例的结构示意图。
具体实施方式
下面结合附图和实施例对本发明进行详细的说明。
请参阅图1,图1是本发明一种薄膜晶体管一实施例的结构示意图。如图1所示,本发明的薄膜晶体管10包括栅极11、第一绝缘层12、半导体层13、源极14、漏极15、第二绝缘层16以及导电层17。其中,第一绝缘层12设置在栅极11上。第二绝缘层16设置在第一绝缘层12上方。半导体层13、源极14和漏极15设置在第一绝缘层12和第二绝缘层16之间。导电层17设置在第二绝缘层16上,并与栅极11相互导通,使得薄膜晶体管10在打开状态时,增大形成在半导体层13的导电沟道中的开态电流,在关闭状态时,减小半导体层13的导电沟道中的关态电流。
本实施例中,导电层17与栅极11相互导通的具体实现方式为:在栅极11的上方设置第一开孔110,第一开孔110穿透第一绝缘层12和第二绝缘层16,并露出栅极11,导电层17通过第一开孔110与栅极11连接。其中,导电层17为ITO(IndiumTinOxide,掺锡氧化铟)膜或金属层。导电层17还可以为其他导电材料,只要能使栅极11和导电层17的电性相互导通即可,在此不作限制。
本实施例中,半导体层13设置在第一绝缘层12上,源极14和漏极15设置在半导体层13上,并位于半导体层13的两侧。薄膜晶体管10还包括欧姆接触层18,其设置在半导体层13和源极14和漏极15之间,并且在欧姆接触层18上设置第二开孔111,第二开孔111经过源极14和漏极15之间的空隙并穿透欧姆接触层18,并露出半导体层13,第二绝缘层16通过第二开孔111与半导体层13连接。
以下将介绍本发明的薄膜晶体管10的工作原理:
请参阅图2和图3,图2是薄膜晶体管10在打开状态时的结构示意图;图3是薄膜晶体管10在关闭状态时的结构示意图。首先如图2所示,在薄膜晶体管10的栅极11接收到打开信号例如高电压时,薄膜晶体管10处于打开状态(开态),源极14和漏极15通过半导体层13电连接,其中起导电作用的载流子为电子。本实施例中,因为导电层17和栅极11通过第一开孔110连接,因此,栅极11和导电层17同时接收到打开信号。此时,在半导体层13中靠近栅极11的一侧131和靠近导电层17的一侧132分别形成导电沟道133和134,源极14和漏极15之间的电流通过导电沟道133和134进行传输。
再如图3所示,在薄膜晶体管10的栅极11接收到关闭信号例如低电压时,薄膜晶体管10处于关闭状态(关态)。此时,半导体层13使源极14和漏极15电性绝缘。具体而言,导电层17同时接收到该关闭信号,此时,形成在导电沟道133和134中的电子分别被栅极11和导电层17排走,使得源极14和漏极15之间的无电流传输。
综上所述,本实施例中的薄膜晶体管10在开态时形成了两个导电沟道133和134,减小了导电沟道的阻抗,从而增大了开态电流,在关态时,形成在导电沟道133和134中的电子分别被栅极11和导电层17排走,减小了关态电流,即减小漏电流,因此,本发明能够提高开关比(开态电流与关态电流的比值)。
请参阅图4,图4是本发明一种薄膜晶体管另一实施例的结构示意图。如图4所示,本实施例的薄膜晶体管40依然包括栅极41、第一绝缘层42、半导体层43、源极44、漏极45、第二绝缘层46、导电层47以及欧姆接触层48。其中,本实施例的薄膜晶体管40与图1中的薄膜晶体管10的不同之处在于:本实施例中的源极44和漏极45设置在第一绝缘层42上,半导体层43设置在源极44和漏极45上,欧姆接触层48设置在半导体层43和源极44和漏极45之间,并且在欧姆接触层48上设置第二开孔441,第二开孔441穿透欧姆接触层48并经过源极44和漏极45之间的空隙,并露出第一绝缘层42,半导体层43通过第二开孔441与第一绝缘层42连接。
其中,本实施例的薄膜晶体管40与上述实施例的薄膜晶体管10的原理相同,在此不再赘述。
请参阅图5,图5是本发明一种阵列基板一实施例的结构示意图。如图5所示,本发明的阵列基板50包括基板51和设置在基板51上的多个薄膜晶体管52,其中薄膜晶体管52为前文实施例的薄膜晶体管10或40,在此不再赘述。
请参阅图6,图6是本发明一种显示面板一实施例的结构示意图。如图6所示,本实施例的显示面板60包括相对设置的阵列基板61、彩膜基板62以及设置于阵列基板61和彩膜基板62之间的液晶层63,其中,阵列基板61和彩膜基板62共同控制液晶层63中的液晶631的翻转,以控制穿过液晶层63中的光线,从而得到所需的画面。本实施例中,阵列基板61为前文实施例的阵列基板50,在此不再赘述。
综上所述,本实施例在第二绝缘层上设置了一层导电层,使得薄膜晶体管在开态时形成两个导电沟道,减小了导电沟道的阻抗,从而增大了开态电流,在关态时,形成在两个导电沟道中的电子分别被栅极和导电层排走,减小了关态电流,即减小漏电流,因此,本发明能够提高开关比。
以上所述仅为本发明的实施方式,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。
Claims (10)
1.一种薄膜晶体管,其特征在于,所述薄膜晶体管包括:
栅极;
第一绝缘层,设置在所述栅极上;
第二绝缘层,设置在所述第一绝缘层上方;
半导体层、源极和漏极,设置在所述第一绝缘层和所述第二绝缘层之间;
导电层,设置在所述第二绝缘层上,并与所述栅极相互导通,使得所述薄膜晶体管在打开状态时,增大形成在所述半导体层的导电沟道中的开态电流,在关闭状态时,减小所述导电沟道中的关态电流;
其中,所述半导体层的宽度大于所述源极到漏极的宽度,并且所述栅极的宽度大于所述半导体层的宽度,其中,所述源极到漏极的宽度为所述源极远离所述漏极的一端到所述漏极远离所述源极的一端的宽度。
2.根据权利要求1所述的薄膜晶体管,其特征在于,在所述栅极的上方设置第一开孔,所述第一开孔穿透所述第一绝缘层和所述第二绝缘层,并露出所述栅极,所述导电层通过所述第一开孔与所述栅极连接。
3.根据权利要求1所述的薄膜晶体管,其特征在于,所述导电层为ITO膜或金属层。
4.根据权利要求1所述的薄膜晶体管,其特征在于,所述半导体层设置在所述第一绝缘层上,所述源极和漏极设置在所述半导体层上,所述薄膜晶体管还包括欧姆接触层,设置在所述半导体层和所述源极和漏极之间,并且在所述欧姆接触层上设置第二开孔,所述第二开孔经过所述源极和漏极之间的空隙并穿透所述欧姆接触层,并露出所述半导体层,所述第二绝缘层通过所述第二开孔与所述半导体层连接。
5.根据权利要求1所述的薄膜晶体管,其特征在于,所述源极和漏极设置在所述第一绝缘层上,所述半导体层设置在所述源极和漏极上,所述薄膜晶体管还包括欧姆接触层,设置在所述半导体层和所述源极和漏极之间,并且在所述欧姆接触层上设置第二开孔,所述第二开孔穿透所述欧姆接触层并经过所述源极和漏极之间的空隙,并露出所述第一绝缘层,所述半导体层通过所述第二开孔与所述第一绝缘层连接。
6.一种阵列基板,所述阵列基板包括基板和设置在所述基板上的薄膜晶体管,其特征在于,所述薄膜晶体管包括:
栅极,设置在所述基板的表面上;
第一绝缘层,设置在所述栅极上;
第二绝缘层,设置在源极和漏极上;
半导体层、源极和漏极,设置在所述第一绝缘层和所述第二绝缘层之间;
导电层,设置在所述第二绝缘层上,并与所述栅极相互导通,使得所述薄膜晶体管在打开状态时,增大形成在所述半导体层的导电沟道中的开态电流,在关闭状态时,减小所述导电沟道中的关态电流;
其中,所述半导体层的宽度大于所述源极到漏极的宽度,并且所述栅极的宽度大于所述半导体层的宽度,其中,所述源极到漏极的宽度为所述源极远离所述漏极的一端到所述漏极远离所述源极的一端的宽度。
7.根据权利要求6所述的阵列基板,其特征在于,在所述栅极的上方设置第一开孔,所述第一开孔穿透所述第一绝缘层和所述第二绝缘层,并露出所述栅极,所述导电层通过所述第一开孔与所述栅极连接。
8.根据权利要求6所述的阵列基板,其特征在于,所述导电层为ITO膜或金属层。
9.根据权利要求6所述的阵列基板,其特征在于,所述半导体层设置在所述第一绝缘层上,所述源极和漏极设置在所述半导体层上,所述薄膜晶体管还包括欧姆接触层,设置在所述半导体层和所述源极和漏极之间,并且在所述欧姆接触层上设置第二开孔,所述第二开孔经过所述源极和漏极之间的空隙并穿透所述欧姆接触层,并露出所述半导体层,所述第二绝缘层通过所述第二开孔与所述半导体层连接。
10.一种显示面板,其特征在于,所述显示面板包括相对设置的阵列基板和彩膜基板,其中,所述阵列基板为如权利要求6-9所述的阵列基板。
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