CN104157611B - 氧化物半导体tft基板的制作方法及其结构 - Google Patents

氧化物半导体tft基板的制作方法及其结构 Download PDF

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CN104157611B
CN104157611B CN201410415944.5A CN201410415944A CN104157611B CN 104157611 B CN104157611 B CN 104157611B CN 201410415944 A CN201410415944 A CN 201410415944A CN 104157611 B CN104157611 B CN 104157611B
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transparent conductive
oxide semiconductor
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王俊
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Abstract

本发明提供一种氧化物半导体TFT基板的制作方法及其结构。该方法包括如下步骤：1、在基板(1)上形成栅极(3)及第一重度掺杂透明导电薄膜层(2)；2、沉积栅极绝缘层(4)；3、形成岛状氧化物半导体层(5)；4、形成岛状蚀刻阻挡层(6)；5、形成源/漏极(8)、第二、第三重度掺杂透明导电薄膜层(7、9)，所述源/漏极(8)借由第二重度掺杂透明导电薄膜层(7)与氧化物半导体层(5)的两侧部(53)接触，形成电性连接；6、沉积并图案化保护层(10)；7、沉积并图案化像素电极层(11)，其借由所述第三重度掺杂透明导电薄膜层(9)与源/漏极(8)接触，形成电性连接；8、退火处理。

Description

氧化物半导体TFT基板的制作方法及其结构
技术领域
本发明涉及显示技术领域，尤其涉及一种氧化物半导体TFT基板的制作方法及其结构。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)。
基于有机发光二极管的OLED显示技术同成熟的LCD相比，OLED是主动发光的显示器，具有自发光、高对比度、宽视角(达170°)、快速响应、高发光效率、低操作电压(3～10V)、超轻薄(厚度小于2mm)等优势，具有更优异的彩色显示画质、更宽广的观看范围和更大的设计灵活性。
薄膜晶体管(Thin Film Transistor，TFT)是平板显示装置的重要组成部分，可形成在玻璃基板或塑料基板上，通常作为开光装置和驱动装置用在诸如LCD、OLED、电泳显示装置(EPD)上。
氧化物半导体TFT技术是当前的热门技术。由于氧化物半导体的载流子迁移率是非晶硅半导体的20-30倍，具有较高的电子迁移率，可以大大提高TFT对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，并能够提高像素的行扫描速率，使得制作超高分辨率的平板显示装置成为可能。相比低温多晶硅(LTPS)，氧化物半导体制程简单，与非晶硅制程相容性较高，可以应用于LCD、OLED、柔性显示(Flexible)等领域，且与高世代生产线兼容，可应用于大中小尺寸显示，具有良好的应用发展前景。
现有的氧化物半导体TFT基板结构中，氧化物半导体层直接与源/漏极接触，二者之间形成电性连接；像素电极层直接与源/漏极接触，二者之间形成电性连接；但氧化物半导体层与源/漏极之间、及像素电极层与源/漏极之间的欧姆接触电阻较大，导致平板显示装置的驱动电压较高、功耗较高、响应速度较低。
节能降耗是当今社会发展的需要，努力开发低功耗的显示装置成为了各个显示装置生产厂家的重要目标。
发明内容
本发明的目的在于提供一种氧化物半导体TFT基板的制作方法，能够改善氧化物半导体层与源/漏极、及像素电极层与源/漏极之间的欧姆接触，减小欧姆接触电阻，降低平板显示装置的阈值电压，从而有效降低平板显示装置的功耗，提高其响应速度。
本发明的目的还在于提供一种氧化物半导体TFT基板结构，其氧化物半导体层与源/漏极之间、及像素电极层与源/漏极之间的欧姆接触电阻较小，使得平板显示装置的阈值电压较低、功耗较低、响应速度较快。
为实现上述目的，本发明首先提供一种氧化物半导体TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在该基板上依次沉积并图案化第一重度掺杂透明导电薄膜层与第一金属层，形成栅极、及位于该栅极下表面并与该栅极同样形状的第一重度掺杂透明导电薄膜层；
步骤2、在所述栅极与基板上沉积栅极绝缘层；
步骤3、在所述栅极绝缘层上沉积并图案化氧化物半导体层，形成位于所述栅极正上方的岛状氧化物半导体层；
步骤4、在所述岛状氧化物半导体层与栅极绝缘层上沉积并图案化蚀刻阻挡层，形成位于所述岛状氧化物半导体层上的岛状蚀刻阻挡层；
所述岛状蚀刻阻挡层的宽度小于所述岛状氧化物半导体层的宽度；所述岛状蚀刻阻挡层覆盖岛状氧化物半导体层的中间部而暴露出岛状氧化物半导体层的两侧部；
步骤5、在所述岛状蚀刻阻挡层与栅极绝缘层上依次沉积并图案化第二重度掺杂透明导电薄膜层、第二金属层、与第三重度掺杂透明导电薄膜层，形成源/漏极、位于该源/漏极下表面并与该源/漏极同样形状的第二重度掺杂透明导电薄膜层、及位于该源/漏极上表面并与该源/漏极同样形状的第三重度掺杂透明导电薄膜层；
所述源/漏极借由第二重度掺杂透明导电薄膜层与所述氧化物半导体层的两侧部接触，形成电性连接；
步骤6、在所述第三重度掺杂透明导电薄膜层与蚀刻阻挡层上沉积并图案化保护层，形成位于所述岛状氧化物半导体层一侧的通孔；
步骤7、在所述保护层上沉积并图案化像素电极层；
所述像素电极层填充所述通孔，并借由所述第三重度掺杂透明导电薄膜层与源/漏极接触，形成电性连接；
步骤8、对步骤7得到的基板进行退火处理。
所述栅极与源/漏极的材料为铜，所述像素电极层的材料为ITO或IZO。
所述第一重度掺杂透明导电薄膜层、第二重度掺杂透明导电薄膜层、与第三重度掺杂透明导电薄膜层的材料为重度掺杂的ITO或重度掺杂的IZO。
所述第一重度掺杂透明导电薄膜层、第二重度掺杂透明导电薄膜层、与第三重度掺杂透明导电薄膜层的厚度分别在5～200nm之间。
所述第一重度掺杂透明导电薄膜层的厚度为10nm，所述第二重度掺杂透明导电薄膜层的厚度为15nm，所述第三重度掺杂透明导电薄膜层的厚度为10nm。
所述岛状氧化物半导体层为IGZO半导体层。
所述保护层的材料为SiO2或SiON。
所述图案化通过黄光与蚀刻制程实现。
本发明还提供一种氧化物半导体TFT基板结构，包括一基板、位于基板上的栅极、位于栅极下表面并与栅极同样形状的第一重度掺杂透明导电薄膜层、位于栅极与基板上的栅极绝缘层、于栅极正上方位于栅极绝缘层上的岛状氧化物半导体层、位于岛状氧化物半导体层上的岛状蚀刻阻挡层、位于岛状蚀刻阻挡层与栅极绝缘层上的源/漏极、位于源/漏极下表面并与源/漏极同样形状的第二重度掺杂透明导电薄膜层、位于源/漏极上表面并与源/漏极同样形状的第三重度掺杂透明导电薄膜层、位于第三重度掺杂透明导电薄膜层与蚀刻阻挡层上的保护层、及位于保护层上的像素电极层；所述岛状氧化物半导体层包括中间部与两侧部；所述岛状蚀刻阻挡层的宽度小于所述氧化物半导体层的宽度，仅覆盖所述中间部；所述源/漏极借由第二重度掺杂透明导电薄膜层与所述氧化物半导体层的两侧部接触，形成电性连接；所述保护层具有位于所述岛状氧化物半导体层一侧的通孔，所述像素电极层填充所述通孔，并借由所述第三重度掺杂透明导电薄膜层与源/漏极接触，形成电性连接。
所述栅极与源/漏极的材料为铜，所述第一重度掺杂透明导电薄膜层、第二重度掺杂透明导电薄膜层、与第三重度掺杂透明导电薄膜层的材料为重度掺杂的ITO或重度掺杂的IZO，所述岛状氧化物半导体层为IGZO半导体层，所述保护层的材料为SiO2或SiON，所述像素电极层的材料为ITO或IZO；所述第一重度掺杂透明导电薄膜层、第二重度掺杂透明导电薄膜层、与第三重度掺杂透明导电薄膜层的厚度分别在5～200nm之间。
本发明的有益效果：本发明的氧化物半导体TFT基板的制作方法，通过在源/漏极上、下表面分别设置第二重度掺杂透明导电薄膜层、第三重度掺杂透明导电薄膜层，能够改善氧化物半导体层与源/漏极、及像素电极层与源/漏极之间的欧姆接触，减小欧姆接触电阻，降低平板显示装置的阈值电压，从而有效降低平板显示装置的功耗，提高其响应速度；本发明的氧化物半导体TFT基板结构，具有分别位于源/漏极上、下表面的第二重度掺杂透明导电薄膜层、第三重度掺杂透明导电薄膜层，使得氧化物半导体层与源/漏极之间、
及像素电极层与源/漏极之间的欧姆接触电阻较小，从而使得平板显示装置的阈值电压较低、功耗较低、响应速度较快。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明氧化物半导体TFT基板的制作方法的流程图；
图2为本发明氧化物半导体TFT基板的制作方法的步骤1的示意图；
图3为本发明氧化物半导体TFT基板的制作方法的步骤2的示意图；
图4为本发明氧化物半导体TFT基板的制作方法的步骤3的示意图；
图5为本发明氧化物半导体TFT基板的制作方法的步骤4的示意图；
图6为本发明氧化物半导体TFT基板的制作方法的步骤5的示意图；
图7为本发明氧化物半导体TFT基板的制作方法的步骤6的示意图；
图8为本发明氧化物半导体TFT基板的制作方法的步骤7暨本发明氧化物半导体TFT基板结构的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其技术效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，为本发明氧化物半导体TFT基板的制作方法的流程图，该氧化物半导体TFT基板的制作方法包括如下步骤：
步骤1、请参阅图2，提供一基板1，在该基板1上依次沉积并图案化第一重度掺杂透明导电薄膜层与第一金属层，形成栅极3、及位于该栅极3下表面并与该栅极3同样形状的第一重度掺杂透明导电薄膜层2。
所述基板1为透明基板，优选的，所述基板1为玻璃基板。
在该步骤1中，通过一道普通光罩进行黄光制程、再经蚀刻制程图案化所述第一重度掺杂透明导电薄膜层与第一金属层，形成栅极3、及位于该栅极3下表面并与该栅极3同样形状的第一重度掺杂透明导电薄膜层2。
所述栅极3的材料为铜(Cu)。
所述第一重度掺杂透明导电薄膜层2的材料为重度掺杂的氧化铟锡(ITO)或重度掺杂的氧化铟锌(IZO)，且该第一重度掺杂透明导电薄膜层2的厚度分别在5～200nm之间，优选的，该第一重度掺杂透明导电薄膜层2的厚度为10nm。所述第一重度掺杂透明导电薄膜层2能够增加所述栅极3与基板1之间的附着力，改善二者之间的粘合强度。
步骤2、请参阅图3，在所述栅极3与基板1上沉积栅极绝缘层4。
所述栅极绝缘4完全覆盖所述栅极3与基板1。
步骤3、请参阅图4，在所述栅极绝缘层4上沉积并通过黄光与蚀刻制程图案化氧化物半导体层，形成位于所述栅极3正上方的岛状氧化物半导体层5。
具体的，所述岛状氧化物半导体层5为铟镓锌氧化物(IGZO)半导体层。
步骤4、请参阅图5，在所述岛状氧化物半导体层5与栅极绝缘层4上沉积并通过黄光与蚀刻制程图案化蚀刻阻挡层，形成位于所述岛状氧化物半导体层5上的岛状蚀刻阻挡层6。
进一步的，所述岛状蚀刻阻挡层6的宽度小于所述氧化物半导体层5的宽度；所述岛状蚀刻阻挡层6覆盖岛状氧化物半导体层5的中间部51而暴露出氧化物半导体层5的两侧部53。
步骤5、请参阅图6，在所述岛状蚀刻阻挡层6与栅极绝缘层3上依次沉积并通过黄光与蚀刻制程图案化第二重度掺杂透明导电薄膜层、第二金属层、与第三重度掺杂透明导电薄膜层，形成源/漏极8、位于该源/漏极8下表面并与该源/漏极8同样形状的第二重度掺杂透明导电薄膜层7、及位于该源/漏极8上表面并与该源/漏极8同样形状的第三重度掺杂透明导电薄膜层9。
具体的，所述第二与第三重度掺杂透明导电薄膜层7、9的材料为重度掺杂的ITO或重度掺杂的IZO；且该第二与第三重度掺杂透明导电薄膜层7、9的厚度分别在5～200nm之间，优选的，所述第二重度掺杂透明导电薄膜层7的厚度为15nm，所述第三重度掺杂透明导电薄膜层9的厚度为10nm。
所述源/漏极8的材料为Cu。
所述源/漏极8借由第二重度掺杂透明导电薄膜层7与所述氧化物半导体层5的两侧部53接触，形成电性连接。所述第二重度掺杂透明导电薄膜层7具有较强的导电能力，其作为源/漏极8与氧化物半导体层5之间的接触过渡层，能够有效降低源/漏极8与氧化物半导体层5之间的欧姆接触电阻，从而达到有效降低平板显示装置的阈值电压与功耗，提高响应速度的目的。
步骤6、请参阅图7，在所述第三重度掺杂透明导电薄膜层9与蚀刻阻挡层6上沉积并图案化保护层10，形成位于所述岛状氧化物半导体层5一侧的通孔101。
具体的，所述保护层10的材料为二氧化硅(SiO2)或氮氧化硅(SiON)。
步骤7、请参阅图8，在所述保护层10上沉积并通过黄光与蚀刻制程图案化像素电极层11。
具体的，所述像素电极层11的材料为ITO或IZO。
所述像素电极层11填充所述通孔101，并借由所述第三重度掺杂透明导电薄膜层9与源/漏极8接触，形成电性连接。所述第三重度掺杂透明导电薄膜层9具有较强的导电能力，其作为源/漏极8与像素电极层11之间的接触过渡层，能够有效降低源/漏极8与像素电极层11之间的欧姆接触电阻，从而达到有效降低平板显示装置的驱动电压与功耗，提高响应速度的目的。
步骤8、对步骤7得到的基板1进行退火处理，完成该氧化物半导体TFT基板的制作。
请参阅图8，在上述氧化物半导体TFT基板的制作方法的基础上，本发明还提供一种氧化物半导体TFT基板结构，包括一基板1、位于基板1上的栅极3、位于栅极3下表面并与栅极3同样形状的第一重度掺杂透明导电薄膜层2、位于栅极3与基板1上的栅极绝缘层4、于栅极3正上方位于栅极绝缘层4上的岛状氧化物半导体层5、位于岛状氧化物半导体层5上的岛状蚀刻阻挡层6、位于岛状蚀刻阻挡层6与栅极绝缘层4上的源/漏极8、位于源/漏极8下表面并与源/漏极8同样形状的第二重度掺杂透明导电薄膜层7、位于源/漏极8上表面并与源/漏极8同样形状的第三重度掺杂透明导电薄膜层9、位于第三重度掺杂透明导电薄膜层9与蚀刻阻挡层6上的保护层10、及位于保护层10上的像素电极层11。
所述岛状氧化物半导体层5包括中间部51与两侧部53；所述岛状蚀刻阻挡层6的宽度小于所述氧化物半导体层5的宽度，仅覆盖所述中间部51。所述源/漏极8借由第二重度掺杂透明导电薄膜层7与所述氧化物半导体层5的两侧部53接触，形成电性连接，能够使得氧化物半导体层5与源/漏极8之间的欧姆接触电阻较小，从而使得平板显示装置的阈值电压较低、功耗较低、响应速度较快。所述保护层10具有位于所述岛状氧化物半导体层5一侧的通孔101，所述像素电极层11填充所述通孔101，并借由所述第三重度掺杂透明导电薄膜层9与源/漏极8接触，形成电性连接，能够使得像素电极层11与源/漏极8之间的欧姆接触电阻较小，从而使得平板显示装置的驱动电压较低、功耗较低、响应速度较快。
具体的，所述栅极3与源/漏极8的材料为铜；所述第一重度掺杂透明导电薄膜层2、第二重度掺杂透明导电薄膜层7、与第三重度掺杂透明导电薄膜层9的材料为重度掺杂的ITO或重度掺杂的IZO；所述岛状氧化物半导体层5为IGZO半导体层；所述保护层10的材料为SiO2或SiON；所述像素电极层11的材料为ITO或IZO；所述第一重度掺杂透明导电薄膜层2、第二重度掺杂透明导电薄膜层7、与第三重度掺杂透明导电薄膜层9的厚度分别在5～200nm之间，优选的，所述第一重度掺杂透明导电薄膜层2的厚度为10nm，所述第二重度掺杂透明导电薄膜层7的厚度为15nm，所述第三重度掺杂透明导电薄膜层9的厚度为10nm。
综上所述，本发明的氧化物半导体TFT基板的制作方法，通过在源/漏极上、下表面分别设置第二重度掺杂透明导电薄膜层、第三重度掺杂透明导电薄膜层，能够改善氧化物半导体层与源/漏极、及像素电极层与源/漏极之间的欧姆接触，减小欧姆接触电阻，降低平板显示装置的阈值电压，从而有效降低平板显示装置的功耗，提高其响应速度；本发明的氧化物半导体TFT基板结构，具有分别位于源/漏极上、下表面的第二重度掺杂透明导电薄膜层、第三重度掺杂透明导电薄膜层，使得氧化物半导体层与源/漏极之间、及像素电极层与源/漏极之间的欧姆接触电阻较小，从而使得平板显示装置的阈值电压较低、功耗较低、响应速度较快。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (10)

1.一种氧化物半导体TFT基板的制作方法，其特征在于，包括如下步骤：
步骤1、提供一基板(1)，在该基板(1)上依次沉积并图案化第一重度掺杂透明导电薄膜层与第一金属层，形成栅极(3)、及位于该栅极(3)下表面并与该栅极(3)同样形状的第一重度掺杂透明导电薄膜层(2)；
步骤2、在所述栅极(3)与基板(1)上沉积栅极绝缘层(4)；
步骤3、在所述栅极绝缘层(4)上沉积并图案化氧化物半导体层，形成位于所述栅极(3)正上方的岛状氧化物半导体层(5)；
步骤4、在所述岛状氧化物半导体层(5)与栅极绝缘层(4)上沉积并图案化蚀刻阻挡层，形成位于所述岛状氧化物半导体层(5)上的岛状蚀刻阻挡层(6)；
所述岛状蚀刻阻挡层(6)的宽度小于所述岛状氧化物半导体层(5)的宽度；所述岛状蚀刻阻挡层(6)覆盖岛状氧化物半导体层(5)的中间部(51)而暴露出岛状氧化物半导体层(5)的两侧部(53)；
步骤5、在所述岛状蚀刻阻挡层(6)与栅极绝缘层(4)上依次沉积并图案化第二重度掺杂透明导电薄膜层、第二金属层、与第三重度掺杂透明导电薄膜层，形成源/漏极(8)、位于该源/漏极(8)下表面并与该源/漏极(8)同样形状的第二重度掺杂透明导电薄膜层(7)、及位于该源/漏极(8)上表面并与该源/漏极(8)同样形状的第三重度掺杂透明导电薄膜层(9)；
所述源/漏极(8)借由第二重度掺杂透明导电薄膜层(7)与所述氧化物半导体层(5)的两侧部(53)接触，形成电性连接；
步骤6、在所述第三重度掺杂透明导电薄膜层(9)与蚀刻阻挡层(6)上沉积并图案化保护层(10)，形成位于所述岛状氧化物半导体层(5)一侧的通孔(101)；
步骤7、在所述保护层(10)上沉积并图案化像素电极层(11)；
所述像素电极层(11)填充所述通孔(101)，并借由所述第三重度掺杂透明导电薄膜层(9)与源/漏极(8)接触，形成电性连接；
步骤8、对步骤7得到的基板(1)进行退火处理。
2.如权利要求1所述的氧化物半导体TFT基板的制作方法，其特征在于，所述栅极(3)与源/漏极(8)的材料为铜，所述像素电极层(11)的材料为ITO或IZO。
3.如权利要求1所述的氧化物半导体TFT基板的制作方法，其特征在于，所述第一重度掺杂透明导电薄膜层(2)、第二重度掺杂透明导电薄膜层(7)、与第三重度掺杂透明导电薄膜层(9)的材料为重度掺杂的ITO或重度掺杂的IZO。
4.如权利要求3所述的氧化物半导体TFT基板的制作方法，其特征在于，所述第一重度掺杂透明导电薄膜层(2)、第二重度掺杂透明导电薄膜层(7)、与第三重度掺杂透明导电薄膜层(9)的厚度分别在5～200nm之间。
5.如权利要求4所述的氧化物半导体TFT基板的制作方法，其特征在于，所述第一重度掺杂透明导电薄膜层(2)的厚度为10nm，所述第二重度掺杂透明导电薄膜层(7)的厚度为15nm，所述第三重度掺杂透明导电薄膜层(9)的厚度为10nm。
6.如权利要求1所述的氧化物半导体TFT基板的制作方法，其特征在于，所述岛状氧化物半导体层(5)为IGZO半导体层。
7.如权利要求1所述的氧化物半导体TFT基板的制作方法，其特征在于，所述保护层(10)的材料为SiO2或SiON。
8.如权利要求1所述的氧化物半导体TFT基板的制作方法，其特征在于，所述图案化通过黄光与蚀刻制程实现。
9.一种氧化物半导体TFT基板结构，其特征在于，包括一基板(1)、位于基板(1)上的栅极(3)、位于栅极(3)下表面并与栅极(3)同样形状的第一重度掺杂透明导电薄膜层(2)、位于栅极(3)与基板(1)上的栅极绝缘层(4)、于栅极(3)正上方位于栅极绝缘层(4)上的岛状氧化物半导体层(5)、位于岛状氧化物半导体层(5)上的岛状蚀刻阻挡层(6)、位于岛状蚀刻阻挡层(6)与栅极绝缘层(4)上的源/漏极(8)、位于源/漏极(8)下表面并与源/漏极(8)同样形状的第二重度掺杂透明导电薄膜层(7)、位于源/漏极(8)上表面并与源/漏极(8)同样形状的第三重度掺杂透明导电薄膜层(9)、位于第三重度掺杂透明导电薄膜层(9)与蚀刻阻挡层(6)上的保护层(10)、及位于保护层(10)上的像素电极层(11)；所述岛状氧化物半导体层(5)包括中间部(51)与两侧部(53)；所述岛状蚀刻阻挡层(6)的宽度小于所述氧化物半导体层(5)的宽度，仅覆盖所述中间部(51)；所述源/漏极(8)借由第二重度掺杂透明导电薄膜层(7)与所述氧化物半导体层(5)的两侧部(53)接触，形成电性连接；所述保护层(10)具有位于所述岛状氧化物半导体层(5)一侧的通孔(101)，所述像素电极层(11)填充所述通孔(101)，并借由所述第三重度掺杂透明导电薄膜层(9)与源/漏极(8)接触，形成电性连接。
10.如权利要求9所述的氧化物半导体TFT基板结构，其特征在于，所述栅极(3)与源/漏极(8)的材料为铜，所述第一重度掺杂透明导电薄膜层(2)、第二重度掺杂透明导电薄膜层(7)、与第三重度掺杂透明导电薄膜层(9)的材料为重度掺杂的ITO或重度掺杂的IZO，所述岛状氧化物半导体层(5)为IGZO半导体层，所述保护层(10)的材料为SiO2或SiON，所述像素电极层(11)的材料为ITO或IZO；所述第一重度掺杂透明导电薄膜层(2)、第二重度掺杂透明导电薄膜层(7)、与第三重度掺杂透明导电薄膜层(9)的厚度分别在5～200nm之间。
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