WO2017128581A1 - 薄膜晶体管阵列基板及其制造方法 - Google Patents

薄膜晶体管阵列基板及其制造方法 Download PDF

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WO2017128581A1
WO2017128581A1 PCT/CN2016/084752 CN2016084752W WO2017128581A1 WO 2017128581 A1 WO2017128581 A1 WO 2017128581A1 CN 2016084752 W CN2016084752 W CN 2016084752W WO 2017128581 A1 WO2017128581 A1 WO 2017128581A1
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layer
semiconductor layer
thin film
film transistor
transistor array
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PCT/CN2016/084752
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English (en)
French (fr)
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周志超
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深圳市华星光电技术有限公司
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Priority to US15/317,296 priority Critical patent/US20170221930A1/en
Publication of WO2017128581A1 publication Critical patent/WO2017128581A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present invention relates to a thin film transistor and a method of fabricating the same, and, in particular, to a thin film transistor array substrate and a method of fabricating the same.
  • Liquid crystal display is one of the most widely used flat panel displays, and has gradually become a widely used electronic device such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptop screens with high-resolution color screens. monitor.
  • PDAs personal digital assistants
  • LCDs liquid crystal display
  • LCDs liquid crystal display
  • the liquid crystal panel is the most important component of the liquid crystal display, and includes a vacuum-bonded thin film transistor (TFT) array substrate, a color filter (CF) substrate, a liquid crystal layer disposed therebetween, and an alignment film.
  • TFT vacuum-bonded thin film transistor
  • CF color filter
  • Indium gallium zinc oxide (IGZO) materials can meet the requirements of high charge and discharge because of their high mobility, high on-state current, low off-state current, and rapid switching.
  • etching block (Etching Stop) Structural devices tend to have better electrical stability than other structures due to the presence of a protective layer.
  • etching block Etching Stop
  • the fabrication of such a structure is costly and limits the application of IGZO.
  • a first object of the present invention is to provide a method of fabricating a thin film transistor array substrate.
  • the manufacturing method includes: step S10, providing a transparent substrate, depositing a first metal layer on the transparent substrate, and patterning the first metal layer to form a gate pattern; and step S20, in the gate pattern And depositing a gate insulating layer on the transparent substrate; step S30, depositing a semiconductor layer on the gate insulating layer, patterning the semiconductor layer to form a semiconductor layer pattern; wherein the semiconductor layer pattern corresponds to a gate pattern, and the semiconductor layer is made of indium gallium zinc oxide; step S40, depositing an etch barrier layer on the semiconductor layer pattern and the gate insulating layer, where the etch barrier layer is Forming at least two spaced contact holes in the region of the semiconductor layer for exposing the semiconductor layer; step S50, depositing a second metal layer on the etch stop layer, patterning the second metal layer to form a a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively connected to the semiconductor layer through the contact hole; and, in step S60, at the source electrode Depositing a drain electrode
  • the molybdenum alloy is a molybdenum-titanium alloy.
  • a second object of the present invention is to provide a thin film transistor array substrate having a transparent substrate.
  • the thin film transistor array substrate further includes: a gate, the gate is disposed on the transparent substrate; a gate insulating layer, the gate insulating layer is disposed on the transparent substrate, and covers the gate; a semiconductor layer, the semiconductor layer is disposed on the gate insulating layer, and corresponds to a gate electrode on the transparent substrate; an etch barrier layer is disposed on the gate insulating layer and covers the semiconductor layer a semiconductor layer, and a plurality of contact holes are formed on the etch stop layer; a source electrode and a drain electrode, the source electrode and the drain electrode are disposed on the etch stop layer, and pass through the contact hole And respectively connected to the semiconductor layer; and a pixel electrode, wherein the pixel electrode is disposed on the source electrode and the drain electrode.
  • the semiconductor layer is made of indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the pixel electrode is made of a molybdenum alloy.
  • the molybdenum alloy is composed of molybdenum (Mo) and selected from the group consisting of titanium (Ti) and tantalum An alloy formed of one of (Ta), chromium (Cr), nickel (Ni), indium (In), and aluminum (Al). More preferably, the molybdenum alloy is a molybdenum-titanium alloy (MoTi).
  • the present invention also provides a method of manufacturing the above thin film transistor array substrate.
  • the method includes the steps of: providing a transparent substrate, depositing a first metal layer on the transparent substrate, patterning the first metal layer to form a gate pattern; and step S20, forming the gate pattern and the transparent Depositing a gate insulating layer on the substrate; step S30, depositing a semiconductor layer on the gate insulating layer, patterning the semiconductor layer to form a semiconductor layer pattern, wherein the semiconductor layer pattern corresponds to the gate a step S40, depositing an etch stop layer on the semiconductor layer pattern and the gate insulating layer, and forming at least two spaced contact holes in the region of the etch stop layer corresponding to the semiconductor layer, Exposing the semiconductor layer; step S50, depositing a second metal layer on the etch barrier layer, patterning the second metal layer to form a source electrode and a drain electrode, the source electrode and the drain The electrode electrodes are respectively connected to the semiconductor layer through the contact holes; and, in step S60, a pixel
  • the present invention also provides a liquid crystal panel comprising: a first substrate, a second substrate, and a liquid crystal composition and an alignment film filled between the first substrate and the second substrate, wherein the first substrate In the above thin film transistor array substrate, the second substrate is a color filter substrate.
  • the thin film transistor array substrate of the present invention replaces the ITO electrode in the conventional structure by using a MoTi electrode, and functions as a pixel electrode while covering and protecting the source electrode and the drain electrode under the MoTi electrode.
  • a similar passivation layer PV layer. Therefore, in the manufacturing process of the thin film transistor array substrate of the present invention, the PV layer can be omitted at the same time, and a photomask can be reduced to reduce the manufacturing cost and expand the application of the IGZO structure.
  • FIG. 1 is a schematic structural view of a thin film transistor array substrate of the present invention in a pixel structure
  • FIG. 2 is a schematic view showing the steps of the thin film transistor array substrate of the present invention.
  • 3A-3F are process flow diagrams of the thin film transistor array substrate of the present invention.
  • FIG. 4 is a schematic view showing a pixel structure of a liquid crystal panel using the thin film transistor array substrate of the present invention.
  • FIGS. 3A to 3F are presented in a simplified schematic manner in which the number of lines has been simplified, and details not related to the description are also omitted.
  • a thin film transistor array substrate 100 having a transparent substrate 101 is provided.
  • the thin film transistor array substrate 100 of the present invention will be described in detail below by taking a pixel region as an example.
  • the thin film transistor array substrate 100 includes a gate electrode 110 , a gate insulating layer 120 , a semiconductor layer 130 , an etch barrier layer 140 , a source electrode 151 and a drain electrode 152 , and a pixel electrode 160 .
  • the specific structure of the thin film transistor array substrate 100 is: a transparent substrate 101; a gate 110 disposed on the transparent substrate 101; disposed on the transparent substrate 101 and covering the gate a gate insulating layer 120; a semiconductor layer 130 disposed on the gate insulating layer 120 and corresponding to the gate electrode 110 on the transparent substrate 101; disposed on the gate insulating layer 120 and covering the
  • the etch stop layer 140 of the semiconductor layer 130 and as shown, the etch stop layer 140 is formed with a plurality of contact holes 141, 142; disposed on the etch stop layer 140 and passing through the contact hole 141, 142, a source electrode 151 and a drain electrode 152 respectively connected to the semiconductor layer 130; and a pixel electrode 160 provided on the source electrode 151 and the drain electrode 152.
  • the semiconductor layer is made of indium gallium zinc oxide (IGZO).
  • the pixel electrode is made of a molybdenum-titanium alloy (MoTi).
  • the present invention further provides a method for preparing the above thin film transistor array substrate.
  • the preparation method comprises the following steps:
  • a transparent substrate 101 is provided.
  • a first metal layer is deposited on the transparent substrate 101, and the first metal layer is patterned to form a gate 110 pattern.
  • a gate insulating layer 120 is deposited on the gate 110 pattern and the transparent substrate 101.
  • a semiconductor layer 130 is deposited on the gate insulating layer 120, and the semiconductor layer 130 is patterned to form a semiconductor layer 130 pattern such that the semiconductor layer 130 pattern corresponds to the gate 110. pattern.
  • an etch stop layer 140 is deposited on the semiconductor layer 130 pattern and the gate insulating layer 120, and at least two intervals are formed in the etch stop layer 140 corresponding to the semiconductor layer 130.
  • Contact holes 141, 142 are provided to expose the semiconductor layer 130.
  • a second metal layer is deposited on the etch stop layer 140, and the second metal layer is patterned to form a source electrode 151 and a drain electrode 152.
  • the source electrode 151 and the The drain electrode 152 is connected to the semiconductor layer 130 through the contact holes 141 and 142, respectively.
  • a pattern of pixel electrodes 160 is deposited on the source electrode 151 and the drain electrode 152.
  • FIG. 4 is a schematic diagram of a pixel structure of a liquid crystal panel using the thin film transistor array substrate of the present invention.
  • the present invention further provides a liquid crystal panel including: the oppositely disposed thin film transistor array substrate 100, the second substrate 200, and a filling between the first substrate 100 and the second substrate 200.
  • the second substrate is a color filter substrate.
  • the thin film transistor array substrate of the present invention replaces the ITO electrode in the conventional structure by using a MoTi electrode, and functions as a pixel electrode while covering and protecting the source electrode and the drain electrode under the MoTi electrode.
  • a similar passivation layer PV layer. Therefore, in the manufacturing process of the thin film transistor array substrate of the present invention, the PV layer can be omitted at the same time, and a photomask can be reduced to reduce the manufacturing cost and expand the application of the IGZO structure.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

一种薄膜晶体管阵列基板及其制备方法和液晶面板。薄膜晶体管阵列基板（100）包括透明基板（101）、栅极（110）、栅极绝缘层（120）、半导体层（130）、蚀刻阻挡层（140）、源极电极（151）与漏极电极（152）和像素电极（160）。该薄膜晶体管阵列基板通过采用MoTi电极取代传统结构中的ITO电极，使得薄膜晶体管阵列基板的制造工艺中可以同时省掉PV层，减少一道光罩，以降低制造成本，扩大IGZO结构的应用。

Description

薄膜晶体管阵列基板及其制造方法 技术领域
本发明涉及一种薄膜晶体管及其制造方法，特别是涉及一种薄膜晶体管阵列基板及其制造方法。
 背景技术
液晶显示器是目前使用最广泛的一种平板显示器，已经逐渐成为各种电子设备如移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕所广泛应用具有高分辨率彩色屏幕的显示器。随着液晶显示器技术的发展进步，人们对液晶显示器的显示品质，外观设计等提出了更高的要求。
液晶面板是液晶显示器最主要的组成配件，其包括真空贴合的薄膜晶体管（TFT）阵列基板、彩色滤光片（CF）基板、设置在两者之间的液晶层及配向膜。
随着目前显示行业中大尺寸化，对于高解析度的需求越来越强烈，因此，对有源层半导体器件充放电提出了更高的要求。铟镓锌氧化物（IGZO）材料因具有的高迁移率、高开态电流、低关态电流、可迅速开关等特点，因此，能够有效满足高充放电的要求。
尽管在目前常用的IGZO结构中，蚀刻阻挡(Etching Stop)结构器件因有保护层的存在，使得其电性的稳定性往往较其他结构更好。但是，由于增加了一道光罩，因此，该种结构的制备成本高，限制了IGZO的应用。
因此，需要提供一种新的薄膜晶体管阵列基板及应用该薄膜晶体管阵列基板的液晶面板，以解决上述问题。
 技术问题
本发明的第一个目的是提供一种薄膜晶体管阵列基板的制造方法。
 技术解决方案
所述制造方法包括：步骤S10、提供一透明基板，在所述透明基板上沉积第一金属层，并图案化所述第一金属层形成一栅极图案；步骤S20、在所述栅极图案及透明基板上沉积一栅极绝缘层；步骤S30、在所述栅极绝缘层上沉积一半导体层，图案化所述半导体层形成一半导体层图案；其中，所述半导体层图案对应于所述栅极图案，并且，所述半导体层由铟镓锌氧化物制成；步骤S40、在所述半导体层图案及所述栅极绝缘层上沉积一蚀刻阻挡层，在所述蚀刻阻挡层对应所述半导体层的区域内形成至少两个间隔设置的接触孔，用以暴露所述半导体层；步骤S50、在所述蚀刻阻挡层上沉积第二金属层，图案化所述第二金属层形成一源极电极和一漏极电极，其中，所述源极电极及所述漏极电极分别通过所述接触孔与所述半导体层连接；以及，步骤S60、在所述源极电极及漏极电极上沉积像素电极图案，其中所述像素电极由钼与由钛、钽、铬、镍、铟、以及铝组成的组中的一种形成的钼合金制成。
在本发明一实施例中，所述钼合金为钼钛合金。
本发明的第二个目的是提供一种薄膜晶体管阵列基板，具有一透明基板。所述薄膜晶体管阵列基板还包括：栅极，所述栅极设于所述透明基板上；栅极绝缘层，所述栅极绝缘层设于所述透明基板上，并且覆盖所述栅极；半导体层，所述半导体层设于所述栅极绝缘层上，并且对应所述透明基板上的栅极电极；蚀刻阻挡层，所述蚀刻阻挡层设于所述栅极绝缘层上并覆盖所述半导体层，并且，所述蚀刻阻挡层上形成数个接触孔；源极电极与漏极电极，所述源极电极与漏极电极设于所述蚀刻阻挡层上，并通过所述接触孔分别与所述半导体层连接；以及，像素电极，所述像素电极设于所述源极电极及漏极电极上。
在本发明一实施例中，所述半导体层由铟镓锌氧化物（IGZO）制成。
在本发明一实施例中，所述像素电极由钼合金制成。优选地，所述钼合金是由钼（Mo）与选自钛（Ti）、钽 （Ta）、铬（Cr）、镍（Ni）、铟（In）、以及铝（Al）中的一种所形成的合金。更优选地，所述钼合金为钼钛合金（MoTi）。
本发明还提供上述薄膜晶体管阵列基板的制造方法。所述方法包括：步骤S10、提供一透明基板，在所述透明基板上沉积第一金属层，图案化所述第一金属层形成一栅极图案；步骤S20、在所述栅极图案及透明基板上沉积一栅极绝缘层；步骤S30、在所述栅极绝缘层上沉积一半导体层，图案化所述半导体层形成一半导体层图案，其中，所述半导体层图案对应于所述栅极图案；步骤S40、在所述半导体层图案及所述栅极绝缘层上沉积一蚀刻阻挡层，在所述蚀刻阻挡层对应所述半导体层的区域形成至少两个间隔设置的接触孔，用以暴露所述半导体层；步骤S50、在所述蚀刻阻挡层上沉积第二金属层，图案化所述第二金属层形成一源极电极和一漏极电极，所述源极电极及所述漏极电极分别通过所述接触孔与所述半导体层连接；以及，步骤S60、在所述源极电极及漏极电极上沉积像素电极图案。
本发明还提供一种液晶面板，包括：相对设置的第一基板、第二基板和填充于所述第一基板及第二基板之间的液晶组合物和配向膜，其中，所述第一基板为上述薄膜晶体管阵列基板，所述第二基板为彩色滤光片基板。
 有益效果
本发明的薄膜晶体管阵列基板通过采用MoTi电极取代传统结构中的ITO电极，既起到作为像素电极的作用，同时对位于所述MoTi电极下的源极电极与漏极电极进行覆盖和保护，起到类似钝化层(PV层)的作用。因此，本发明的所述薄膜晶体管阵列基板的制造工艺中可以同时省掉PV层，减少一道光罩，以降低制造成本，扩大IGZO结构的应用。
 附图说明
图1是本发明所述薄膜晶体管阵列基板在一像素结构中的结构示意图；
图2是本发明所述薄膜晶体管阵列基板的步骤示意图；
图3A~3F是本发明所述薄膜晶体管阵列基板的工艺流程图；
图4是利用本发明所述薄膜晶体管阵列基板的液晶面板的像素结构示意图。
 本发明的最佳实施方式
以下结合实施例对本发明做详细的说明，实施例旨在解释而非限定本发明的技术方案。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。特别说明的是，为了说明上的方便，图3A~3F是以简化示意的方式来呈现，其中的线路数量已经过简化，并且也省略了与说明无关的细节。
本发明的优选实施例中提供一种薄膜晶体管阵列基板100，所述薄膜晶体管阵列基板100具有一透明基板101。以下以一像素区域作为示例对本发明的薄膜晶体管阵列基板100进行详细描述。
请参见图1，所述薄膜晶体管阵列基板100包括：栅极110、栅极绝缘层120、半导体层130、蚀刻阻挡层140、源极电极151与漏极电极152，以及，像素电极160。如图所示的，所述薄膜晶体管阵列基板100的具体结构依次为：透明基板101；设于所述透明基板101上的栅极110；设于所述透明基板101上并且覆盖所述栅极110的栅极绝缘层120；设于所述栅极绝缘层120上，并且对应所述透明基板101上的栅极110的半导体层130；设于所述栅极绝缘层120上并覆盖所述半导体层130的蚀刻阻挡层140，并且，如图所示的，所述蚀刻阻挡层140上形成数个接触孔141、142；设于所述蚀刻阻挡层140上并通过所述接触孔141、142分别与所述半导体层130连接的源极电极151与漏极电极152；以及，设于所述源极电极151及漏极电极152上的像素电极160。其中，所述半导体层由铟镓锌氧化物（IGZO）制成。所述像素电极由钼钛合金（MoTi）制成。
以下结合图2及图3A~3F，对上述薄膜晶体管阵列基板的制备方法进行详细描述。请参见图2及图3A~3F，本发明还提供上述薄膜晶体管阵列基板的制备方法。所述制备方法包括如下步骤：
参见步骤S10及图3A，提供一透明基板101，在所述透明基板101上沉积第一金属层，图案化所述第一金属层形成一栅极110图案。
参见步骤S20及图3B，在所述栅极110图案及透明基板101上沉积一栅极绝缘层120。
参见步骤S30及图3C，在所述栅极绝缘层120上沉积一半导体层130，图案化所述半导体层130形成一半导体层130图案，使得所述半导体层130图案对应于所述栅极110图案。
参见步骤S40及图3D，在所述半导体层130图案及所述栅极绝缘120层上沉积一蚀刻阻挡层140，在所述蚀刻阻挡层140对应所述半导体层130的区域形成至少两个间隔设置的接触孔141、142，用以暴露所述半导体层130。
参见步骤S50及图3E，在所述蚀刻阻挡层140上沉积第二金属层，图案化所述第二金属层形成一源极电极151和一漏极电极152，所述源极电极151及所述漏极电极152分别通过所述接触孔141、142与所述半导体层130连接。
参见步骤S60及图3F，在所述源极电极151及漏极电极152上沉积像素电极160图案。
此外，本发明的所述薄膜晶体管阵列基板可以用于液晶面板。请参见图4，图4是利用本发明所述薄膜晶体管阵列基板的液晶面板的像素结构示意图。如图4所示的，本发明还提供一种液晶面板，包括：相对设置的所述薄膜晶体管阵列基板100、第二基板200和填充于所述第一基板100及第二基板200之间的液晶组合物300。其中，所述第二基板为彩色滤光片基板。
本发明的薄膜晶体管阵列基板通过采用MoTi电极取代传统结构中的ITO电极，既起到作为像素电极的作用，同时对位于所述MoTi电极下的源极电极与漏极电极进行覆盖和保护，起到类似钝化层(PV层)的作用。因此，本发明的所述薄膜晶体管阵列基板的制造工艺中可以同时省掉PV层，减少一道光罩，以降低制造成本，扩大IGZO结构的应用。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (11)

  1. 一种薄膜晶体管阵列基板的制造方法，包括：
    步骤S10、提供一透明基板，在所述透明基板上沉积第一金属层，并图案化所述第一金属层形成一栅极图案；
    步骤S20、在所述栅极图案及透明基板上沉积一栅极绝缘层；
    步骤S30、在所述栅极绝缘层上沉积一半导体层，图案化所述半导体层形成一半导体层图案；其中，所述半导体层图案对应于所述栅极图案，并且，所述半导体层由铟镓锌氧化物制成；
    步骤S40、在所述半导体层图案及所述栅极绝缘层上沉积一蚀刻阻挡层，在所述蚀刻阻挡层对应所述半导体层的区域内形成至少两个间隔设置的接触孔，用以暴露所述半导体层；
    步骤S50、在所述蚀刻阻挡层上沉积第二金属层，图案化所述第二金属层形成一源极电极和一漏极电极，其中，所述源极电极及所述漏极电极分别通过所述接触孔与所述半导体层连接；以及，
    步骤S60、在所述源极电极及漏极电极上沉积像素电极图案，其中所述像素电极由钼与由钛、钽、铬、镍、铟、以及铝组成的组中的一种形成的钼合金制成。
  2. 如权利要求1所述的制造方法，其中，所述钼合金为钼钛合金。
  3. 一种薄膜晶体管阵列基板，具有一透明基板，其中，所述薄膜晶体管阵列基板还包括：
    栅极，所述栅极设于所述透明基板上；
    栅极绝缘层，所述栅极绝缘层设于所述透明基板上，并且覆盖所述栅极；
    半导体层，所述半导体层设于所述栅极绝缘层上，并且对应所述透明基板上的栅极电极；
    蚀刻阻挡层，所述蚀刻阻挡层设于所述栅极绝缘层上并覆盖所述半导体层，并且，所述蚀刻阻挡层上形成数个接触孔；
    源极电极与漏极电极，所述源极电极与漏极电极设于所述蚀刻阻挡层上，并通过所述接触孔分别与所述半导体层连接；以及，
    像素电极，所述像素电极设于所述源极电极及漏极电极上。
  4. 如权利要求3所述的薄膜晶体管阵列基板，其中，所述半导体层由铟镓锌氧化物制成。
  5. 如权利要求4所述的薄膜晶体管阵列基板，其中，所述像素电极由钼合金制成。
  6. 如权利要求5所述的薄膜晶体管阵列基板，其中，所述钼合金由钼与由钛、钽、铬、镍、铟、以及铝组成的组中的一种形成。
  7. 如权利要求6所述的薄膜晶体管阵列基板，其中，所述钼合金为钼钛合金。
  8. 一种如权利要求3所述的薄膜晶体管阵列基板的制造方法，包括：
    步骤S10、提供一透明基板，在所述透明基板上沉积第一金属层，图案化所述第一金属层形成一栅极图案；
    步骤S20、在所述栅极图案及透明基板上沉积一栅极绝缘层；
    步骤S30、在所述栅极绝缘层上沉积一半导体层，图案化所述半导体层形成一半导体层图案，其中所述半导体层图案对应于所述栅极图案；
    步骤S40、在所述半导体层图案及所述栅极绝缘层上沉积一蚀刻阻挡层，在所述蚀刻阻挡层对应所述半导体层的区域形成至少两个间隔设置的接触孔，用以暴露所述半导体层；
    步骤S50、在所述蚀刻阻挡层上沉积第二金属层，图案化所述第二金属层形成一源极电极和一漏极电极，其中，所述源极电极及所述漏极电极分别通过所述接触孔与所述半导体层连接；以及，
    步骤S60、在所述源极电极及漏极电极上沉积像素电极图案。
  9. 如权利要求8所述的方法，其中，所述半导体层由铟镓锌氧化物制成。
  10. 如权利要求8所述的方法，其中，所述像素电极由钼合金制成。
  11. 如权利要求9所述的方法，其中，所述钼合金为钼钛合金。
PCT/CN2016/084752 2016-01-28 2016-06-03 薄膜晶体管阵列基板及其制造方法 WO2017128581A1 (zh)

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