CN106887406B - 一种阵列基板的制作方法 - Google Patents

一种阵列基板的制作方法 Download PDF

Info

Publication number
CN106887406B
CN106887406B CN201710197970.9A CN201710197970A CN106887406B CN 106887406 B CN106887406 B CN 106887406B CN 201710197970 A CN201710197970 A CN 201710197970A CN 106887406 B CN106887406 B CN 106887406B
Authority
CN
China
Prior art keywords
scan line
layer
semiconductor layer
grid
source electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710197970.9A
Other languages
English (en)
Other versions
CN106887406A (zh
Inventor
周志超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to CN201710197970.9A priority Critical patent/CN106887406B/zh
Priority to US15/571,346 priority patent/US10355031B2/en
Priority to PCT/CN2017/082814 priority patent/WO2018176567A1/zh
Publication of CN106887406A publication Critical patent/CN106887406A/zh
Application granted granted Critical
Publication of CN106887406B publication Critical patent/CN106887406B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1262Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/22Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • G02F1/136295Materials; Compositions; Manufacture processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明的阵列基板的制作方法包括:基板;在基板上形成缓冲层;在缓冲层内形成源极和数据线,同时在缓冲层上形成第一栅极、第二栅极、第一扫描线以及第二扫描线;在源极、第一扫描线以及第二扫描线上形成半导体层;对位于第一扫描线以及第二扫描线上的半导体层进行导体化,以形成导体层;在半导体层上形成第一像素电极,同时在导体层上形成第二像素电极。本发明中阵列基板的制作方法,其工艺步骤较简单,提高了生产效率,减小了生产成本。

Description

一种阵列基板的制作方法
技术领域
本发明涉及液晶面板技术领域,尤其涉及一种阵列基板的制作方法。
背景技术
在液晶面板工业中,通过阵列基板来控制液晶的排列,从而实现不同灰度光线的显示,阵列基板为液晶面板中的重要部分,其生产也属于液晶面板制造过程中的重要工艺。
现有的采用环形栅极结构的阵列基板,由于其优越的性能,越来越受到人们的重视。然而该环形栅极结构的阵列基板运用于量产时,其工艺步骤较步骤,成本较高。
故,有必要提供一种阵列基板的制作方法,以解决现有技术所存在的问题。
发明内容
本发明的目的在于提供一种阵列基板的制作方法,以解决现有技术中阵列基板的工艺步骤复杂,成本较高的问题。
本发明提供一种阵列基板的制作方法,包括:
基板;
在所述基板上形成缓冲层;
在所述缓冲层内形成源极和数据线,同时在所述缓冲层上形成第一栅极、第二栅极、第一扫描线以及第二扫描线,其中,所述数据线与所述源极连接,所述第一栅极与所述第二栅极电性连接且环绕所述源极,所述第二扫描线线与所述第一栅极以及所述第二栅极连接;
在所述源极、所述第一扫描线以及所述第二扫描线上形成半导体层;
对位于所述第一扫描线以及所述第二扫描线上的所述半导体层进行导体化,以形成导体层;
在所述半导体层上形成第一像素电极,同时在所述导体层上形成第二像素电极,其中,所述第一像素电极通过所述导体层使得所述第一扫描线以及所述第二扫描线连接。
在本发明的阵列基板的制作方法中,所述在所述缓冲层内形成源极和数据线,同时在所述缓冲层上形成第一栅极、第二栅极、第一扫描线以及第二扫描线的步骤,包括:
在所述缓冲层上形成一光阻层;
通过黄光工艺和蚀刻工艺,形成第一栅极区域、第二栅极区域、第一扫描线区域、第二扫描线区域、源极区域以及数据线区域;
在所述光阻层上形成金属层,以覆盖所述第一栅极区域、所述第二栅极区域、所述第一扫描线区域、所述第二扫描线区域、所述源极区域以及所述数据线区域;
通过剥离工艺,去除所述光阻层以及位于所述光阻层上的所述金属层。
在本发明的阵列基板的制作方法中,所述在所述源极、所述第一扫描线以及所述第二扫描线上形成半导体层的步骤,包括:
在所述缓冲层上形成一绝缘层,以覆盖所述源极、所述数据线、所述第一栅极、所述第二栅极、所述第一扫描线以及所述第二扫描线;
在所述绝缘层上形成光阻层,以使得所述源极、所述第一扫描线以及所述第二扫描线裸露在外面;
在所述源极、所述第一扫描线以及所述第二扫描线上形成所述半导体层。
在本发明的阵列基板的制作方法中,所述在所述绝缘层上形成光阻层,以使得所述源极、所述第一扫描线以及所述第二扫描线裸露在外面的步骤,包括:
在所述绝缘层上形成所述光阻层;
通过黄光工艺与蚀刻工艺,使得所述源极、所述第一扫描线以及所述第二扫描线裸露在外面。
在本发明的阵列基板的制作方法中,所述在所述源极、所述第一扫描线以及所述第二扫描线上形成所述半导体层的步骤,包括:
在所述光阻层上形成所述半导体层,以覆盖所述第一扫描线、所述第二扫描线以及所述源极;
通过剥离工艺去除所述光阻层上的所述半导体层。
在本发明的阵列基板的制作方法中,所述对位于所述第一扫描线以及所述第二扫描线上的所述半导体层进行导体化,以形成导体层的步骤,包括:
通过黄光工艺,形成光阻层,以使得位于所述第一扫描线以及所述第二扫描线上的所述半导体层裸露在外面;
对位于所述第一扫描线以及所述第二扫描线上的所述半导体层进行导体化。
在本发明的阵列基板的制作方法中,可使用氩气、氮气以及氨气对位于所述第一扫描线以及所述第二扫描线上的所述半导体层进行导体化。
在本发明的阵列基板的制作方法中,所述在所述半导体层上形成第一像素电极,同时在所述导体层上形成第二像素电极的步骤,包括:
通过黄光工艺,形成光阻层,以使得所述导体层、所述半导体层以及位于所述第一扫描线与所述第二扫描线之间的区域裸露在外面;
在所述光阻层上形成像素电极层,以覆盖所述导体层所述半导体层以及位于所述第一扫描线与所述第二扫描线之间的区域。
通过剥离工艺去除所述光阻层以及位于所述光阻层上的所述像素电极层。
在本发明的阵列基板的制作方法中,所述半导体层的材料为铟镓锌氧化物。
在本发明的阵列基板的制作方法中,所述缓冲层为氮化硅层、氧化硅层或氧化铝层。
本发明的阵列基板的制作方法包括:基板;在基板上形成缓冲层;在缓冲层内形成源极和数据线,同时在缓冲层上形成第一栅极、第二栅极、第一扫描线以及第二扫描线;在源极、第一扫描线以及第二扫描线上形成半导体层;对位于第一扫描线以及第二扫描线上的半导体层进行导体化,以形成导体层;在半导体层上形成第一像素电极,同时在导体层上形成第二像素电极。本发明中阵列基板的制作方法,其工艺步骤较简单,提高了生产效率,减小了生产成本。
为让本发明的上述内容能更明显易懂,下文特举优选实施例,并配合所附图式,作详细说明如下:
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其它有益效果显而易见。
图1为本发明优选实施例提供的阵列基板的制作方法的流程示意图;
图2A-2D为图1所示阵列基板的制作方法中形成源极、数据线、第一栅极、第二栅极、第一扫描线以及第二扫描线的步骤对应的结构示意图;
图3A-3E为图1所示阵列基板的制作方法中在源极、第一扫描线以及第二扫描线上形成半导体层的步骤对应的结构示意图;
图4A-4C为图1所示阵列基板的制作方法中在源极、第一扫描线以及第二扫描线上形成半导体层对位于所述第一扫描线以及所述第二扫描线上的所述半导体层进行导体化,以形成导体层的步骤对应的结构示意图;
图5A-5C为图1所示阵列基板的制作方法中在所述半导体层上形成第一像素电极,同时在所述导体层上形成第二像素电极的步骤对应的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
参阅图1,图1为本发明优选实施例提供的阵列基板的制作方法的流程示意图。如图1所示,本优选实施例的阵列基板的制作方法,包括:
步骤S101,在基板上形成缓冲层;
步骤S102,在缓冲层内形成源极和数据线,同时在缓冲层上形成第一栅极、第二栅极、第一扫描线以及第二扫描线,其中,数据线与源极连接,第一栅极与第二栅极电性连接且环绕源极,第二扫描线与第一栅极以及第二栅极连接;
步骤S103,在源极、第一扫描线以及第二扫描线上形成半导体层;
步骤S104,对位于第一扫描线以及第二扫描线上的半导体层进行导体化,以形成导体层;
步骤S105,在半导体层上形成第一像素电极,同时在导体层上形成第二像素电极,其中,第一像素电极通过导体层使得第一扫描线以及第二扫描线连接。
具体的,在步骤S102中,请参阅图2A-2D,图2A-2D为图1所示阵列基板的制作方法中形成源极、数据线、第一栅极、第二栅极、第一扫描线以及第二扫描线的步骤对应的结构示意图;图2D中的上图为阵列基板的俯视图,下图为阵列基板A-A方向的剖视图。如图2A所示,在一基板11上依次形成缓冲层12和光阻层13;随后,如图2B所示,通过黄光工艺和蚀刻工艺,形成第一栅极区域133、第二栅极区域134、第一扫描线区域131、第二扫描线区域132、源极区域122以及数据线区域121;接着,如图2C所示,在光阻层13上形成金属层14,以覆盖第一栅极区域133、第二栅极区域134、第一扫描线区域132、第二扫描线区域131、源极区域122以及数据线区域121;最后,如图2D所示,通过剥离工艺,去除光阻层13以及位于光阻层13上的金属层14。特别的,数据线105与源极连接106,第一栅极103与第二栅极104电性连接且环绕源极106,第二扫描线102与第一栅极103以及第二栅极104连接。
具体的,在步骤S103中,请参阅图3A-3E,图3A-3E为图1所示阵列基板的制作方法中在源极、第一扫描线以及第二扫描线上形成半导体层的步骤对应的结构示意图。如图3A所示,首先,如图3A所示,在缓冲层12上形成一绝缘层15,以覆盖源极106、数据线105、第一栅极103、第二栅极104、第一扫描线101以及第二扫描线102。
接着,在绝缘层15上形成光阻层16,以使得源极106、第一扫描线101以及第二扫描线102裸露在外面;具体的,如图3B所示,在绝缘层15上形成光阻层16;随后,如图3C所示,通过黄光工艺与蚀刻工艺,使得源极106、第一扫描线101以及第二扫描线102裸露在外面。
最后,在源极106、第一扫描线101以及第二扫描线102上形成半导体层17。具体的,如图3D所示,在光阻层16上形成半导体层17,以覆盖第一扫描线101、第二扫描线102以及源极106;随后,如图3E所示,通过剥离工艺去除光阻层16上的半导体层17。
具体的,在步骤S104中,请参阅图4A-4C,图4A-4C为图1所示阵列基板的制作方法中在源极、第一扫描线以及第二扫描线上形成半导体层对位于所述第一扫描线以及所述第二扫描线上的所述半导体层进行导体化,以形成导体层的步骤对应的结构示意图。如图4A所示,通过黄光工艺,形成光阻层18,以使得位于第一扫描线101以及第二扫描线102上的半导体层裸露在外面;随后如图4B所示,对位于第一扫描线101以及第二扫描线102上的半导体层进行导体化,以形成导体层21,本优选实施例使用氩气、氮气以及氨气对位于所述第一扫描线101以及所述第二扫描线102上的半导体层进行导体化;最后,如图4C所示,去除光阻层18。
具体的,在步骤S105中,请参阅图5A-5C,图5A-5C为图1所示阵列基板的制作方法中在所述半导体层上形成第一像素电极,同时在所述导体层上形成第二像素电极的步骤对应的结构示意图。如图5A所示,通过黄光工艺,形成光阻层19,以使得导体层21、半导体层17以及所述第一扫描线101与第二扫描线102之间的区域裸露在外面;随后,如图5B所示,在光阻层19上形成像素电极层20,以覆盖所述导体层21、半导体层17以及位于第一扫描线101与第二扫描线102之间的区域。最后,如图5C所示,通过剥离工艺去除光阻层19以及位于光阻层19上的像素电极层20。
优选的,该半导体层17的材料为铟镓锌氧化物;该缓冲层12为氮化硅层、氧化硅层或氧化铝层。
本发明的阵列基板的制作方法包括:基板;在基板上形成缓冲层;在缓冲层内形成源极和数据线,同时在缓冲层上形成第一栅极、第二栅极、第一扫描线以及第二扫描线;在源极、第一扫描线以及第二扫描线上形成半导体层;对位于第一扫描线以及第二扫描线上的半导体层进行导体化,以形成导体层;在半导体层上形成第一像素电极,同时在导体层上形成第二像素电极。本发明中阵列基板的制作方法,其工艺步骤较简单,提高了生产效率,减小了生产成本。
综上,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

1.一种阵列基板的制作方法,其特征在于,包括:
基板;
在所述基板上形成缓冲层;
在所述缓冲层内形成源极和数据线,同时在所述缓冲层上形成第一栅极、第二栅极、第一扫描线以及第二扫描线,其中,所述数据线与所述源极连接,所述第一栅极与所述第二栅极电性连接且环绕所述源极,所述第二扫描线与所述第一栅极以及所述第二栅极连接;
在所述源极、所述第一扫描线以及所述第二扫描线上形成半导体层;
对位于所述第一扫描线以及所述第二扫描线上的所述半导体层进行导体化,以形成导体层;
在所述半导体层上形成第一像素电极,同时在所述导体层上形成第二像素电极,其中,所述第二像素电极通过所述导体层使得所述第一扫描线以及所述第二扫描线连接。
2.根据权利要求1所述的阵列基板的制作方法,其特征在于,所述在所述缓冲层内形成源极和数据线,同时在所述缓冲层上形成第一栅极、第二栅极、第一扫描线以及第二扫描线的步骤,包括:
在所述缓冲层上形成一光阻层;
通过黄光工艺和蚀刻工艺,形成第一栅极区域、第二栅极区域、第一扫描线区域、第二扫描线区域、源极区域以及数据线区域;
在所述光阻层上形成金属层,以覆盖所述第一栅极区域、所述第二栅极区域、所述第一扫描线区域、所述第二扫描线区域、所述源极区域以及所述数据线区域;
通过剥离工艺,去除所述光阻层以及位于所述光阻层上的所述金属层。
3.根据权利要求1所述的阵列基板的制作方法,其特征在于,所述在所述源极、所述第一扫描线以及所述第二扫描线上形成半导体层的步骤,包括:
在所述缓冲层上形成一绝缘层,以覆盖所述源极、所述数据线、所述第一栅极、所述第二栅极、所述第一扫描线以及所述第二扫描线;
在所述绝缘层上形成光阻层,以使得所述源极、所述第一扫描线以及所述第二扫描线裸露在外面;
在所述源极、所述第一扫描线以及所述第二扫描线上形成所述半导体层。
4.根据权利要求3所述的阵列基板的制作方法,其特征在于,所述在所述绝缘层上形成光阻层,以使得所述源极、所述第一扫描线以及所述第二扫描线裸露在外面的步骤,包括:
在所述绝缘层上形成所述光阻层;
通过黄光工艺与蚀刻工艺,使得所述源极、所述第一扫描线以及所述第二扫描线裸露在外面。
5.根据权利要求3所述的阵列基板的制作方法,其特征在于,所述在所述源极、所述第一扫描线以及所述第二扫描线上形成所述半导体层的步骤,包括:
在所述光阻层上形成所述半导体层,以覆盖所述第一扫描线、所述第二扫描线以及所述源极;
通过剥离工艺去除所述光阻层上的所述半导体层。
6.根据权利要求1所述的阵列基板的制作方法,其特征在于,所述对位于所述第一扫描线以及所述第二扫描线上的所述半导体层进行导体化,以形成导体层的步骤,包括:
通过黄光工艺,形成光阻层,以使得位于所述第一扫描线以及所述第二扫描线上的所述半导体层裸露在外面;
对位于所述第一扫描线以及所述第二扫描线上的所述半导体层进行导体化。
7.根据权利要求6所述的阵列基板的制作方法,其特征在于,可使用氩气、氮气以及氨气对位于所述第一扫描线以及所述第二扫描线上的所述半导体层进行导体化。
8.根据权利要求1所述的阵列基板的制作方法,其特征在于,所述在所述半导体层上形成第一像素电极,同时在所述导体层上形成第二像素电极的步骤,包括:
通过黄光工艺,形成光阻层,以使得所述导体层、所述半导体层以及位于所述第一扫描线与所述第二扫描线之间的区域裸露在外面;
在所述光阻层上形成像素电极层,以覆盖所述导体层、 所述半导体层以及位于所述第一扫描线与所述第二扫描线之间的区域;
通过剥离工艺去除所述光阻层以及位于所述光阻层上的所述像素电极层。
9.根据权利要求1所述的阵列基板的制作方法,其特征在于,所述半导体层的材料为铟镓锌氧化物。
10.根据权利要求1所述的阵列基板的制作方法,其特征在于,所述缓冲层为氮化硅层、氧化硅层或氧化铝层。
CN201710197970.9A 2017-03-29 2017-03-29 一种阵列基板的制作方法 Active CN106887406B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201710197970.9A CN106887406B (zh) 2017-03-29 2017-03-29 一种阵列基板的制作方法
US15/571,346 US10355031B2 (en) 2017-03-29 2017-05-03 Method for manufacturing array substrate
PCT/CN2017/082814 WO2018176567A1 (zh) 2017-03-29 2017-05-03 一种阵列基板的制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710197970.9A CN106887406B (zh) 2017-03-29 2017-03-29 一种阵列基板的制作方法

Publications (2)

Publication Number Publication Date
CN106887406A CN106887406A (zh) 2017-06-23
CN106887406B true CN106887406B (zh) 2019-11-15

Family

ID=59181517

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710197970.9A Active CN106887406B (zh) 2017-03-29 2017-03-29 一种阵列基板的制作方法

Country Status (3)

Country Link
US (1) US10355031B2 (zh)
CN (1) CN106887406B (zh)
WO (1) WO2018176567A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI696026B (zh) * 2019-04-24 2020-06-11 友達光電股份有限公司 畫素陣列基板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102683353A (zh) * 2012-04-05 2012-09-19 南京中电熊猫液晶显示科技有限公司 用于显示设备的阵列基板及其制造方法
CN104779272A (zh) * 2015-04-10 2015-07-15 京东方科技集团股份有限公司 薄膜晶体管和阵列基板及其制作方法、显示装置
CN105977206A (zh) * 2016-06-27 2016-09-28 深圳市华星光电技术有限公司 一种阵列基板的制造方法及阵列基板

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5324673A (en) * 1992-11-19 1994-06-28 Motorola, Inc. Method of formation of vertical transistor
EP0683507B1 (en) * 1993-12-07 2002-05-29 Kabushiki Kaisha Toshiba Manufacture of a display device
KR20050081053A (ko) * 2004-02-12 2005-08-18 삼성전자주식회사 박막 트랜지스터 표시판 및 그의 제조방법
WO2011052411A1 (en) * 2009-10-30 2011-05-05 Semiconductor Energy Laboratory Co., Ltd. Transistor
TWI508269B (zh) * 2013-06-20 2015-11-11 Au Optronics Corp 畫素結構
CN105914213B (zh) * 2016-06-01 2019-02-22 深圳市华星光电技术有限公司 阵列基板及其制备方法
CN106129086B (zh) * 2016-07-21 2019-04-30 深圳市华星光电技术有限公司 Tft基板及其制作方法
KR20180055701A (ko) * 2016-11-17 2018-05-25 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
KR20180066848A (ko) * 2016-12-09 2018-06-19 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 및 반도체 장치의 제작 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102683353A (zh) * 2012-04-05 2012-09-19 南京中电熊猫液晶显示科技有限公司 用于显示设备的阵列基板及其制造方法
CN104779272A (zh) * 2015-04-10 2015-07-15 京东方科技集团股份有限公司 薄膜晶体管和阵列基板及其制作方法、显示装置
CN105977206A (zh) * 2016-06-27 2016-09-28 深圳市华星光电技术有限公司 一种阵列基板的制造方法及阵列基板

Also Published As

Publication number Publication date
US10355031B2 (en) 2019-07-16
US20190157315A1 (en) 2019-05-23
CN106887406A (zh) 2017-06-23
WO2018176567A1 (zh) 2018-10-04

Similar Documents

Publication Publication Date Title
CN107482064B (zh) 薄膜晶体管及其制作方法以及阵列基板
CN103365014B (zh) 显示面板制作方法、显示面板及显示装置
CN103869559B (zh) 像素结构
CN104915052B (zh) 触控显示装置及其制备方法、电子设备
CN104637955B (zh) 一种阵列基板及其制作方法、显示装置
CN104345511B (zh) 像素结构及其制造方法、显示面板
CN106935546B (zh) 阵列基板的制备方法、阵列基板、显示面板和显示装置
CN107132710A (zh) 一种阵列基板及其制备方法、显示面板
CN107039351B (zh) Tft基板的制作方法及tft基板
CN107179637A (zh) 阵列基板、液晶显示面板和液晶显示装置
CN107833895A (zh) 显示面板及其制造方法、显示装置
CN103474439B (zh) 一种显示装置、阵列基板及其制作方法
CN105159002B (zh) 像素结构
CN106887406B (zh) 一种阵列基板的制作方法
CN104062786B (zh) 液晶显示器的连接垫结构及其制作方法
CN104576527A (zh) 一种阵列基板的制备方法
CN103985708A (zh) 薄膜晶体管阵列基板及其制作方法
CN104733477A (zh) 阵列基板及其制作方法、显示面板、显示装置
CN103560113A (zh) 一种阵列结构及其制作方法、阵列基板和显示装置
CN103700668A (zh) 一种阵列基板及其制备方法和显示装置
CN102931091A (zh) 一种主动矩阵式平面显示装置、薄膜晶体管及其制作方法
CN205080335U (zh) 一种阵列基板和一种内嵌式触控显示装置
CN107731748A (zh) 显示装置、阵列基板及其制造方法
CN104269412B (zh) Tft阵列基板、tft阵列基板的制作方法及显示装置
CN107919321A (zh) Ffs型薄膜晶体管阵列基板及其制作方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20171027

Address after: 518132 No. 9-2 Ming Avenue, Gongming street, Guangming District, Guangdong, Shenzhen

Applicant after: Shenzhen Huaxing photoelectric semiconductor display technology Co., Ltd.

Address before: 518132 9-2, Guangming Road, Guangming New District, Guangdong, Shenzhen

Applicant before: Shenzhen Huaxing Optoelectronic Technology Co., Ltd.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant