WO2015192397A1 - 薄膜晶体管基板的制造方法 - Google Patents

薄膜晶体管基板的制造方法 Download PDF

Info

Publication number
WO2015192397A1
WO2015192397A1 PCT/CN2014/081433 CN2014081433W WO2015192397A1 WO 2015192397 A1 WO2015192397 A1 WO 2015192397A1 CN 2014081433 W CN2014081433 W CN 2014081433W WO 2015192397 A1 WO2015192397 A1 WO 2015192397A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
gate insulating
film transistor
oxide semiconductor
Prior art date
Application number
PCT/CN2014/081433
Other languages
English (en)
French (fr)
Inventor
李文辉
曾志远
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/381,920 priority Critical patent/US9685471B2/en
Publication of WO2015192397A1 publication Critical patent/WO2015192397A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of planar display, and more particularly to a method of fabricating a thin film transistor substrate. Background technique
  • the flat display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the existing flat display devices mainly include a liquid crystal display device (LCD) and an organic electroluminescence display device (OLED). Since the organic electroluminescent device has self-luminescence, no backlight, contrast is required. High performance, thin thickness, wide viewing angle, fast response, flexible panel, wide temperature range, simple structure and simple process are considered to be the next generation of flat panel display emerging applications.
  • OLED display devices are The drive types can be divided into PM-OLED (passive OLED) and AM-OLED (active OLED) 0
  • the pixel driving circuit of the AM-OLED generally uses a TFT (Thin Film Transistor).
  • TFT substrate of the AM-OLED is driven by two types of TFTs: a switching transistor and a driving transistor, and the switching transistor and the driving transistor are required to pass.
  • GI via gate insulator via
  • GI via requires an additional lithography process, including film formation process, yellow process, etching, Process steps such as stripping.
  • Oxide semiconductors have high electron mobility (oxide semiconductor mobility)
  • amorphous silicon (a-Si) mobility is only 0.5 ⁇ 0.8cm 2 /Vs
  • LTPS low temperature polysilicon
  • oxide semiconductor process is simple, and amorphous silicon process compatibility It can be applied to the fields of liquid crystal display devices, organic light-emitting display devices, flexible displays, etc., and is compatible with high-generation production lines. It can be applied to large, medium and small-sized displays, and has good application development prospects.
  • common oxide semiconductor thin film transistors include an oxide semiconductor thin film transistor of an Etch Stopper (ES) structure and an oxide semiconductor thin film transistor of a back channel etching (BCE) structure.
  • ES Etch Stopper
  • BCE back channel etching
  • the more mature structure is the ESL (etch barrier) structure.
  • the ESL is fabricated by an additional lithography process (including film formation process, yellow process, etching, stripping, etc.) to increase cost and reduce yield.
  • FIG. 1 is a schematic structural diagram of an oxide semiconductor thin film transistor of a conventional etch barrier structure.
  • an etch barrier layer is formed ( Etch Stopper Layer (ESL) 300 for protecting the oxide semiconductor layer 100 from being subjected to subsequent processes such as metal source/drain electrode 200 etching processes Destruction, thereby improving the stability of the oxide semiconductor thin film transistor, but to create an etch barrier layer requires a lithography process, a lithography process including film formation, exposure, development, etching, stripping, etc., thus making an additional
  • the layer etch barrier will greatly increase production costs, which in turn will reduce production yield. Summary of the invention
  • An object of the present invention is to provide a method for fabricating a thin film transistor substrate, which simultaneously performs via processing and patterned etch barrier on a gate insulating layer in the same lithography process, and a method for manufacturing a thin film transistor substrate In comparison, one lithography process can be reduced, and the preparation efficiency is improved. At the same time, the aperture ratio is increased by opening on the transparent conductive layer.
  • the present invention provides a method of fabricating a thin film transistor substrate, comprising the steps of:
  • Step 1 Providing a substrate
  • Step 2 depositing a first metal layer on the substrate, and patterning the first metal layer to form a gate of the switching transistor and the driving transistor;
  • Step 3 depositing a gate insulating layer on the gate and the substrate;
  • Step 4 depositing an oxide semiconductor layer on the gate insulating layer, and patterning the oxide semiconductor layer;
  • Step 5 depositing an etch barrier layer on the gate insulating layer and the oxide semiconductor layer;
  • Step 6. performing a via process on the gate insulating layer by using a photolithography process and patterning the etch barrier layer;
  • Step 7 forming a source/drain on the etch barrier layer
  • Step 8 Form a protective layer and a flat layer on the etch stop layer and the source/drain sequentially; Step 9. Form a transparent conductive layer on the flat layer and the exposed portion of the source/drain, and pattern the Transparent conductive layer;
  • Step 10 sequentially forming a pixel defining layer and a photoresist gap on the flat layer and the transparent conductive layer.
  • the substrate is a transparent substrate.
  • the substrate is a glass substrate.
  • the photolithography process may adopt a halftone/gray tone for exposure, dry etching or ashing after exposure, and stripping the photoresist layer to form an etch barrier layer of a predetermined pattern, and The gate insulating layer is subjected to via processing.
  • the photolithography process may also be exposed by a conventional method, dry etching after exposure, and stripping the photoresist layer to form an etching barrier layer of a predetermined pattern, and performing the gate insulating layer. Hole handling.
  • the via processing is performed by etching the gate insulating layer and the etch barrier at the via to expose the gate of the driving transistor.
  • the oxide semiconductor layer is an indium gallium zinc oxide semiconductor layer.
  • the transparent conductive layer is made of indium tin oxide.
  • the transparent conductive layer is opened to increase the aperture ratio.
  • the invention also provides a method for manufacturing a thin film transistor substrate, comprising the following steps: Step 1: providing a substrate;
  • Step 2 depositing a first metal layer on the substrate, and patterning the first metal layer to form a gate of the switching transistor and the driving transistor;
  • Step 3 depositing a gate insulating layer on the gate and the substrate;
  • Step 4 depositing an oxide semiconductor layer on the gate insulating layer, and patterning the oxide semiconductor layer;
  • Step 5 depositing an etch stop layer on the gate insulating layer and the oxide semiconductor layer; Step 6. performing a via process on the gate insulating layer by using a photolithography process and patterning the etch stop layer;
  • Step 7 forming a source/drain on the etch barrier layer
  • Step 8. sequentially forming a protective layer and a flat layer on the etch barrier layer and the source/drain;
  • Step 9. forming a transparent conductive layer on the flat layer and the exposed partial source/drain, and patterning the transparent conductive layer;
  • Step 10 sequentially forming a pixel defining layer and a photoresist gap on the flat layer and the transparent conductive layer;
  • the substrate is a transparent substrate
  • the substrate is a glass substrate
  • the photolithography process may also be exposed by a conventional method, dry etching after exposure, and stripping the photoresist layer to form an etching barrier layer of a predetermined pattern, and performing the gate insulating layer.
  • Hole treatment
  • the via processing is performed by etching the gate insulating layer and the etch stop layer at the via hole to expose the gate of the driving transistor;
  • the oxide semiconductor layer is an indium gallium zinc oxide semiconductor layer
  • the transparent conductive layer is made of indium tin oxide
  • the transparent conductive layer is opened to increase the aperture ratio.
  • the present invention provides a method for fabricating a thin film transistor substrate in which a gate insulating layer is simultaneously subjected to via processing and a patterned etch barrier layer in the same photolithography process, that is, a gate insulating layer is formed. After that, the lithography process is not performed, and the oxide semiconductor pattern is directly formed. Then, after the etch barrier film is formed, the gate insulating layer vias and the etch barrier layer are patterned into the same lithography process, which can reduce one lithography compared with the existing thin film transistor substrate manufacturing method. The process improves the preparation efficiency. At the same time, the aperture ratio is increased by opening on the transparent conductive layer.
  • FIG. 1 is a schematic view showing the structure of an existing oxide semiconductor thin film transistor having an etch barrier structure
  • FIG. 2 is a flow chart showing a method of manufacturing a thin film transistor substrate of the present invention
  • 3 to 10 are schematic views showing respective steps of a method of manufacturing a thin film transistor substrate of the present invention.
  • the present invention provides a method for manufacturing a thin film transistor substrate, comprising the following steps:
  • Step 1 Provide a substrate 20.
  • the substrate 20 is a transparent substrate, preferably a glass substrate or a plastic substrate. In the present embodiment, the substrate 20 is a glass substrate.
  • Step 2 Deposit a first metal layer on the substrate 20 and pattern the first metal layer to form a gate electrode 21 of a switching transistor and a driving TFT.
  • the first metal layer is formed on the substrate 20 by deposition, and the first metal layer is exposed, developed, and etched through a mask or a half mask to form a gate 21 of a predetermined pattern.
  • Step 3 depositing a gate insulating layer 22 0 on the gate 21 and the substrate 20
  • the gate insulating layer 22 generally includes one of silicon oxide, silicon nitride, or a combination thereof.
  • Step 4 depositing an oxide semiconductor layer 23 on the gate insulating layer 22, and patterning the oxide semiconductor layer 23 0
  • the oxide semiconductor layer 23 is an IGZO (Indium Gallium Zinc Oxide) semiconductor layer.
  • the oxide semiconductor layer 23 is formed in a manner similar to that of the above-described gate electrode 22, and will not be described here.
  • Step 5 Depositing an etch barrier layer on the gate insulating layer 22 and the oxide semiconductor layer 23
  • Step 6 Perform a via process on the gate insulating layer 22 and pattern the etch stop layer 24 by a photolithography process.
  • the photolithography process may be exposed by a halftone/gray tone, dried or ashed after exposure, and the photoresist layer is stripped to form a predetermined pattern of the etch barrier layer 24 and the gate electrode.
  • the insulating layer 22 is subjected to via processing.
  • the photolithography process can also be exposed by a conventional method, dry etching after exposure, and stripping the P photoresist layer to form a predetermined pattern of the etch barrier layer 24, and performing via processing on the gate insulating layer 22.
  • the via processing is performed by etching the gate insulating layer 22 and the etch barrier layer 24 at the via hole to expose the gate 21 0 of the driving transistor.
  • Step 7 Form a source/drain 25 0 on the etch stop layer 24.
  • the source/drain 25 is formed in a manner similar to that of the gate 22 described above, and is not used herein. Cheer.
  • Step 8 A protective layer 26 and a planar layer 27 are sequentially formed on the etch barrier layer 24 and the source/drain electrodes 25.
  • the protective layer 26 and the flat layer 27 are formed in a manner similar to the manner in which the gate electrode 22 is formed, and will not be described herein.
  • Step 9 Form a transparent conductive layer 28 on the flat layer 27 and the exposed portion of the source/drain 24, and pattern the transparent conductive layer 28.
  • the transparent conductive layer 28 is made of indium tin oxide in a manner similar to that of the above-described gate electrode 22, and will not be described here.
  • the transparent conductive layer 28 is opened to increase the aperture ratio.
  • Step 10 sequentially forming a pixel defining layer 29 and a photoresist spacer 30 on the flat layer 27 and the transparent conductive layer 28.
  • the pixel defining layer 29 and the photoresist spacer 30 are formed in a manner similar to the manner in which the gate 22 is formed, and are not described herein.
  • the method for fabricating a thin film transistor substrate provided by the present invention simultaneously performs via processing and etching barrier layer in the same photolithography process, that is, after the gate insulating layer is formed into a film, the photolithography process is not performed.
  • Directly fabricating an oxide semiconductor pattern, and then forming a film after etching the barrier layer The gate insulating layer via and the etch barrier layer are patterned into the same lithography process, which can reduce one lithography process and improve the preparation efficiency compared with the existing thin film transistor substrate manufacturing method.
  • the aperture ratio is increased by opening on the transparent conductive layer.

Abstract

一种薄膜晶体管基板的制造方法，在同一道光刻制程中同时对栅极绝缘层（22）进行过孔处理及图案化刻蚀阻挡层（24），即栅绝缘层（22）成膜后先不进行光刻制程，直接线制作氧化物半导体图案，然后在刻蚀阻挡层（24）成膜后，栅绝缘层（22）过孔与刻蚀阻挡层（24）图案化合并为同一道光刻制程，与现有的薄膜晶体管基板的制造方法相比，可减少一道光刻制程，提高了制备效率。同时通过在透明导电层上开口，提高了开口率。

Description

薄膜晶体管基板的制造方法 技术领域
本发明涉及平面显示领域，尤其涉及一种薄膜晶体管基板的制造方法。 背景技术
平面显示器件具有机身薄、 省电、 无辐射等众多优点，得到了广泛的 应用。现有的平面显示器件主要包括液晶显示器件 ( Liquid Crystal Display , LCD )及有机电致发光显示器件 ( Organic Light Emitting Display , OLED \ 有机电致发光器件由于同时具备自发光，不需背光源、 对比度高、 厚 度薄、 视角广、 反应速度快、 可用于挠曲性面板、 使用温度范围广、 构造 及制程较简单等优异之特性，被认为是下一代的平面显示器新兴应用技术。 OLED 显示器件按照驱动类型可分为 PM-OLED (无源 OLED)和 AM-OLED (有源 OLED)0
AM-OLED的像素驱动电路通常采用 TFT(Thin Film Transistor ,薄膜场 效应晶体管）， AM-OLED的 TFT基板通过需要 2种 TFT来驱动：开关晶体 管与驱动晶体管，所述开关晶体管与驱动晶体管需通过 GI via (栅极绝缘层 过孔)桥接， GI via需额外一道光刻制程，包括成膜制程、 黄光制程、 蚀刻、 剥离等制程工序。
氧化物半导体由于具有较高的电子迀移率（氧化物半导体迀移率
>10cm2/Vs ,非晶硅（ a-Si )迀移率仅 0.5〜0.8cm2/Vs ) ,而且相比低温多晶硅 ( LTPS ) ,氧化物半导体制程简单，与非晶硅制程相容性较高，可以应用于 液晶显示装置、 有机发光显示装置、 柔性显示（ Flexible )等领域，且与高 世代生产线兼容，可应用于大中小尺寸显示，具有良好的应用发展前景， 为当前业界硏究热门。
目前，常见的氧化物半导体薄膜晶体管有：刻蚀阻挡 ( Etch Stopper , ES )结构的氧化物半导体薄膜晶体管和背沟道（ Back channel etching ,BCE ) 结构的氧化物半导体薄膜晶体管。
当前较为成熟的结构是 ESL (刻蚀阻挡层）结构，通常 ESL的制作需 额外一道光刻制程（包括成膜制程、 黄光制程、 蚀刻、 剥离等制程工序）， 增加成本，降低良率。
请参阅图 1 ,为现有的刻蚀阻挡结构的氧化物半导体薄膜晶体管的结构 示意图，其在氧化物半导体层 100形成后及金属源 /漏电极 200形成前，制 作一层刻蚀阻挡层（ Etch Stopper Layer , ESL ) 300 ,用于保护氧化物半导 体层 100 ,避免其在后续的制程（如金属源 /漏电极 200蚀刻等制程）中遭 破坏，进而提升了氧化物半导体薄膜晶体管稳定性，但制作一层刻蚀阻挡 层需增加一道光刻制程，一道光刻制程包括成膜、 曝光、 显影、 蚀刻、 剥 离等工序，因而额外制作一层刻蚀阻挡层将大大增加生产成本，进而降低 生产良率。 发明内容
本发明的目的在于提供一种薄膜晶体管基板的制造方法，在同一道光 刻制程中同时对栅极绝缘层进行过孔处理及图案化刻蚀阻挡层，与现有的 薄膜晶体管基板的制造方法相比，可减少一道光刻制程，提高了制备效率。 同时通过在透明导电层上开口，提高了开口率。
为实现上述目的，本发明提供一种薄膜晶体管基板的制造方法，包括 以下步骤：
步骤 1、 提供基板；
步骤 2、在所述基板上沉积第一金属层，并图案化该第一金属层，以形 成开关晶体管和驱动晶体管的栅极；
步骤 3、 在所述栅极与基板上沉积栅极绝缘层；
步骤 4、在所述栅极绝缘层上沉积氧化物半导体层，并图案化所述氧化 物半导体层； 步骤 5、 在所述栅极绝缘层和氧化物半导体层上沉积刻蚀阻挡层； 步骤 6、采用一道光刻制程对栅极绝缘层进行过孔处理并图案化刻蚀阻 挡层；
步骤 7、 在所述刻蚀阻挡层上形成源 /漏极；
步骤 8、 在所述刻蚀阻挡层及源 /漏极上依次形成保护层、 平坦层； 步骤 9、 在所述平坦层及露出的部分源 /漏极上形成透明导电层，并图 案化该透明导电层；
步骤 10、 在所述平坦层及透明导电层上依次形成像素定义层及光阻间 隙物。
所述基板为透明基板。
所述基板为玻璃基板。
所述步骤 6中，所述光刻制程可采用半色调 /灰色调进行曝光，曝光后 进行干蚀刻或者灰化处理，并剥除光阻层，以形成预定图案的刻蚀阻挡层， 并对栅极绝缘层进行过孔处理。
所述步骤 ό中，所述光刻制程也可采用常规方法进行曝光，曝光后进 行干蚀刻，并剥除光阻层，以形成预定图案的刻蚀阻挡层，并对栅极绝缘 层进行过孔处理。 所述步骤 ό中，所述过孔处理是通过将过孔处的栅极绝缘层、 刻蚀阻 挡层刻蚀掉，露出驱动晶体管的栅极。
所述氧化物半导体层为铟镓锌氧化物半导体层。
所述透明导电层由氧化铟锡制成。
所述步骤 9中，在透明导电层上开口以提高开口率。
本发明还提供一种薄膜晶体管基板的制造方法，包括以下步骤： 步骤 1、 提供基板；
步骤 2、在所述基板上沉积第一金属层，并图案化该第一金属层，以形 成开关晶体管和驱动晶体管的栅极；
步骤 3、 在所述栅极与基板上沉积栅极绝缘层；
步骤 4、在所述栅极绝缘层上沉积氧化物半导体层，并图案化所述氧化 物半导体层；
步骤 5、 在所述栅极绝缘层和氧化物半导体层上沉积刻蚀阻挡层； 步骤 6、采用一道光刻制程对栅极绝缘层进行过孔处理并图案化刻蚀阻 挡层；
步骤 7、 在所述刻蚀阻挡层上形成源 /漏极；
步骤 8、 在所述刻蚀阻挡层及源 /漏极上依次形成保护层、 平坦层； 步骤 9、 在所述平坦层及露出的部分源 /漏极上形成透明导电层，并图 案化该透明导电层；
步骤 10、 在所述平坦层及透明导电层上依次形成像素定义层及光阻间 隙物；
所述基板为透明基板；
所述基板为玻璃基板；
所述步骤 ό中，所述光刻制程也可采用常规方法进行曝光，曝光后进 行干蚀刻，并剥除光阻层，以形成预定图案的刻蚀阻挡层，并对栅极绝缘 层进行过孔处理；
所述步骤 ό中，所述过孔处理是通过将过孔处的栅极绝缘层、 刻蚀阻 挡层刻蚀掉，露出驱动晶体管的栅极；
所述氧化物半导体层为铟镓锌氧化物半导体层；
所述透明导电层由氧化铟锡制成；
所述步骤 9中，在透明导电层上开口以提高开口率。
本发明的有益效果：本发明提供的一种薄膜晶体管基板的制造方法， 在同一道光刻制程中同时对栅极绝缘层进行过孔处理及图案化刻蚀阻挡 层，即栅绝缘层成膜后，先不进行光刻制程，直接线制作氧化物半导体图 案，然后在刻蚀阻挡层成膜后，栅绝缘层过孔与刻蚀阻挡层图案化合并为 同一道光刻制程，与现有的薄膜晶体管基板的制造方法相比，可减少一道 光刻制程，提高了制备效率。 同时通过在透明导电层上开口，提高了开口 率。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本 发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发 明加以限制。 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明 的技术方案及其它有益效果显而易见。
附图中，
图 1 为现有的具有刻蚀阻挡结构的氧化物半导体薄膜晶体管的结构示 意图；
图 2为本发明薄膜晶体管基板的制造方法的流程图；
图 3至图 10为本发明薄膜晶体管基板的制造方法的各步骤的示意图。 具体实施方式 为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图 2 ,并参考图 3至图 10 ,本发明提供一种薄膜晶体管基板的 制造方法，包括以下步骤：
步骤 1、 提供基板 20。
所述基板 20为透明基板，优选玻璃基板或塑料基板，在本实施例中， 所述基板 20为玻璃基板。
步骤 2、 在所述基板 20上沉积第一金属层，并图案化该第一金属层， 以形成开关晶体管 ( Switching TFT )和驱动晶体管 ( Driving TFT )的栅极 21。
具体地，在所述基板 20上通过沉积形成所述第一金属层，再通过掩模 板或半掩模板对该第一金属层进行曝光、 显影、 蚀刻以形成预定图案的栅 极 21。
步骤 3、 在所述栅极 21与基板 20上沉积栅极绝缘层 220
所述栅极绝缘层 22—般包括氧化硅、 氮化硅其中之一或其组合。
步骤 4、 在所述栅极绝缘层 22上沉积氧化物半导体层 23 ,并图案化所 述氧化物半导体层 230 所述氧化物半导体层 23为 IGZO (铟镓锌氧化物)半导体层。
所述氧化物半导体层 23的形成方式与上述栅极 22的形成方式类似， 在此不作螯述。
步骤 5、在所述栅极绝缘层 22和氧化物半导体层 23上沉积刻蚀阻挡层
24。
步骤 6、 采用一道光刻制程对栅极绝缘层 22进行过孔处理并图案化刻 蚀阻挡层 24。
具体的，所述光刻制程可采用半色调 /灰色调进行曝光，曝光后进行干 蚀刻或者灰化处理，并剥除光阻层，以形成预定图案的刻蚀阻挡层 24 ,并 对栅极绝缘层 22进行过孔处理。
所述光刻制程也可采用常规方法进行曝光，曝光后进行干蚀刻，并剥 P余光阻层，以形成预定图案的刻蚀阻挡层 24 ,并对栅极绝缘层 22进行过孔 处理。
所述过孔处理是通过将过孔处的栅极绝缘层 22、刻蚀阻挡层 24刻蚀掉， 露出驱动晶体管的栅极 210
步骤 7、 在所述刻蚀阻挡层 24上形成源 /漏极 250
所述源 /漏极 25的形成方式与上述栅极 22的形成方式类似，在此不作 螯述。
步骤 8、 在所述刻蚀阻挡层 24及源 /漏极 25上依次形成保护层 26、 平 坦层 27。
所述保护层 26、平坦层 27的形成方式与上述栅极 22的形成方式类似， 在此不作螯述。
步骤 9、 在所述平坦层 27及露出的部分源 /漏极 24上形成透明导电层 28 ,并图案化该透明导电层 28。
所述透明导电层 28由氧化铟锡制成，其形成方式与上述栅极 22的形 成方式类似 ,在此不作螯述。
具体的，在透明导电层 28上开口以提高开口率。
步骤 10、 在所述平坦层 27及透明导电层 28上依次形成像素定义层 29 及光阻间隙物 30。
所述像素定义层 29及光阻间隙物 30的形成方式与上述栅极 22的形成 方式类似，在此不作螯述。
综上所述，本发明提供的一种薄膜晶体管基板的制造方法，在同一道 光刻制程中同时进行过孔处理及蚀刻阻挡层，即栅绝缘层成膜后，先不进 行光刻制程，直接线制作氧化物半导体图案，然后在刻蚀阻挡层成膜后， 栅绝缘层过孔与刻蚀阻挡层图案化合并为同一道光刻制程，与现有的薄膜 晶体管基板的制造方法相比，可减少一道光刻制程，提高了制备效率。 同 时通过在透明导电层上开口，提高了开口率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形 都应属于本发明权利要求的保护范围。

Claims

杈 利 要 求
1、 一种薄膜晶体管基板的制造方法，包括以下步骤：
步骤 1、 提供基板；
步骤 2、在所述基板上沉积第一金属层，并图案化该第一金属层，以形 成开关晶体管和驱动晶体管的栅极；
步骤 3、 在所述栅极与基板上沉积栅极绝缘层；
步骤 4、在所述栅极绝缘层上沉积氧化物半导体层，并图案化所述氧化 物半导体层；
步骤 5、 在所述栅极绝缘层和氧化物半导体层上沉积刻蚀阻挡层； 步骤 6、采用一道光刻制程对栅极绝缘层进行过孔处理并图案化刻蚀阻 挡层；
步骤 7、 在所述刻蚀阻挡层上形成源 /漏极；
步骤 8、 在所述刻蚀阻挡层及源 /漏极上依次形成保护层、 平坦层； 步骤 9、 在所述平坦层及露出的部分源 /漏极上形成透明导电层，并图 案化该透明导电层；
步骤 10、 在所述平坦层及透明导电层上依次形成像素定义层及光阻间 隙物。
2、 如权利要求 1所述的薄膜晶体管基板的制造方法，其中，所述基板 为透明基板。
3、 如权利要求 2所述的薄膜晶体管基板的制造方法，其中，所述基板 为玻璃基板。
4、 如权利要求 1所述的薄膜晶体管基板的制造方法，其中，所述步骤 6 中，所述光刻制程采用半色调 /灰色调进行曝光，曝光后进行干蚀刻或者 灰化处理，并剥除光阻层，以形成预定图案的刻蚀阻挡层，并对栅极绝缘 层进行过孔处理。
5、 如权利要求 1所述的薄膜晶体管基板的制造方法，其中，所述步骤 6中，所述光刻制程进行曝光，曝光后进行干蚀刻，并剥除光阻层，以形成 预定图案的刻蚀阻挡层，并对栅极绝缘层进行过孔处理。
6、 如权利要求 1所述的薄膜晶体管基板的制造方法，其中，所述步骤 6中，所述过孔处理是通过将过孔处的栅极绝缘层、刻蚀阻挡层刻蚀掉，露 出驱动晶体管的栅极。
7、 如权利要求 1所述的薄膜晶体管基板的制造方法，其中，所述氧化 物半导体层为铟镓锌氧化物半导体层。
8、 如权利要求 1所述的薄膜晶体管基板的制造方法，其中，所述透明 导电层由氧化铟锡制成。
9、 如权利要求 1所述的薄膜晶体管基板的制造方法，其中，所述步骤 9中，在透明导电层上开口以提高开口率。
10、 一种薄膜晶体管基板的制造方法，包括以下步骤：
步骤 1、 提供基板；
步骤 2、在所述基板上沉积第一金属层，并图案化该第一金属层，以形 成开关晶体管和驱动晶体管的栅极；
步骤 3、 在所述栅极与基板上沉积栅极绝缘层；
步骤 4、在所述栅极绝缘层上沉积氧化物半导体层，并图案化所述氧化 物半导体层；
步骤 5、 在所述栅极绝缘层和氧化物半导体层上沉积刻蚀阻挡层； 步骤 6、采用一道光刻制程对栅极绝缘层进行过孔处理并图案化刻蚀阻 挡层；
步骤 7、 在所述刻蚀阻挡层上形成源 /漏极；
步骤 8、 在所述刻蚀阻挡层及源 /漏极上依次形成保护层、 平坦层； 步骤 9、 在所述平坦层及露出的部分源 /漏极上形成透明导电层，并图 案化该透明导电层； 步骤 10、 在所述平坦层及透明导电层上依次形成像素定义层及光阻间 隙物；
其中，所述基板为透明基板；
其中，所述基板为玻璃基板；
其中，所述步骤 6中，所述光刻制程进行曝光，曝光后进行干蚀刻， 并剥除光阻层，以形成预定图案的刻蚀阻挡层，并对栅极绝缘层进行过孔 处理；
其中，所述步骤 ό中，所述过孔处理是通过将过孔处的栅极绝缘层、 刻蚀阻挡层刻蚀掉，露出驱动晶体管的栅极；
其中，所述氧化物半导体层为铟镓锌氧化物半导体层；
其中，所述透明导电层由氧化铟锡制成；
其中，所述步骤 9中，在透明导电层上开口以提高开口率。
PCT/CN2014/081433 2014-06-19 2014-07-02 薄膜晶体管基板的制造方法 WO2015192397A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/381,920 US9685471B2 (en) 2014-06-19 2014-07-02 Manufacturing method of thin film transistor substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410277297.6A CN104022079A (zh) 2014-06-19 2014-06-19 薄膜晶体管基板的制造方法
CN201410277297.6 2014-06-19

Publications (1)

Publication Number Publication Date
WO2015192397A1 true WO2015192397A1 (zh) 2015-12-23

Family

ID=51438770

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/081433 WO2015192397A1 (zh) 2014-06-19 2014-07-02 薄膜晶体管基板的制造方法

Country Status (3)

Country Link
US (1) US9685471B2 (zh)
CN (1) CN104022079A (zh)
WO (1) WO2015192397A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104362127A (zh) * 2014-11-21 2015-02-18 深圳市华星光电技术有限公司 薄膜晶体管基板的制作方法及制造设备
CN105789115A (zh) * 2016-04-26 2016-07-20 京东方科技集团股份有限公司 过孔的制作方法、阵列基板及其制作方法、显示装置
CN106229297B (zh) * 2016-09-18 2019-04-02 深圳市华星光电技术有限公司 Amoled像素驱动电路的制作方法
CN107658332A (zh) * 2017-10-25 2018-02-02 京东方科技集团股份有限公司 一种显示面板、显示装置及制作方法
CN108231553B (zh) * 2017-12-28 2020-08-28 深圳市华星光电半导体显示技术有限公司 薄膜晶体管的制作方法及阵列基板的制作方法
CN111668236A (zh) * 2020-06-08 2020-09-15 Tcl华星光电技术有限公司 阵列基板及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101071816A (zh) * 2006-05-12 2007-11-14 Lg.菲利浦Lcd株式会社 多晶硅薄膜晶体管阵列基板及其制造方法
CN101635276A (zh) * 2009-08-26 2010-01-27 友达光电股份有限公司 有机发光二极管触控面板及其制作方法
CN101894760A (zh) * 2010-06-10 2010-11-24 友达光电股份有限公司 薄膜晶体管及其制造方法
CN102122673A (zh) * 2010-11-30 2011-07-13 友达光电股份有限公司 氧化物半导体薄膜晶体管结构与其制作方法
CN102652330A (zh) * 2009-12-09 2012-08-29 夏普株式会社 半导体装置及其制造方法
US20120286264A1 (en) * 2010-05-14 2012-11-15 Takeshi Suzuki Flexible semiconductor device, method for manufacturing the same and image display device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4522660B2 (ja) * 2003-03-14 2010-08-11 シャープ株式会社 薄膜トランジスタ基板の製造方法
US8390771B2 (en) * 2008-09-08 2013-03-05 Sharp Kabushiki Kaisha Liquid crystal display device
WO2011161910A1 (ja) * 2010-06-22 2011-12-29 パナソニック株式会社 発光表示装置及びその製造方法
TWI488296B (zh) * 2012-06-14 2015-06-11 Au Optronics Corp 有機電激發光顯示面板及其製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101071816A (zh) * 2006-05-12 2007-11-14 Lg.菲利浦Lcd株式会社 多晶硅薄膜晶体管阵列基板及其制造方法
CN101635276A (zh) * 2009-08-26 2010-01-27 友达光电股份有限公司 有机发光二极管触控面板及其制作方法
CN102652330A (zh) * 2009-12-09 2012-08-29 夏普株式会社 半导体装置及其制造方法
US20120286264A1 (en) * 2010-05-14 2012-11-15 Takeshi Suzuki Flexible semiconductor device, method for manufacturing the same and image display device
CN101894760A (zh) * 2010-06-10 2010-11-24 友达光电股份有限公司 薄膜晶体管及其制造方法
CN102122673A (zh) * 2010-11-30 2011-07-13 友达光电股份有限公司 氧化物半导体薄膜晶体管结构与其制作方法

Also Published As

Publication number Publication date
US20160240567A1 (en) 2016-08-18
US9685471B2 (en) 2017-06-20
CN104022079A (zh) 2014-09-03

Similar Documents

Publication Publication Date Title
US9768323B2 (en) Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof
US9799677B2 (en) Structure of dual gate oxide semiconductor TFT substrate
WO2015100935A1 (zh) 阵列基板及其制造方法、以及显示装置
US9685461B2 (en) Display device, array substrate and method for manufacturing the same
US20160370621A1 (en) Array substrate, manufacturing method thereof and liquid crystal display
US9548324B2 (en) Array substrate and method for fabricating the same
WO2016173027A1 (zh) 薄膜晶体管阵列基板及其制作方法
US9825069B2 (en) Array substrate manufacturing method
WO2018006441A1 (zh) 薄膜晶体管、阵列基板及其制备方法
WO2015100898A1 (zh) 薄膜晶体管、tft阵列基板及其制造方法和显示装置
WO2015192397A1 (zh) 薄膜晶体管基板的制造方法
WO2016004668A1 (zh) 具有存储电容的tft基板的制作方法及该tft基板
WO2016176881A1 (zh) 双栅极tft基板的制作方法及其结构
WO2014166176A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
WO2015096292A1 (zh) 阵列基板及其制造方法、显示装置
WO2018119879A1 (zh) 薄膜晶体管及其制作方法
US9520320B2 (en) TFT array substrate, method of manufacturing the same, and display device
KR102318054B1 (ko) Tft 기판 및 이의 제조 방법
WO2015192417A1 (zh) Tft背板的制造方法及tft背板结构
WO2015067054A1 (zh) 互补式薄膜晶体管及其制备方法、阵列基板和显示装置
WO2014117512A1 (zh) 一种薄膜晶体管、薄膜晶体管驱动背板的制备方法及薄膜晶体管驱动背板
WO2015096307A1 (zh) 氧化物薄膜晶体管、显示器件、及阵列基板的制造方法
KR101415484B1 (ko) 유기 ｔｆｔ 어레이 기판 및 그 제조 방법
WO2015161523A1 (zh) 薄膜晶体管及有机发光二极管显示器制备方法
WO2015100859A1 (zh) 阵列基板及其制造方法和显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14381920

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14895361

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14895361

Country of ref document: EP

Kind code of ref document: A1