201205168 六、發明說明： 【發明所屬之技術領域】 [0001]本發明是有關於一種薄膜電晶體陣列板，特別是指一種 液晶顯示器用之薄臈電晶體陣列板。 【先兩技術】 [0002]參圖1、2A及2B，一種傳統之液晶顯示器用之薄膜電晶體 陣列板1，疋適用於八區域型（d〇main)液晶顯示器’其 包含：一基板11、複數相互平行之掃描線（％郎 lirie)12、複數與該等掃描線12相隔、相交又且與該等 掃描線1 2共同將該基板11界定出複數像素區丨丨丨之資料線 ! (data line)13、複數分別形成在該等像素區lu之第 一薄膜電晶體14及第二薄膜電晶體15、複數分別形成在 該等像素區111並分別具有相間隔設置之一第一區161與 一第二區162之像素電極16、複數分別位於該等像素區 111並平行於該等掃描線〗2且界於兩相鄰之掃描線12之間 之共用（common)電極17、一上介電:詹、一下介電層 182，及一具有相間隔設置之一第一段191與一第二段 192 之儲存電容（st〇rage capacitor)電極 19。 4*- [0003] 每一第一薄膜電晶體14包括一與其相對應之掃描線丨2電 連接之閘極141、一與其相對應之資料線13電連接之源極 142 ’及一汲極143。每一第二薄膜電晶體15包括一與其 對應之第一薄膜電晶體14之閘極141連接之閘極丨51、一 與其對應之第一薄膜電晶體14之汲極143電連接之源極 152，及一汲極153。 [0004] 每一像素電極16之第一區161與第二區162是分別與其對 099123371 表單編號A0101 第4頁/共34頁 0992041165-0 201205168 應之第一薄膜電晶體14之汲極143與第二薄膜電晶體15之 $及極153電連接。 [〇〇〇5]該等共用電極17是形成在該等像素電極16之下方，且于 其平行方向上與其兩相鄰之像素區lu之共用電極17相連 接0 [0006]201205168 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a thin film transistor array panel, and more particularly to a thin germanium transistor array panel for a liquid crystal display. [First two technologies] [0002] Referring to Figures 1, 2A and 2B, a conventional thin film transistor array panel 1 for liquid crystal displays, suitable for an eight-zone (d〇main) liquid crystal display, which comprises: a substrate 11 And a plurality of scanning lines parallel to each other (% lang lirie) 12, the plurality of scanning lines 12 are spaced apart from each other, and intersect with the scanning lines 12 to define the data lines of the plurality of pixel regions together with the scanning lines 12! (data line) 13. The first thin film transistor 14 and the second thin film transistor 15 respectively formed in the pixel regions lu are respectively formed in the pixel regions 111 and respectively have one of the first regions a pixel electrode 16 of a second region 162 and a plurality of common electrodes 17 and a plurality of pixel electrodes 111 respectively located in the pixel region 111 and parallel to the scan lines 2 and between the adjacent scan lines 12 The upper dielectric: Zhan, the lower dielectric layer 182, and a storage capacitor electrode 19 having a first segment 191 and a second segment 192 spaced apart from each other. 4*- [0003] Each of the first thin film transistors 14 includes a gate 141 electrically connected to the corresponding scanning line 2, a source 142' electrically connected to the corresponding data line 13 and a drain 143. Each of the second thin film transistors 15 includes a gate 丨 51 connected to the gate 141 of the corresponding first thin film transistor 14 and a source 152 electrically connected to the drain 143 of the corresponding first thin film transistor 14 . , and a bungee 153. [0004] The first region 161 and the second region 162 of each pixel electrode 16 are respectively opposite to the gate 143 of the first thin film transistor 14 of 099123371 Form No. A0101 Page 4 / Total 34 Page 0992041165-0 201205168 The second thin film transistor 15 is electrically connected to the pole 153. [〇〇〇5] The common electrodes 17 are formed under the pixel electrodes 16 and are connected to the common electrode 17 of the pixel regions lu adjacent thereto in the parallel direction. [0006]
[0007][0007]
每一儲存電容電極19是位於其對應之像素電極16下方並 位於其對應之共用電極17上方，且每一儲存電容電極19 之第一段191與第二段192是分別與其對應之像素電極16 之第一區161及第二區192電連接。 在該傳統之液晶顯示器用之薄膜電晶體陣列板丨中，該等 掃描線12、閘極141、151及共用電極17是分別形成在該 基板11上並由一第一圖案化（patterned)金屬層（Mp所 界疋而成，該下介電層182是形成在該第一圖案化金屬層 )上，該等資料線丨3、源極mi、151、汲極143、 153與該等儲存電容電極19是分別形成在該下介電層 上，並由一第二圖案化金屬層（^)所界定而成；該上介 電層181是形成表該第二圖案化金屬層（M)上；該等像素 電極16是分別形成在該上介電層181上並由一圖案化透明 導電層（transparent conductive layer，簡稱 TCL) 所界疋而成。因此，每一像素區Hi内之共用電極17、下 介電層182與儲存電容電極1 9之第一段191共同界定出一 第一儲存電容（如圖2A所示，Cs!);每一像素區lu内之 共用電極17、下介電層182與儲存電容電極19之第二段 192共同界定出一第二儲存電容（如圖2B所示，Cs ); 2 每一像素區111内之儲存電容電極19之第一段191、上介 099123371 表單編號A0I01 第5頁/共34頁 0992041165-0 201205168 電層]8〗與像素電極〗6之第二區]62共同界定出一用以控 制液晶分子之傾角之補償電容（如圖2β所示，Ccp )。 [0008] [0009] 液晶本身由於無法自行發光，其顯示器之顯示機制則必 須仰賴背光（back Iight)模組之光源◊因此，被應用於 液晶顯示器中之薄膜電晶體陣列板之開口率（aperha rat10)則構成了影響液晶顯示器之顯示亮度之主要因素 。然而’該傳統之液晶顯示器用之薄膜電晶體陣列板！為 了降低該等共用電極17與儲存電容電極19之阻值而使用 該第一、二圖案化金屬層、m2)來定義出該等共用電 極17與健存電容電極19。因此，也犧牲掉該傳統之液晶 顯示器用之薄膜電晶體陣列板1之整禮開口率。 經前述說明可知，提升液晶顯示器用之薄膜電晶體陣列 板之開口率高糾低其轉域值，是職術領域者所 待克服之難題。 【發明内容】 [0010] 因此，本發明之目之即在提供一 電晶體陣列板。 種液晶顯示器用之薄膜 [0011] 099123371 於是，本發明液晶顯示器用之薄膜電晶體陣列板，包含 土板複數相互平仃之掃描線、複數與該等掃描線 相隔、相父叉且與該等掃描線共同將該基板界定出複數 像素區之貝料線、複數分卿成在該等像素區之第一薄 膜電晶體、魏分卿成在料像純並㈣與其對應 之第一薄膜電㈣電連接之像素電極、複數分別形成在 鱗像素區之透明之儲存電容電極、至少—絕緣地隔開 母一對儲存電容電極與像辛 09920411 表一第6頁象共t電頁極之介電層，及複數形成 201205168 在該介電層 層上之導電橋接線。 • [0012] [0013] [0014] Ο [0015] [0016] ❹ [0017] [0018] 099123371 ":存電奋電極是位於其對應之像素電極下方。 該介電層盥各— 個錯存電二。：存電容電極與像素電極共同界定- 且分別是：署：介電層形成有複數分別位於該等像素區 -與其導體之導孔。每-導體具有-上端及 〜儲存電容電極電連接之下端。 :料線:越位於兩相鄰像素區之間之掃描線與 上端 接位於兩相鄰Sr且每一導電橋接線之兩端分別橋 .. 像素區 <該介電層之該等導孔内之導體之 Χ之力效在於’提升液晶顯示器用之薄膜電晶體陣 歹i板之開口率馬並降低其電路之阻值。 【實施方式】 有關本發明之前述及其它技㈣容、雜與功效，在以 下配Π參考圖式之六僻較佳實施例謂細說明中，將可 清楚地呈現。 在本發明被詳細描述之前，要注f之是，在以下之說明 内容中，類似之元件是以相同之編號來表示。 參閱圖3及圖4，本發明之液晶顯示器用之薄膜電晶體陣 列板之一第一較佳實施例，是適用於四區域型 之液晶顯示器。本發明該第—較佳實施例，包含：一基 板2、複數相互平行之掃描線3、複數與該等掃描線3相隔 、相交叉且與該等掃描線3共同將該基板2界定出複數像 素區21之資料線4、複數分別形成在該等像素區21之第一 0992041165-0 表單編號A010I 第7頁/共34頁 201205168 [0019] [0020] [0021] [0022] [0023] 099123371 溥獏電晶體51、複數分別形成在該等像素區以之 極6、複數分別形成在該等像素區21之透明之 ^ 5 = '兩絕緣地隔開每—對锦存電容電極？與像素電極= ，、母1儲存電容電極7與像素電極6上下迭接之 ，及複數導電橋接線91。 曰 每—第一薄膜電晶體51包括一與其相對應之掃 接之閘極511、—盥其相庙— 線3電連 ”其相對應之:樣線4電連接 ，及—汲極513。 每—像素電糾與錢 極⑴電連接之第-區61。第4膜電日日體Η之及 母—儲存電容電極7是位於其對應之像素電極^ 一透明之健存電容電極7具有—平行於該等掃描線3之I 1及兩自該共用段71沿著平行於該等資料唆4/、 伸之連接段72，且哕 貝料線4反向延 用肋相串連。叫71與其相鄰之像素區21之共 在本發明該第—較佳實鮮透 極7是分別用以作為一此用^ °亥專透明之赌存電容電 π 、用線（common line)佶 ，該等介電層8與每一對儲 用，因此 界定-個儲存電容（st 與像素電極6共同 dSe capacitor ， cs)。 該下介電層8形成有複數分 填置有一導_之導孔。每—導體^象有素—區心分別是 與其對紅財刚物以減72之— =t8U及— 下職。在本發明該第—較佳實施例中，=連接之 別是由形成該等導電橋接_之材料所構成導體81分 第8頁/共34頁 0992041165-0 201205168 -闺每-導電橋接線9】是形成在該下介電層8上並 • 相鄰像素區21之間之掃浐㈣日一道 於兩 ]炙_插線3，且母—導電橋接線 鹌分别橋接位於兩相鄰像素區2】之該下介電層8之 孔内之導體81之上端811。 X等導 _]纟本發日㈣第-較佳實施财，該料明之儲存電 ^即’共用線）是由—第—圖案化透明導電層（似）所 ' '而成；該等掃描線3與該等第-薄膜電晶體5心極 511是由-第-圖案化金屬層（Μι)所界定而成；該等； 〇 、線4、第一薄膜電晶體51之源極512、没極5 i 3與 電橋接線91是由一第二圖案化金屬層（V所界定而^導 "亥等像素電極6是由—第二圖案化透明導電層（TCL )所 定而成。此處值得說明之是，本發明該第一較佳實2施:界 ，—方面是利用該第一圖案化透明導電層（TCL )所 之共用線取代傳統所使用之金屬之共用電極，i而提: 本發明該第-較佳實施例之開口率；另—方面利用每 —導電橋接線91來串聯該等共用線（即，讀等儲存電= Q 極7)，進而降低該等共用線之阻值。 谷 闕㈣圖5及圖6，本發明之液晶顯示㈣之薄膜電晶體陣 列板之一第二較佳實施例，大致上是相同於該第— 命 ^ —^較佳 貫施例，其不同處是在於，本發明該第二較佳實施例 包含複數㈣位於該料素㈣内且與其對應之錯= 容電極7之連接段72之末端電連接且上下迭接之金 =接且每—導舰之下端812與其對應之金屬導線92; 圃在本發明該第二較佳實施例中，該等掃 099123371 表單編號删i 第9頁/共34頁 逆等第一 0992041165-0 201205168 間極5U與該等金屬導_由該第-案金屬層（Μ】）所界定而成。本發明該第 例進一步地料金料線921㈣低該料用線貝 ，該等儲存電容電極7)之阻值。 、用、.泉(即 [0028] 參閱圖7及圖8，本發 列板之一第：較佳實…器用之薄膜電晶體陣 大致上是㈣於該第一較佳 實施例’其不同處是在於 適用於八區械刑〜. 第二&佳實施例是 、 α 〇main)之液晶顯示器，並更包含福| 刀別形成在該等像素區2 复數 分別形成在該等像素區2 ^賴電晶體52，及複數 方且與其對應之儲存^位於其對應之像素電極6下 容（卿嶋uQn eapa彻祕咐❹之補償電 [0029] [0030] 099123371Each storage capacitor electrode 19 is located below its corresponding pixel electrode 16 and above its corresponding common electrode 17, and the first segment 191 and the second segment 192 of each storage capacitor electrode 19 are respectively corresponding to the pixel electrode 16 The first zone 161 and the second zone 192 are electrically connected. In the thin film transistor array of the conventional liquid crystal display, the scan lines 12, the gates 141, 151 and the common electrode 17 are respectively formed on the substrate 11 and are formed of a first patterned metal. a layer (the upper dielectric layer 182 is formed on the first patterned metal layer), the data line 、3, the source mi, 151, the drain 143, 153 and the storage Capacitor electrodes 19 are respectively formed on the lower dielectric layer and are defined by a second patterned metal layer (^); the upper dielectric layer 181 is formed to form the second patterned metal layer (M) The pixel electrodes 16 are respectively formed on the upper dielectric layer 181 and are bounded by a patterned transparent conductive layer (TCL). Therefore, the common electrode 17, the lower dielectric layer 182 and the first segment 191 of the storage capacitor electrode 19 in each pixel region Hi together define a first storage capacitor (as shown in FIG. 2A, Cs!); The common electrode 17, the lower dielectric layer 182 and the second segment 192 of the storage capacitor electrode 19 in the pixel region lu together define a second storage capacitor (as shown in FIG. 2B, Cs); 2 in each pixel region 111 The first segment 191 of the storage capacitor electrode 19, the upper layer 099123371, the form number A0I01, the fifth page, the total 34 page 0992041165-0, the 201205168 layer 8 and the second electrode of the pixel electrode 6 are defined to control one. The compensation capacitance of the tilt angle of the liquid crystal molecules (shown in Figure 2β, Ccp). [0009] [0009] Since the liquid crystal itself cannot emit light by itself, the display mechanism of the display must rely on the backlight of the back Iight module. Therefore, the aperture ratio of the thin film transistor array plate used in the liquid crystal display (aperha) Rat10) constitutes a major factor affecting the display brightness of liquid crystal displays. However, the thin film transistor array board for the conventional liquid crystal display! In order to reduce the resistance of the common electrode 17 and the storage capacitor electrode 19, the first and second patterned metal layers, m2) are used to define the common electrode 17 and the storage capacitor electrode 19. Therefore, the etiquette aperture ratio of the thin film transistor array panel 1 for the conventional liquid crystal display is also sacrificed. According to the foregoing description, it is known that the aperture ratio of the thin film transistor array plate for liquid crystal display is high and the value of the transfer domain is lowered, which is a problem to be overcome by the professional field. SUMMARY OF THE INVENTION [0010] Accordingly, it is an object of the present invention to provide a transistor array panel. A film for a liquid crystal display [0011] 099123371 Thus, a thin film transistor array plate for a liquid crystal display according to the present invention comprises a scan line in which a plurality of earth plates are mutually flat, a plurality of scan lines are separated from the scan lines, a parent fork, and the like The scan lines collectively define the substrate as a bead line of a plurality of pixel regions, a plurality of first thin film transistors in the pixel regions, and Wei Zhiqing in a material image pure and (4) corresponding to the first thin film electricity (4) The pixel electrode electrically connected, the plurality of transparent storage capacitor electrodes respectively formed in the squamous pixel region, at least - the insulating pair of the pair of storage capacitor electrodes and the dielectric of the common page electrode of the same page The layers, and complex numbers form the 201205168 conductive bridge wiring on the dielectric layer. [0012] [0014] [0016] [0016] [0018] [0018] 099123371 ": The memory electrode is located below its corresponding pixel electrode. The dielectric layer is each faulty. The storage capacitor electrode and the pixel electrode are defined together - and respectively: the dielectric layer is formed with a plurality of conductive holes respectively located in the pixel regions - the conductors thereof. Each conductor has an upper end and a storage capacitor electrode electrically connected to the lower end. : Feed line: the scan line between the two adjacent pixel areas and the upper end are located at two adjacent Sr and the ends of each conductive bridge are respectively bridged. Pixel area < the conductive layer of the conductive layer The effect of the inner conductor is to improve the aperture ratio of the thin film transistor array for the liquid crystal display and reduce the resistance of the circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The foregoing and other aspects of the present invention, which are described in the accompanying drawings, which are incorporated herein by reference. Before the present invention is described in detail, in the following description, like elements are denoted by the same reference numerals. Referring to Figures 3 and 4, a first preferred embodiment of a thin film transistor array for a liquid crystal display according to the present invention is suitable for a four-region type liquid crystal display. The first preferred embodiment of the present invention comprises: a substrate 2; a plurality of scanning lines 3 parallel to each other; and a plurality of scanning lines 3 spaced apart from each other and intersecting with the scanning lines 3 to define the substrate 2 The data line 4 and the complex number of the pixel area 21 are respectively formed in the first 0992041165-0 of the pixel area 21. Form No. A010I Page 7 / Total 34 Page 201205168 [0020] [0022] [0023] [0023] 099123371 The germanium transistor 51 and the plurality of pixels are respectively formed at the poles of the pixel regions, and the plurality of transparent pixels formed in the pixel regions 21 are respectively separated by 5 5 ''insulatingly separated each of the pair of capacitor capacitor electrodes? And the pixel electrode = , the mother 1 storage capacitor electrode 7 and the pixel electrode 6 are vertically stacked, and the plurality of conductive bridge wires 91. Each of the first thin film transistors 51 includes a corresponding gate 511, which is connected to the temple, and has a corresponding connection: the sample line 4 is electrically connected, and the drain is 513. Each pixel is electrically corrected to the first region 61 electrically connected to the money pole (1). The fourth membrane electricity day and the mother-storage capacitor electrode 7 are located at the corresponding pixel electrode ^ a transparent storage capacitor electrode 7 has - I 1 and two parallel to the scanning lines 3 and the connecting sections 72 extending parallel to the data 唆4/, from the common section 71, and the mussel strands 4 are extended in series by ribs. 71 is in common with the pixel area 21 adjacent thereto. In the present invention, the first-perfect real-transparent pole 7 is respectively used as a gamma-capacitor capacitor π, a common line. The dielectric layer 8 is stored with each pair, thus defining a storage capacitor (st is common with the pixel electrode 6 dSe capacitor, cs). The lower dielectric layer 8 is formed with a plurality of sub-packages. Holes. Each conductor is well-characterized - the core of the zone is reduced by 72 to the red property, = t8U and - the lower position. In the present invention - the preferred implementation In the example, the connection is formed by the material forming the conductive bridge. The conductor 81 is divided into 8th page/total 34 pages 0992041165-0 201205168 - 闺 per-conductive bridge wire 9 is formed in the lower dielectric layer 8 and the broom (four) day between the adjacent pixel regions 21 is connected to the two] 炙_plug wires 3, and the mother-conductive bridge wires 桥 are respectively bridged to the lower dielectric layer 8 of the two adjacent pixel regions 2] The upper end 811 of the conductor 81 in the hole. The X-conducting _] 纟 发 ( 四 四 四 四 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳The scan line 3 and the first thin film transistor 5 core 511 are defined by a -first patterned metal layer (Μι); these; 〇, line 4, The source 512, the gate 5 i 3 and the bridge wire 91 of a thin film transistor 51 are defined by a second patterned metal layer (V is defined by "V" and the pixel electrode 6 is composed of - second patterning The transparent conductive layer (TCL) is defined. It is worth noting that the first preferred embodiment of the present invention utilizes the first patterned transparent conductive layer (TCL). The common line replaces the common electrode of the metal used conventionally, i: the aperture ratio of the first preferred embodiment of the present invention; and the other common use of the conductive bridge line 91 to connect the common lines (ie, , reading and other storage power = Q pole 7), thereby reducing the resistance of the common line. 阙 (4) Figure 5 and Figure 6, a liquid crystal display (4) of the present invention, a thin film transistor array plate, a second preferred embodiment Is substantially the same as the first embodiment of the present invention, the difference being that the second preferred embodiment of the present invention comprises a plurality (four) located in the element (4) and corresponding to the error = tolerance The ends of the connecting sections 72 of the electrodes 7 are electrically connected and vertically overlapped by gold = and each of the lower ends 812 of the guide ship and its corresponding metal wires 92; 圃 in the second preferred embodiment of the present invention, the sweeps 099123371 Form number deletion i Page 9 / total 34 pages reverse first 0992041165-0 201205168 The interpole 5U and the metal guide _ defined by the first metal layer (Μ). The first example of the present invention further increases the resistance of the gold wire 921 (four) to the wire of the material and the storage capacitor electrode 7). [0028] Referring to Figures 7 and 8, a thin film transistor array for one of the present inventions is substantially (four) different from the first preferred embodiment. It is applied to the eight-zone mechanical penalty ~. The second & preferred embodiment is a liquid crystal display of α 〇 main), and more includes a blessing | a knife is formed in the pixel area 2 and a plurality of pixels are respectively formed in the pixel areas 2 ^ Lai transistor 52, and the complex side and its corresponding storage ^ is located under its corresponding pixel electrode 6 (Qi嶋uQn eapa secret tips compensation [0029] [0030] 099123371
Pacitor，Cep)電極 93。 每—第二薄膜電晶體52包括一盘 抑之_则連接之第一^電晶 膜電晶體51之難⑴_之侧;:及 。每-像素電極6更具有—與其第一 _相::， 與1對癤$坌_兹_ 匕^相互間隔設置並 62。 —電晶體52之汲極523電連接之第二區 補償電容電極93是與其對應之像素電刻之第 電連接’且每—對對應之補償電 第二區62與該等介電層8 3像素電極6之 在本發明該第三較佳實二二 補償電容如)。 極⑽，共用線)==透明之儲存電容電 1荦化透明導•居r 償電容電極93是由該第 圖累化透明導电層（Τ')所界定而成 、统之薄膜電晶體陣列板1相較之下，本發明’與该傳 表單編號麵 ^ ίο 34 . 5亥第三較佳實 201205168 [0031] 施例之整體開口率較高。 參閱圖9、圖10及圖114 電晶體陳， ’本發明之液晶顯示器用之薄膜 室板之第四較佳實施例，大致上是相同於該 η ^例其不同處是在於’本發明該第四較佳 Μ之母—導電橋接線91跨越位於兩相鄰像素區21之 間之資料線4。 [0032] Ο [0033] Ο 二及雨t電容電極7具有—平行於該等資料線4之共用段 連接η/共㈣73沿著平行於該等雜線3方向延伸之 叫目I且該制段73輿其相鄰之像素區21之共用段 該第吨佳實施例中，該等導體81是設置在該 ^ 8 ’每-導體81之下端812是與其對應之儲存電 ^極7之連接段74之—末端電連接；每 是:成在該上介電組並跨越位於兩相鄰像:= 二每;:今電橋接線91之兩端分別橋接位於兩 鄰像素£21之社介電層8之導趙81之上端811;此外 ’该等像素電極6與該等導電橋接㈣是由該第二圖案化 透明導電層（TCL )所界定而成。 [0034] 參閱圖9、圖10及圖11Β，本發明之液晶顯示器用之薄膜 電晶體陣列板之-第五較佳實_，域上是彳目同於該 第四較佳實施例，其不同處是在於，本發明該第五較佳 實施例更包含複數分別位於該等像素區21内且與其對應 之儲存電容電極7之連接段74之末端電連接且上下迭接I 金屬導線922，每-導體S1之下端川與其對應之金屬導 099123371 表單編號Α0Ι0Ι 第11頁/共34頁 0992041165-0 201205168 [0035] [0036] [0037] [0038] [0039] [0040] 099123371 線922電連接。 在本發明該第五較佳實施例中，該等資料線4、第一薄膜 電晶體51之源極512、汲極513與該等金屬導線922是由 該第二圖案化金屬層（m2)所界定而成。 參閱圖1 2及圖1 3，本發明之液晶顯示器用之薄膜電晶體 陣列板之一第六較佳實施例，大致上是相同於該第三、 四較佳實施例，其不同處是在於，本發明該第六較佳實 施例之該等補償電容（Cep)電極93是形成在該下介電層8 上，且每一對對應之該補償電容電極93、像素電極6之第 二區62與該上介電層8共同界定出該補償電容（Cep)。 综上所述，本發明液晶顯示器用之薄膜電晶體陣列板， 開口率高且其薄膜電晶體陣列之電路之阻值低，故確實 能達成本發明之目之。 惟以上所述者，僅為本發明之較佳實施例與具體例而已 ，當不能以此限定本發明實施之範圍，即大凡依本發明 申請專利範圍及發明說明内容所作之簡單之等效變化與 修飾，皆仍屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一俯視示意圖，說明一種傳統之液晶顯示器用之薄 膜電晶體陣列板。 圖2 A是沿著該圖1之直線11 -11所取之局部剖視示意圖， 說明該傳統之薄膜電晶體陣列板之一第一儲存電容（Csi ) 之膜層結構。 圖2B是沿著該圖1之直線I I-Ι I所取之局部剖視示意圖， 表單編號A0101 第12頁/共34頁 0992041165-0 [0041] 201205168 [0042] [0043] [0044]D [0045] [0046] [0047]Ο [0048] [0049] [0050] 說明該傳統之薄膜電晶體陣列板之一第二儲存電容（Cs2) 與一補償電容（CcP{))之膜層結構。 圖3是一俯視示意圖，說明本發明液晶顯示器用之薄膜電 晶體陣列板之一第一較佳實施例。 圖4是沿著該圖3之直線IV-IV所取之局部剖視示意圖，說 明本發明該第一較佳實施例之一導電橋接線之橋接關係 與一儲存電容（Cs)之膜層結構。 圖5是一俯視示意圖，說明本發明液晶顯示器用之薄膜電 晶體陣列板之一第二較佳實施例。 圖6是沿著該圖5之直線VI-VI所取之局部剖視示意圖，說 明本發明該第二較佳實施例之導電橋接線之橋接關係與 儲存電容（Cs)之膜層結構。 圖7是一俯視示意圖，說明本發明液晶顯示器吊之薄膜電 晶體陣列板之一第三較佳實施例。 圖8是沿著該圖7之直線VI 11-VIII所取之局部剖視示意 圖，說明本發明該第三較佳實施例之一補償電容（Cep)之 膜層結構。 圖9是一俯視示意圖，說明本發明液晶顯示器用之薄膜電 晶體陣列板之一第四較佳實施例。 圖10是沿著該圖9之直線X-X所取之局部剖視示意圖，說 明本發明該第四較佳實施例兩相鄰像素區之儲存電容電 極之共用段之連接關係與儲存電容（Cs)之膜層結構。 圖11A是沿著該圖9之直線XI-XI所取之局部剖視示意圖 099123371 表單編號A0101 第13頁/共34頁 0992041165-0 201205168 ，說明本發明該第四較佳實施例之導電橋接線之橋接關 係與儲存電容（Cs)之膜層結構。 [0051] 第11 B圖是沿著該圖9之直線XI -XI所取之局部剖視示意 圖，說明本發明一第五較佳實施例之導電橋接線之橋接 關係與儲存電容（Cs)之膜層結構。 [0052] 圖12是一俯視示意圖，說明本發明液晶顯示器用之薄膜 電晶體陣列板之一第六較佳實施例。 [0053] 圖1 3是沿著該圖1 2之直線X111 -X111所取之局部剖視示 意圖，說明本發明該第六較佳實施例之補償電容（Cep)之 膜層結構。 【主要元件符號說明】 [0054] 基板：2 [0055] 像素區：21 [0056] 掃描線：3 [0057] 數據線：4 [0058] 第一薄膜電晶體：5 1 [0059] 閘極：511 [0060] 源極：512 [0061] 汲極：513 [0062] 第二薄膜電晶體：52 [0063] 閘極：521 099123371 表單編號A0101 第14頁/共34頁 0992041165-0 201205168 [0064]源極：522 [0065] 汲極：523 [0066] 像素電極：6 [0067] 第一區：61 [0068] 第二區：62 [0069] 儲存電容電極：7. [0070] 共用段：71 f) [0071] 連接段：72 [0072] 共用段：73 [0073] 連接段：74 [0074] 介電層：8 [0075] 導體：81 [0076] 上端：811 〇 [0077] 下端：812 [0078] 導電橋接線：91 [0079] 金屬導線：921 [0080] 金屬導線：922 [0081] 補償電容電極：93 [0082] 儲存電容：Cs 099123371 表單編號A0101 第15頁/共34頁 0992041165-0 201205168 [0083] 補償電容：Cep 099123371 表單編號A0101 第16頁/共34頁 0992041165-0Pacitor, Cep) Electrode 93. Each of the second thin film transistors 52 includes a disk and is connected to the side of the first (1)_ of the first transistor 11; Each of the pixel electrodes 6 has - with its first _ phase::, and 1 pair 疖$坌_ _ 匕 ^ are spaced apart from each other and 62. The second region of the transistor 52 is electrically connected to the second region of the compensation capacitor electrode 93, which is the first electrical connection of the pixel corresponding to the corresponding pixel, and the corresponding compensation second region 62 and the dielectric layer 8 3 The pixel electrode 6 is in the third preferred real two-second compensation capacitor of the present invention. Pole (10), common line) == Transparent storage capacitors 1 透明 透明 透明 居 居 偿 偿 偿 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 93 In contrast to the array board 1, the present invention has a higher overall aperture ratio than the transmission form number surface ίο 34. 5 hai third preferred embodiment 201205168 [0031]. Referring to FIG. 9, FIG. 10 and FIG. 114, the fourth preferred embodiment of the film chamber panel for a liquid crystal display of the present invention is substantially the same as the η^ example. The difference lies in the present invention. The fourth preferred mother-conductive bridge wire 91 spans the data line 4 between the two adjacent pixel regions 21. [0032] 003 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 003 003 003 003 003 003 The segment 73 is the common segment of the adjacent pixel region 21. In the preferred embodiment, the conductor 81 is disposed at the lower end 812 of the conductor 81 and is connected to the corresponding storage electrode 7 The end of the segment 74 is electrically connected; each is: in the upper dielectric group and across the two adjacent images: = two each;: the two ends of the current bridge connection 91 respectively bridge the two adjacent pixels £21 The upper end 811 of the conductive layer 8 is further defined by the second patterned transparent conductive layer (TCL). [0034] Referring to FIG. 9, FIG. 10 and FIG. 11A, the fifth preferred embodiment of the thin film transistor array panel for a liquid crystal display according to the present invention is similar to the fourth preferred embodiment. The difference is that the fifth preferred embodiment of the present invention further includes a plurality of terminals respectively located in the pixel regions 21 and electrically connected to the ends of the connection segments 74 of the corresponding storage capacitor electrodes 7 and vertically connected to the I metal wires 922. The lower end of each conductor S1 and its corresponding metal guide 099123371 Form No. Ι0Ι0Ι Page 11 / Total 34 Page 0992041165-0 201205168 [0036] [0037] [0040] [0040] 099123371 Line 922 electrical connection . In the fifth preferred embodiment of the present invention, the data lines 4, the source 512 of the first thin film transistor 51, the drain 513 and the metal wires 922 are formed by the second patterned metal layer (m2). Defined. Referring to FIG. 12 and FIG. 13, a sixth preferred embodiment of a thin film transistor array panel for a liquid crystal display according to the present invention is substantially the same as the third and fourth preferred embodiments, and the difference lies in The compensation capacitor (Cep) electrode 93 of the sixth preferred embodiment of the present invention is formed on the lower dielectric layer 8, and each pair corresponds to the compensation capacitor electrode 93 and the second region of the pixel electrode 6. The compensation capacitor (Cep) is defined by the upper dielectric layer 8 together with the upper dielectric layer 8. As described above, the thin film transistor array panel for a liquid crystal display of the present invention has a high aperture ratio and a low resistance of the circuit of the thin film transistor array, so that the object of the present invention can be achieved. The above is only the preferred embodiment and the specific examples of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent change according to the scope of the invention and the description of the invention. And modifications are still within the scope of the invention patent. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a top plan view showing a conventional thin film transistor array panel for a liquid crystal display. 2A is a partial cross-sectional view taken along line 11-11 of FIG. 1, illustrating a film structure of a first storage capacitor (Csi) of the conventional thin film transistor array panel. 2B is a partial cross-sectional view taken along line I I-Ι I of FIG. 1, Form No. A0101, Page 12/34, 0992041165-0 [0041] 201205168 [0042] [0044] [0047] [0049] [0050] [0050] A film structure of a second storage capacitor (Cs2) and a compensation capacitor (CcP{)) of the conventional thin film transistor array panel is illustrated. . Fig. 3 is a top plan view showing a first preferred embodiment of a thin film transistor array panel for a liquid crystal display of the present invention. 4 is a partial cross-sectional view taken along line IV-IV of FIG. 3, illustrating a bridge relationship of a conductive bridge connection and a film structure of a storage capacitor (Cs) according to the first preferred embodiment of the present invention. . Figure 5 is a top plan view showing a second preferred embodiment of a thin film transistor array panel for a liquid crystal display of the present invention. Figure 6 is a partial cross-sectional view taken along line VI-VI of Figure 5, illustrating the bridging relationship of the conductive bridge wiring and the film structure of the storage capacitor (Cs) of the second preferred embodiment of the present invention. Fig. 7 is a top plan view showing a third preferred embodiment of the thin film transistor array panel of the liquid crystal display panel of the present invention. Figure 8 is a partial cross-sectional view taken along line VI 11-VIII of Figure 7 illustrating the film structure of a compensation capacitor (Cep) of the third preferred embodiment of the present invention. Figure 9 is a top plan view showing a fourth preferred embodiment of a thin film transistor array panel for a liquid crystal display of the present invention. 10 is a partial cross-sectional view taken along line XX of FIG. 9 to illustrate the connection relationship and storage capacitance (Cs) of the shared sections of the storage capacitor electrodes of the two adjacent pixel regions in the fourth preferred embodiment of the present invention. The film structure. Figure 11A is a partial cross-sectional view taken along line XI-XI of Figure 9 099123371 Form No. A0101 Page 13 / Total 34 Page 0992041165-0 201205168, illustrating the conductive bridge wiring of the fourth preferred embodiment of the present invention The bridge structure and the film structure of the storage capacitor (Cs). 11B is a partial cross-sectional view taken along the line XI-XI of FIG. 9 to illustrate the bridging relationship of the conductive bridge connection and the storage capacitor (Cs) according to a fifth preferred embodiment of the present invention. Membrane structure. 12 is a top plan view showing a sixth preferred embodiment of a thin film transistor array panel for a liquid crystal display of the present invention. 13 is a partial cross-sectional view taken along the line X111-X111 of FIG. 12, illustrating the film structure of the compensation capacitor (Cep) of the sixth preferred embodiment of the present invention. [Main component symbol description] [0054] Substrate: 2 [0055] Pixel region: 21 [0056] Scanning line: 3 [0057] Data line: 4 [0058] First thin film transistor: 5 1 [0059] Gate: PMOS [0060] Source: 512 [0061] Pole: 513 [0062] Second thin film transistor: 52 [0063] Gate: 521 099123371 Form No. A0101 Page 14 of 34 0992041165-0 201205168 [0064] Source: 522 [0065] Pole: 523 [0066] Pixel electrode: 6 [0067] First region: 61 [0068] Second region: 62 [0069] Storage capacitor electrode: 7. [0070] Shared segment: 71 f) [0071] Connection section: 72 [0072] Common section: 73 [0073] Connection section: 74 [0074] Dielectric layer: 8 [0075] Conductor: 81 [0076] Upper end: 811 〇 [0077] Lower end: 812 [0078] Conductive Bridge Wiring: 91 [0079] Metal Wire: 921 [0080] Metal Wire: 922 [0081] Compensation Capacitor Electrode: 93 [0082] Storage Capacitor: Cs 099123371 Form No. A0101 Page 15 of 34 0992041165- 0 201205168 [0083] Compensation Capacitor: Cep 099123371 Form No. A0101 Page 16 of 34 0992041165-0