CN105589272A - 阵列基板的制作方法及制得的阵列基板 - Google Patents

阵列基板的制作方法及制得的阵列基板 Download PDF

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CN105589272A
CN105589272A CN201610116254.9A CN201610116254A CN105589272A CN 105589272 A CN105589272 A CN 105589272A CN 201610116254 A CN201610116254 A CN 201610116254A CN 105589272 A CN105589272 A CN 105589272A
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甘启明
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to PCT/CN2016/078876 priority patent/WO2017147973A1/zh
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Abstract

本发明提供一种阵列基板的制作方法及制得的阵列基板，通过先依次形成第一钝化层与平坦层，之后对平坦层进行图形化处理及退火处理，在对平坦层进行退火处理的过程中，由于平坦层与源漏极之间设有第一钝化层，不能够相接触，因此不会发生反应生成络合物，有利于提高阵列基板的电学性能，实现信号导通；与现有的阵列基板的制作方法相比，本发明还可以至少减少一道光罩，有利于提升工艺效果，缩短制程时间，降低生产成本。本发明制得的阵列基板，信号传导畅通，具有良好的电学性能。

Description

阵列基板的制作方法及制得的阵列基板
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板的制作方法及制得的阵列基板。
背景技术
随着显示技术的发展，液晶显示器(LiquidCrystalDisplay，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlightmodule)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜(CF，ColorFilter)基板、薄膜晶体管(TFT，ThinFilmTransistor)阵列基板、夹于彩膜基板与薄膜晶体管阵列基板之间的液晶(LC，LiquidCrystal)及密封胶框(Sealant)组成。
图1为现有的一种阵列基板的制作方法的示意图，该阵列基板的制作方法包括如下步骤：
步骤1、提供一衬底基板100，在所述衬底基板100上依次形成栅极(未图示)、栅极绝缘层200、有源层(未图示)、及源/漏极300；
步骤2、在所述源/漏极300及栅极绝缘层200上形成第一钝化层400，并对该第一钝化层400进行图形化处理，得到位于第一钝化层400上的第一过孔410；
步骤3、在所述第一钝化层400上形成平坦层500，并对该平坦层500进行图形化处理，得到位于第一过孔410中的第二过孔510；之后对平坦层500进行退火处理；
步骤4、在所述平坦层500上形成公共电极600；
步骤5、在所述公共电极600、平坦层500上形成第二钝化层700，并对该第二钝化层700进行图形化处理，得到位于第二过孔510内的第三过孔710；
步骤6、在所述第二钝化层700上形成像素电极800，所述像素电极800经由第三过孔710与源/漏极300相接触。
上述阵列基板的制作方法步骤3中，在对平坦层500进行退火处理时，位于第一过孔410中的平坦层500的光阻材料会与源/漏极300的金属材料发生反应，生成不导电的络合物550，从而阻隔所述像素电极800与源/漏极300的导通，导致数据(Data)信号无法传输至像素电极300，从而对阵列基板的性能造成致命性的影响。
发明内容
本发明的目的在于提供一种阵列基板的制作方法，有效阻隔平坦层与源/漏极的接触，防止在平坦层的退火工艺中产生不导电的络合物，有利于提高阵列基板的电学性能，实现信号导通；同时减少光罩数量，减少制程时间，降低生产成本。
本发明的目的还在于提供一种阵列基板，信号传导畅通，具有良好的电学性能。
为实现上述目的，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上依次形成栅极、栅极绝缘层、有源层、及源/漏极；
步骤2、在所述源/漏极及栅极绝缘层上形成第一钝化层，在所述第一钝化层上形成平坦层，对所述平坦层进行图形化处理，得到对应于源/漏极上方的第一通孔；
步骤3、在所述平坦层上沉积第一透明导电层，并对所述第一透明导电层进行图形化处理，形成公共电极；
步骤4、在所述公共电极、平坦层上形成第二钝化层，所述第二钝化层包覆第一通孔并与第一钝化层相接触；
对所述第二钝化层上位于第一通孔内的部分进行开孔处理，得到位于第二钝化层上的第二通孔，沿所述第二通孔继续对第一钝化层进行蚀刻，得到对应于第二通孔的第三通孔，从而所述第二通孔与第三通孔的尺寸小于所述第一通孔的尺寸；
步骤5、在所述第二钝化层上沉积第二透明导电层，并对所述第二透明导电层进行图形化处理，形成像素电极，所述像素电极经由第二通孔与第三通孔与源/漏极相接触。
所述第一钝化层与第二钝化层的材质和膜厚相同。
所述第一钝化层与第二钝化层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层与第二钝化层的膜厚为
所述第二通孔与第三通孔的尺寸小于所述第一通孔的尺寸。
所述第一通孔、第二通孔、及第三通孔均为圆形孔，所述第一通孔的直径为7-12μm，所述第二通孔与第三通孔的直径为3-5μm。
本发明还提供一种阵列基板，包括基板、设于所述基板上的栅极、设于所述栅极及基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层及栅极绝缘层上的源/漏极、设于所述源/漏极、有源层、及栅极绝缘层上的第一钝化层、设于所述第一钝化层上的平坦层、设于所述平坦层上的公共电极、设于所述公共电极、及平坦层上的第二钝化层、及设于所述第二钝化层上的像素电极；
所述平坦层上设有对应于源/漏极上方的第一通孔，所述第二钝化层上位于所述第一通孔底部的部分上设有第二通孔，所述第一钝化层上设有与所述第二通孔相贯通的第三通孔，所述像素电极经由第二通孔与第三通孔与源/漏极相接触。
所述第一钝化层与第二钝化层的材质和膜厚相同。
所述第一钝化层与第二钝化层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层与第二钝化层的膜厚为
所述第二通孔与第三通孔的尺寸小于所述第一通孔的尺寸。
所述第一通孔、第二通孔、及第三通孔均为圆形孔，所述第一通孔的直径为7-12μm，所述第二通孔与第三通孔的直径为3-5μm。
本发明的有益效果：本发明提供的一种阵列基板的制作方法，通过先依次形成第一钝化层与平坦层，之后对平坦层进行图形化处理及退火处理，在对平坦层进行退火处理的过程中，由于平坦层与源漏极之间设有第一钝化层，不能够相接触，因此不会发生反应生成络合物，有利于提高阵列基板的电学性能，实现信号导通；与现有的阵列基板的制作方法相比，本发明还可以至少减少一道光罩，有利于提升工艺效果，缩短制程时间，降低生产成本。本发明制得的阵列基板，信号传导畅通，具有良好的电学性能。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有的一种阵列基板的制作方法的示意图；
图2为本发明的阵列基板的制作方法的步骤1的示意图；
图3为本发明的阵列基板的制作方法的步骤2的示意图；
图4为本发明的阵列基板的制作方法的步骤3的示意图；
图5-6为本发明的阵列基板的制作方法的步骤4的示意图；
图7为本发明的阵列基板的制作方法的步骤5的示意图暨本发明制得的阵列基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2-7，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤1、如图2所示，提供一基板10，在所述基板10上依次形成栅极15、栅极绝缘层20、有源层25、及源/漏极30。
具体的，所述基板10为透明基板，优选为玻璃基板。
具体的，所述栅极15、及源/漏极30的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。所述源/漏极30的材料优选为铜。
具体的，所述栅极绝缘层20为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的，所述有源层25的材料为铟镓锌氧化物(IGZO，indiumgalliumzincoxide)。
步骤2、如图3所示，在所述源/漏极30及栅极绝缘层20上形成第一钝化层40，在所述第一钝化层40上形成平坦层50，采用一道光罩对所述平坦层50进行曝光、显影，以对所述平坦层50进行图形化处理，得到对应于源/漏极30上方的第一通孔51。
具体的，所述平坦层50的材料为正性光阻。
具体的，所述步骤2还包括：在所述平坦层50上形成第一通孔51后，对所述平坦层50进行退火(anneal)处理，使其加热固化。在对平坦层50进行退火处理时，由于平坦层50与源/漏极30之间设有第一钝化层40不能够相接触，因此不会发生反应生成络合物。
步骤3、如图4所示，在所述平坦层50上沉积第一透明导电层，并采用一道光刻制程对所述第一透明导电层进行图形化处理，形成公共电极60。
具体的，所述公共电极60的材料为透明导电金属氧化物，如氧化铟锡(ITO)等。
优选的，所述步骤3还包括：对所述公共电极60进行退火处理，使其中的透明导电金属氧化物加热固化结晶，从而改善公共电极60的膜质结构，降低方块电阻，使其结构更稳定，寿命更长。
步骤4、如图5所示，在所述公共电极60、平坦层50上形成第二钝化层70，所述第二钝化层70包覆第一通孔51并与第一钝化层40相接触；
如图6所示，采用一道光刻制程对所述第二钝化层70上位于第一通孔51底部的部分进行开孔处理，得到位于第二钝化层70上的第二通孔71，沿所述第二通孔71继续对第一钝化层40进行蚀刻，得到对应于第二通孔71的第三通孔41。
具体的，所述第一钝化层40与第二钝化层70的材质和膜厚相同，这样可以减少不同材质在干蚀刻过程中带来的底切问题(undercutissue)。
具体的，所述第一钝化层40与第二钝化层70为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
优选的，所述第一钝化层40与第二钝化层70的膜厚为
具体的，所述第二通孔71与第三通孔41的尺寸小于所述第一通孔51的尺寸。
优选的，所述第一通孔51、第二通孔71、及第三通孔41均为圆形孔，所述第一通孔51的直径为7-12μm，所述第二通孔71与第三通孔41的直径为3-5μm。
具体的，所述步骤4中，所述第二钝化层70的光刻制程中的蚀刻制程与所述第一钝化层40的蚀刻制程均为干蚀刻制程。所述步骤4采用一道光罩来实现所述第一钝化层40与第二钝化层70的开孔处理，与现有技术相比，可节约一道光罩，节约生产成本，降低制程时间。
步骤5、如图7所示，在所述第二钝化层70上沉积第二透明导电层，并采用一道光刻制程对所述第二透明导电层进行图形化处理，形成像素电极80，所述像素电极80经由第二通孔71与第三通孔41与源/漏极30相接触。
具体的，所述像素电极80的材料为透明导电金属氧化物，如氧化铟锡(ITO)等。
优选的，所述步骤5还包括：对所述像素电极80进行退火处理，使其中的透明导电金属氧化物加热固化结晶，从而改善像素电极80的膜质结构，降低方块电阻，使其结构更稳定，寿命更长。
请参阅图7，本发明还提供一种阵列基板，包括基板10、设于所述基板10上的栅极15、设于所述栅极15及基板10上的栅极绝缘层20、设于所述栅极绝缘层20上的有源层25、设于所述有源层25及栅极绝缘层20上的源/漏极30、设于所述源/漏极30、有源层25、及栅极绝缘层20上的第一钝化层40、设于所述第一钝化层40上的平坦层50、设于所述平坦层50上的公共电极60、设于所述公共电极60、及平坦层50上的第二钝化层70、及设于所述第二钝化层70上的像素电极80。
所述平坦层50上设有对应于源/漏极30上方的第一通孔51，所述第二钝化层70上位于所述第一通孔51底部的部分上设有第二通孔71，所述第一钝化层40上设有与所述第二通孔71相贯通的第三通孔41，所述像素电极80经由第二通孔71与第三通孔41与源/漏极30相接触。
具体的，所述基板10为透明基板，优选为玻璃基板。
具体的，所述栅极15、及源/漏极30的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。所述源/漏极30的材料优选为铜。
具体的，所述栅极绝缘层20为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的，所述有源层25的材料为铟镓锌氧化物(IGZO，indiumgalliumzincoxide)。
具体的，所述平坦层50的材料为正性光阻。
具体的，所述公共电极60、及像素电极80的材料为透明导电金属氧化物，如氧化铟锡(ITO)等。
优选的，所述第一钝化层40与第二钝化层70的材质和膜厚相同。
具体的，所述第一钝化层40与第二钝化层70为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
优选的，所述第一钝化层40与第二钝化层70的膜厚为
具体的，所述第二通孔71与第三通孔41的尺寸小于所述第一通孔51的尺寸。
优选的，所述第一通孔51、第二通孔71、及第三通孔41均为圆形孔，所述第一通孔51的直径为7-12μm，所述第二通孔71与第三通孔41的直径为3-5μm。
综上所述，本发明提供的一种阵列基板的制作方法，通过先依次形成第一钝化层与平坦层，之后对平坦层进行图形化处理及退火处理，在对平坦层进行退火处理的过程中，由于平坦层与源漏极之间设有第一钝化层，不能够相接触，因此不会发生反应生成络合物，有利于提高阵列基板的电学性能，实现信号导通；与现有的阵列基板的制作方法相比，本发明还可以至少减少一道光罩，有利于提升工艺效果，缩短制程时间，降低生产成本。本发明制得的阵列基板，信号传导畅通，具有良好的电学性能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

1.一种阵列基板的制作方法，其特征在于，包括如下步骤：
步骤1、提供一基板(10)，在所述基板(10)上依次形成栅极(15)、栅极绝缘层(20)、有源层(25)、及源/漏极(30)；
步骤2、在所述源/漏极(30)及栅极绝缘层(20)上形成第一钝化层(40)，在所述第一钝化层(40)上形成平坦层(50)，对所述平坦层(50)进行图形化处理，得到对应于源/漏极(30)上方的第一通孔(51)；
步骤3、在所述平坦层(50)上沉积第一透明导电层，并对所述第一透明导电层进行图形化处理，形成公共电极(60)；
步骤4、在所述公共电极(60)、平坦层(50)上形成第二钝化层(70)，所述第二钝化层(70)包覆第一通孔(51)并与第一钝化层(40)相接触；
对所述第二钝化层(70)上位于第一通孔(51)底部的部分进行开孔处理，得到位于第二钝化层(70)上的第二通孔(71)，沿所述第二通孔(71)继续对第一钝化层(40)进行蚀刻，得到对应于第二通孔(71)的第三通孔(41)；
步骤5、在所述第二钝化层(70)上沉积第二透明导电层，并对所述第二透明导电层进行图形化处理，形成像素电极(80)，所述像素电极(80)经由第二通孔(71)与第三通孔(41)与源/漏极(30)相接触。
2.如权利要求1所述的阵列基板的制作方法，其特征在于，所述第一钝化层(40)与第二钝化层(70)的材质和膜厚相同。
3.如权利要求2所述的阵列基板的制作方法，其特征在于，所述第一钝化层(40)与第二钝化层(70)为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层(40)与第二钝化层(70)的膜厚为
4.如权利要求1所述的阵列基板的制作方法，其特征在于，所述第二通孔(71)与第三通孔(41)的尺寸小于所述第一通孔(51)的尺寸。
5.如权利要求4所述的阵列基板的制作方法，其特征在于，所述第一通孔(51)、第二通孔(71)、及第三通孔(41)均为圆形孔，所述第一通孔(51)的直径为7-12μm，所述第二通孔(71)与第三通孔(41)的直径为3-5μm。
6.一种阵列基板，其特征在于，包括基板(10)、设于所述基板(10)上的栅极(15)、设于所述栅极(15)及基板(10)上的栅极绝缘层(20)、设于所述栅极绝缘层(20)上的有源层(25)、设于所述有源层(25)及栅极绝缘层(20)上的源/漏极(30)、设于所述源/漏极(30)、有源层(25)、及栅极绝缘层(20)上的第一钝化层(40)、设于所述第一钝化层(40)上的平坦层(50)、设于所述平坦层(50)上的公共电极(60)、设于所述公共电极(60)、及平坦层(50)上的第二钝化层(70)、及设于所述第二钝化层(70)上的像素电极(80)；
所述平坦层(50)上设有对应于源/漏极(30)上方的第一通孔(51)，所述第二钝化层(70)上位于所述第一通孔(51)底部的部分上设有第二通孔(71)，所述第一钝化层(40)上设有与所述第二通孔(71)相贯通的第三通孔(41)，所述像素电极(80)经由第二通孔(71)与第三通孔(41)与源/漏极(30)相接触。
7.如权利要求6所述的阵列基板，其特征在于，所述第一钝化层(40)与第二钝化层(70)的材质和膜厚相同。
8.如权利要求7所述的阵列基板，其特征在于，所述第一钝化层(40)与第二钝化层(70)为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层(40)与第二钝化层(70)的膜厚为
9.如权利要求7所述的阵列基板，其特征在于，所述第二通孔(71)与第三通孔(41)的尺寸小于所述第一通孔(51)的尺寸。
10.如权利要求9所述的阵列基板，其特征在于，所述第一通孔(51)、第二通孔(71)、及第三通孔(41)均为圆形孔，所述第一通孔(51)的直径为7-12μm，所述第二通孔(71)与第三通孔(41)的直径为3-5μm。
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