WO2017049676A1 - 阵列基板及其制备方法 - Google Patents

阵列基板及其制备方法 Download PDF

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Publication number
WO2017049676A1
WO2017049676A1 PCT/CN2015/091807 CN2015091807W WO2017049676A1 WO 2017049676 A1 WO2017049676 A1 WO 2017049676A1 CN 2015091807 W CN2015091807 W CN 2015091807W WO 2017049676 A1 WO2017049676 A1 WO 2017049676A1
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layer
gate
drain
region
array substrate
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PCT/CN2015/091807
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English (en)
French (fr)
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贺超
唐国强
郭远
李娟�
陈玉霞
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Priority to US14/787,773 priority Critical patent/US9728403B2/en
Publication of WO2017049676A1 publication Critical patent/WO2017049676A1/zh

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    • H—ELECTRICITY
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a method for fabricating the same.
  • CTR cathode ray tube
  • Thin Film Transistor is currently used in Liquid Crystal Display (LCD) and Active Matrix/Organic Light-Emitting Diode (AMOLED).
  • the main drive components are directly related to the development direction of high-performance flat panel display devices.
  • the thin film transistor has a plurality of structures, and the material of the active layer of the thin film transistor for preparing the corresponding structure is also various. Among them, Low Temperature Poly-silicon (LTPS) material is one of the preferred ones, due to the low temperature polysilicon.
  • LTPS Low Temperature Poly-silicon
  • the atomic arrangement is arranged, and the carrier mobility is high.
  • a thin film transistor can be used to realize deflection driving of liquid crystal molecules. , which greatly reduces the volume occupied by the thin film transistor, increases the light transmission area, and obtains higher brightness and resolution; for the current-driven active matrix driven organic electroluminescent display device, low temperature polysilicon Thin film transistors can better meet the drive current requirements.
  • LTPS TFT-based display panels are favored by consumers because of their superior high image quality, high resolution, ultra-thin and low power consumption.
  • LTPS technology is gradually replacing traditional amorphous silicon (a-Si) TFTs.
  • a-Si amorphous silicon
  • Technology has become the mainstream of next-generation display technology.
  • the existing LTPS array substrate manufacturing process is complicated, and the production and manufacturing cost is high.
  • a conventional complementary metal oxide semiconductor (CMOS) LTPS TFT array substrate includes a substrate 110, a light shielding layer 120 disposed on the substrate 110, and a substrate 110 and a light shielding layer.
  • a buffer layer 130 on the layer 120 an active layer 140 disposed on the buffer layer 130, a gate insulating layer 150 disposed on the buffer layer 140, and a gate disposed on the gate insulating layer 150
  • An interlayer insulating layer 170 disposed on the gate 160, a source/drain 180 disposed on the interlayer insulating layer 170, and a source a planarization layer 190 on the drain 180, a common electrode layer 200 disposed on the planarization layer 190, an insulating layer 210 disposed on the common electrode layer 200, and a pixel electrode 220 disposed on the associated insulating layer 210;
  • the common electrode layer 200 is a full-surface type electrode; therefore, the fabrication process of the conventional CMOS type LTPS TFT array substrate requires an interlayer insulation after the gate 160 is formed.
  • the layer 170 serves as an insulating layer between the gate 160 and the source/drain 180, which is complicated in fabrication process and high in production cost.
  • An object of the present invention is to provide a method for fabricating an array substrate in which a gate electrode and a source drain are formed in the same metal layer, and a conventional full-surface type common electrode layer is divided into two parts, one of which serves as a common electrode. The other part is used to realize the gate scan signal input, thereby reducing the process of an interlayer insulating layer and saving the manufacturing cost of the process.
  • Another object of the present invention is to provide an array substrate in which the gate and the source and drain are located in the same metal layer, and there is no interlayer insulating layer between the gate and the source and drain, and the structure is simplified, thereby reducing the manufacturing cost of the process.
  • the present invention provides a method for preparing an array substrate, comprising the following steps:
  • Step 1 Providing a substrate, sequentially forming a light shielding layer and a buffer layer on the substrate, forming a polysilicon layer on the buffer layer, and performing N-type ion implantation on both ends of the polysilicon layer to obtain the polysilicon layer.
  • An N-type heavily doped region at both ends, and an undoped region between the two N-type heavily doped regions, a gate insulating layer is deposited on the polysilicon layer;
  • Step 2 coating a photoresist on the gate insulating layer, exposing and developing the photoresist by using a half gray scale mask to obtain a photoresist layer, wherein the photoresist layer corresponds to the N-type weight a through hole is disposed above the doped region, and a thickness on the photoresist layer corresponding to the undoped region is greater than a thickness of the other region;
  • Step 3 using a photoresist layer as a shielding layer, performing dry etching on the gate insulating layer to obtain a first via hole located above the N-type heavily doped region, and performing oxygen on the photoresist layer After the ashing treatment, after the oxygen ashing treatment, the remaining photoresist layer is located above the undoped region of the polysilicon layer, and the size is smaller than the size of the undoped region;
  • Step 4 using the remaining photoresist layer as a shielding layer, performing N-type ion implantation on both ends of the undoped region, forming an N-type lightly doped region at both ends of the undoped region, and defining two N
  • the undoped region between the lightly doped regions is a channel region; the photoresist layer is removed, a metal layer is deposited on the gate insulating layer, and the metal layer is patterned to obtain a gate, a source, and a drain. a gate, a source, and a drain are not connected, and the source and the drain respectively pass through the first via and the N-type heavily doped region Connected
  • Step 5 forming a flat layer on the gate, the source, and the drain, forming a second via corresponding to the gate on the flat layer by a photolithography process, and corresponding to the drain a third via at the top of the pole;
  • Step 6 Form an ITO film on the flat layer, pattern the ITO film to obtain a common electrode, and a transparent electrode.
  • the transparent electrode is connected to the gate through a second via hole, thereby scanning a gate signal. It can be input to the gate through the transparent electrode.
  • the half-gray reticle includes a light-transmitting region, a semi-transmissive region, and a light-shielding region, and the light-transmitting region corresponds to the upper portion of the N-type heavily doped region during exposure.
  • the light shielding region corresponds to the upper portion of the undoped region.
  • the method before depositing the metal layer, the method further comprises performing a rapid thermal annealing treatment on the substrate.
  • the buffer layer is a stacked structure composed of a silicon nitride film and a silicon oxide film; the material of the polysilicon layer is low temperature polysilicon.
  • the method further includes the step of forming an insulating layer on the common electrode and the transparent electrode, forming a pixel electrode on the insulating layer, wherein the pixel electrode is connected to the drain through a third via hole on the flat layer.
  • the present invention also provides an array substrate, comprising: a substrate, a light shielding layer disposed on the substrate, a buffer layer disposed on the substrate and the light shielding layer, and a polysilicon layer disposed on the buffer layer; a gate insulating layer on the polysilicon layer, a gate, a source, and a drain provided on the gate insulating layer, and a flatness disposed on the gate insulating layer, the gate, the source, and the drain a layer, and a common electrode and a transparent electrode disposed on the flat layer;
  • the polysilicon layer includes a channel region in the middle and an N-type heavily doped region at both ends;
  • the gate insulating layer is provided with a first via corresponding to the upper portion of the N-type heavily doped region, and the planar layer is provided with a second via corresponding to the upper portion of the gate, and corresponding to the A third via above the drain, the transparent electrode is connected to the gate through a second via, so that a gate scan signal can be input to the gate through the transparent electrode.
  • the polysilicon layer further includes an N-type lightly doped region between the channel region and the N-type heavily doped region; the source and the drain pass through the first via and the N-type heavily doped region, respectively Connected.
  • the gate, the source, and the drain are formed by a photolithography process through a same metal layer, and the common electrode and the transparent electrode are formed by a photolithography process through the same ITO film.
  • the buffer layer is a stacked structure composed of a silicon nitride film and a silicon oxide film; the material of the polysilicon layer is low temperature polysilicon.
  • the array substrate further includes an insulating layer disposed on the common electrode and the transparent electrode, and a pixel electrode on the insulating layer, the pixel electrode being connected to the drain through a third via on the planar layer.
  • the present invention also provides an array substrate, comprising: a substrate, a light shielding layer disposed on the substrate, a buffer layer disposed on the substrate and the light shielding layer, and a polysilicon layer disposed on the buffer layer; a gate insulating layer on the polysilicon layer, a gate, a source, and a drain provided on the gate insulating layer, and a flatness disposed on the gate insulating layer, the gate, the source, and the drain a layer, and a common electrode and a transparent electrode disposed on the flat layer;
  • the polysilicon layer includes an N-type heavily doped region at both ends of the polysilicon layer and a channel region between the two N-type heavily doped regions;
  • the gate insulating layer is provided with a first via corresponding to the upper portion of the N-type heavily doped region, and the planar layer is provided with a second via corresponding to the upper portion of the gate, and corresponding to the a third via above the drain, the transparent electrode is connected to the gate through a second via, so that a gate scan signal can be input to the gate through the transparent electrode;
  • the polysilicon layer further includes an N-type lightly doped region between the channel region and the N-type heavily doped region; the source and the drain are respectively doped with the N-type through the first via hole Miscellaneous areas are connected;
  • the gate, the source, and the drain are formed by a photolithography process through a same metal layer, and the common electrode and the transparent electrode are obtained through a photolithography process through the same ITO film;
  • the array substrate further includes an insulating layer disposed on the common electrode and the transparent electrode, and a pixel electrode disposed on the insulating layer, wherein the pixel electrode passes through the third via and the drain on the planar layer Connected.
  • the present invention provides an array substrate and a preparation method thereof, and a method for fabricating the array substrate of the present invention, wherein the gate electrode and the source and drain electrodes are formed in the same metal layer, and the conventional full-surface type is common
  • the electrode layer is divided into two parts, one part is used as a common electrode, and the other part is used for implementing gate scan signal input, thereby reducing an interlayer insulating layer process and saving process manufacturing cost;
  • the array substrate, gate and source drain of the present invention The electrode is located in the same metal layer, and there is no interlayer insulating layer between the gate and the source and the drain, and the structure is simplified, thereby reducing the manufacturing cost of the array substrate.
  • FIG. 1 is a schematic structural view of a conventional CMOS type low temperature polysilicon thin film transistor array substrate
  • FIG. 2 is a top plan view of the CMOS type low temperature polysilicon thin film transistor array substrate of FIG. 1;
  • FIG. 3 is a schematic view showing the first step of the method for preparing an array substrate of the present invention
  • FIG. 4 is a schematic view showing a step 2 of a method for preparing an array substrate of the present invention
  • step 3 is a schematic view of step 3 of the method for preparing an array substrate of the present invention.
  • FIG. 6 is a schematic view showing a step 4 of a method for preparing an array substrate of the present invention.
  • FIG. 7 is a schematic plan view showing the step 4 of the method for fabricating the array substrate of the present invention.
  • FIG. 8 is a schematic view showing the step 5 of the method for preparing an array substrate of the present invention.
  • FIG. 9 is a schematic view showing the step 6 of the method for preparing an array substrate of the present invention.
  • FIG. 10 is a top plan view showing the step 6 of the method for fabricating the array substrate of the present invention.
  • the present invention provides a method for preparing an array substrate, comprising the following steps:
  • Step 1 as shown in FIG. 3, a substrate 11 is provided, a light shielding layer 12 and a buffer layer 13 are sequentially formed on the substrate 11, and a polysilicon layer 14 is formed on the buffer layer 13, and two layers of the polysilicon layer 14 are formed.
  • N-type ion implantation is performed at the end to obtain an N-type heavily doped region 141 located at both ends of the polysilicon layer 14, and an undoped region 145 between the two N-type heavily doped regions 141 on the polysilicon layer 14.
  • a gate insulating layer 15 is deposited.
  • the buffer layer 12 is a laminated structure composed of a silicon nitride film and a silicon oxide film.
  • the material of the polysilicon layer 14 is low temperature polysilicon.
  • Step 2 As shown in FIG. 4, a photoresist is coated on the gate insulating layer 15, and the photoresist is exposed and developed by using a half gray-scale mask to obtain a photoresist layer 50.
  • a via hole 51 is disposed on the layer 50 corresponding to the N-type heavily doped region 141, and a thickness above the undoped region 145 on the photoresist layer 50 is greater than a thickness of other regions.
  • the half gray scale mask includes a light transmitting region, a semi-light transmitting region, and a light shielding region, and the light transmitting region corresponds to the upper portion of the N-type heavily doped region 141 during exposure, and is used for A via hole is formed on the gate insulating layer 15 above the N-type heavily doped region 142, and the light shielding region corresponds to the upper portion of the undoped region 145.
  • Step 3 as shown in FIG. 5, the gate insulating layer 15 is dry etched by using the photoresist layer 50 as a shielding layer, thereby obtaining a first via hole located above the N-type heavily doped region 141. 151, the photoresist layer 50 is subjected to an oxygen ashing treatment, and after the oxygen ashing treatment, the remaining photoresist layer 50 is located above the undoped region 145 of the polysilicon layer 14, and the size is smaller than the undoped layer. The size of zone 145.
  • Step 4 as shown in FIG. 6, with the remaining photoresist layer 50 as a shielding layer, N-type ion implantation is performed on both ends of the undoped region 145, and N is formed at both ends of the undoped region 145.
  • the lightly doped region 142 defines an undoped region between the two N-type lightly doped regions 142 as a channel region 143; the photoresist layer 50 is removed, and the gate insulating layer 15 is deposited by physical vapor deposition Forming a metal layer, patterning the metal layer to obtain a gate electrode 16, a source electrode 17, and a drain electrode 18.
  • the gate electrode 16, the source electrode 17, and the drain electrode 18 are not connected, and the source electrode 17 and the drain electrode are connected.
  • 18 is connected to the N-type heavily doped region 141 through the first via 151; at this time, the top view of the substrate is as shown in FIG.
  • the substrate 11 is subjected to rapid thermal annealing (RTA) treatment to hydrogen and activate the polysilicon layer 14.
  • RTA rapid thermal annealing
  • Step 5 as shown in FIG. 8, a flat layer 19 is formed on the gate 16, the source 17, and the drain 18, and is formed on the flat layer 19 by a photolithography process corresponding to the gate 16 a second via 191 and a third via 192 above the drain 18.
  • Step 6 as shown in FIG. 9, an ITO film is formed on the flat layer 19, and the ITO film is patterned to obtain a common electrode 201 and a transparent electrode 202.
  • the transparent electrode 202 passes through the second via 191.
  • the gate electrodes 16 are connected, so that the gate scan signal can be input to the gate electrode 16 through the transparent electrode 202, so that the source 17 and the drain electrode 18 are turned on; at this time, the top view of the substrate is as shown in FIG.
  • the transparent electrode 202 is connected to the gate 16 of the row through the second via 191 in the same row, thereby inputting the gate scanning signal line, and forming between the source 17 and the drain 18. Vertical circuit.
  • the method for fabricating the array substrate further includes: forming an insulating layer on the common electrode 201 and the transparent electrode 202, forming a pixel electrode on the insulating layer, and the pixel electrode passes through the flat layer
  • the third via 192 on 19 is connected to the drain 18.
  • the present invention further provides an array substrate, comprising a substrate 11, a light shielding layer 12 disposed on the substrate 11, a buffer layer 13 disposed on the substrate 11 and the light shielding layer 12, and a polysilicon layer 14 on the buffer layer 13 , a gate insulating layer 15 disposed on the polysilicon layer 14 , a gate 16 , a source 17 , and a drain 18 disposed on the gate insulating layer 15 , a flat layer 19 disposed on the gate insulating layer 15, the gate 16, the source 17, and the drain 18, and a common electrode 201 and a transparent electrode 202 disposed on the flat layer 19;
  • the polysilicon layer 14 includes a channel region 143 in the middle, an N-type heavily doped region 141 at both ends, and an N-type lightly doped region 142 between the channel region 143 and the N-type heavily doped region 141;
  • the gate insulating layer 15 is provided with a first via 151 corresponding to the upper portion of the N-type heavily doped region 141, and the flat layer 19 is provided with a second via corresponding to the upper portion of the gate 16. 191, and corresponding to the third via 192 above the drain 18, the transparent electrode 202 passes through the second via 191 is connected to the gate 16 so that a gate scan signal can be input to the gate 16 through the transparent electrode 202 such that the source 17 and the drain 18 are turned on.
  • the source 17 and the drain 18 are respectively connected to the N-type heavily doped region 141 through the first via 151.
  • the array substrate further includes an insulating layer disposed on the common electrode 201 and the transparent electrode 202, and a pixel electrode disposed on the insulating layer, the pixel electrode passing through the third layer on the flat layer 19.
  • the aperture 192 is coupled to the drain 18.
  • the gate electrode 16, the source electrode 17, and the drain electrode 18 are formed by a photolithography process through the same metal layer, and the common electrode 201 and the transparent electrode 202 are formed by photolithography through the same ITO film;
  • the array substrate of the present invention is a CMOS type low temperature polysilicon thin film transistor array substrate; the array substrate of the present invention can be used for an IPS (In-Plane Switching) type liquid crystal display device, or FFS (Fringe Field Switching) ) type liquid crystal display device.
  • IPS In-Plane Switching
  • FFS Ringe Field Switching
  • the buffer layer 12 is a laminated structure composed of a silicon nitride film and a silicon oxide film.
  • the material of the polysilicon layer 14 is low temperature polysilicon.
  • the present invention provides an array substrate and a preparation method thereof.
  • the method for fabricating the array substrate of the present invention has the gate and the source and drain electrodes formed in the same metal layer, and the conventional full-surface type common electrode The layer is divided into two parts, one part is used as a common electrode, and the other part is used for implementing gate scan signal input, thereby reducing an interlayer insulating layer process and saving process manufacturing cost; the array substrate, gate and source drain of the present invention In the same metal layer, there is no interlayer insulating layer between the gate and the source and drain, and the structure is simplified, thereby reducing the manufacturing cost of the array substrate.

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Abstract

一种阵列基板及其制备方法，将栅极（16）与源漏极（17，18）制作在同一金属层内，并将传统的整面型的公共电极层分割为两部分，其中一部分用作公共电极（201），另一部分用于实现栅极扫描信号输入，从而减少一道层间绝缘层制程，节省工艺制作成本；该阵列基板的栅极与源漏极位于同一金属层内，栅极与源漏极之间不存在层间绝缘层，结构简化，从而降低了阵列基板的工艺制作成本。

Description

阵列基板及其制备方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法。
背景技术
在显示技术领域，平板显示技术已经逐步取代阴极射线管(Cathode Ray Tube，简称CRT)显示器。平板显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
薄膜晶体管(Thin Film Transistor，简称TFT)是目前液晶显示装置(Liquid Crystal Display，简称LCD)和有源矩阵驱动式有机电致发光显示装置(Active Matrix/Organic Light-Emitting Diode，简称AMOLED)中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管有源层的材料也具有多种，其中，低温多晶硅(Low Temperature Poly-silicon，简称LTPS)材料是其中较为优选的一种，由于低温多晶硅的原子规则排列，载流子迁移率高，对电压驱动式的液晶显示装置而言，低温多晶硅薄膜晶体管由于其具有较高的迁移率，可以使用体积较小的薄膜晶体管实现对液晶分子的偏转驱动，在很大程度上缩小了薄膜晶体管所占的体积，增加透光面积，得到更高的亮度和解析度；对于电流驱动式的有源矩阵驱动式有机电致发光显示装置而言，低温多晶硅薄膜晶体管可以更好的满足驱动电流要求。
因此，基于LTPS TFT的显示面板以其优越的高画质、高分辨率、超轻薄及低功耗等性能备受广大消费者喜爱，LTPS技术正在逐渐取代传统非晶硅(a-Si)TFT技术，成为新一代显示技术主流。但是现有的LTPS阵列基板制作制程复杂，生产制作成本高。
如图1所示，传统的互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)LTPS TFT阵列基板，包括基板110、设于所述基板110上的遮光层120、设于所述基板110及遮光层120上的缓冲层130、设于所述缓冲层130上的有源层140、设于所述缓冲层140上的栅极绝缘层150、设于所述栅极绝缘层150上的栅极160、设于所述栅极160上的层间绝缘层170、设于所述层间绝缘层170上的源/漏极180、设于所述源 /漏极180上的成平坦层190、设于平坦层190上的公共电极层200、设于公共电极层200上的绝缘层210、以及设于所属绝缘层210上的像素电极220；图2为图1的CMOS型LTPS阵列基板的俯视图，其中，公共电极层200为整面型电极；因此，传统的CMOS型LTPS TFT阵列基板的制作工艺，在栅极160形成后需要制作一层间绝缘层170用作栅极160与源/漏极180之间的绝缘层，制作制程复杂，生产成本高。
发明内容
本发明的目的在于提供一种阵列基板的制备方法，将栅极与源漏极制作在同一金属层内，并将传统的整面型的公共电极层分割为两部分，其中一部分用作公共电极，另一部分用于实现栅极扫描信号输入，从而减少一道层间绝缘层制程，节省工艺制作成本。
本发明的目的还在于提供一种阵列基板，栅极与源漏极位于同一金属层内，栅极与源漏极之间不存在层间绝缘层，结构简化，从而降低了工艺制作成本。
为实现上述目的，本发明提供一种阵列基板的制备方法，包括如下步骤：
步骤1、提供一基板，在所述基板上依次形成遮光层、缓冲层，在所述缓冲层上形成多晶硅层，对所述多晶硅层的两端进行N型离子注入，得到位于所述多晶硅层两端的N型重掺杂区、及位于两N型重掺杂区之间的未掺杂区，在所述多晶硅层上沉积栅极绝缘层；
步骤2、在所述栅极绝缘层上涂布光刻胶，利用半灰阶掩模板对该光刻胶进行曝光、显影，得到光阻层，所述光阻层上对应所述N型重掺杂区上方设有通孔，并且所述光阻层上对应于所述未掺杂区上方的厚度大于其它区域的厚度；
步骤3、以光阻层为遮蔽层，对所述栅极绝缘层进行干法刻蚀，从而得到位于所述N型重掺杂区上方的第一过孔，对所述光阻层进行氧气灰化处理，经氧气灰化处理后，剩余的光阻层位于所述多晶硅层的未掺杂区的上方，且尺寸小于该未掺杂区的尺寸；
步骤4、以剩余的光阻层为遮蔽层，对所述未掺杂区的两端进行N型离子注入，在所述未掺杂区的两端形成N型轻掺杂区，定义两N型轻掺杂区之间的未掺杂区域为沟道区；去除光阻层，在所述栅极绝缘层上沉积形成金属层，图案化该金属层，得到栅极、源极、及漏极，所述栅极、源极、及漏极不相连，所述源极、及漏极分别通过第一过孔与所述N型重掺杂区 相连接；
步骤5、在所述栅极、源极、及漏极上形成平坦层，通过光刻制程在所述平坦层上形成对应于所述栅极上方的第二过孔、以及对应于所述漏极上方的第三过孔；
步骤6、在所述平坦层上形成一ITO薄膜，图案化该ITO薄膜，得到公共电极、及透明电极，所述透明电极通过第二过孔与所述栅极相连接，从而栅极扫描信号可以通过该透明电极输入到栅极上。
所述步骤2中，所述半灰阶掩模板包括透光区、半透光区、及遮光区，在曝光过程中，所述透光区对应于所述N型重掺杂区上方，所述遮光区对应于所述未掺杂区上方。
所述步骤4中，进行沉积金属层之前，还包括对所述基板进行快速热退火处理。
所述缓冲层为由氮化硅薄膜和氧化硅薄膜所组成的叠层结构；所述多晶硅层的材料为低温多晶硅。
还包括步骤7、在所述公共电极、及透明电极上形成绝缘层，在所述绝缘层上形成像素电极，所述像素电极通过所述平坦层上的第三过孔与漏极相连接。
本发明还提供一种阵列基板，包括基板、设于所述基板上的遮光层、设于所述基板及遮光层上的缓冲层、设于所述缓冲层上的多晶硅层、设于所述多晶硅层上的栅极绝缘层、设于所述栅极绝缘层上的栅极、源极、及漏极、设于所述栅极绝缘层、栅极、源极、及漏极上的平坦层、以及设于所述平坦层上的公共电极与透明电极；
所述多晶硅层包括位于中间的沟道区、及位于两端的N型重掺杂区；
所述栅极绝缘层上设有对应于所述N型重掺杂区上方的第一过孔，所述平坦层上设有对应于所述栅极上方的第二过孔、及对应于所述漏极上方的第三过孔，所述透明电极通过第二过孔与所述栅极相连接，从而栅极扫描信号可以通过该透明电极输入到栅极上。
所述多晶硅层还包括位于沟道区与N型重掺杂区之间的N型轻掺杂区；所述源极、及漏极分别通过第一过孔与所述N型重掺杂区相连接。
所述栅极、源极、及漏极通过同一金属层经光刻制程制得，所述公共电极与所述透明电极通过同一ITO薄膜经光刻制程制得。
所述缓冲层为由氮化硅薄膜和氧化硅薄膜所组成的叠层结构；所述多晶硅层的材料为低温多晶硅。
所述阵列基板还包括设于公共电极与透明电极上的绝缘层、以及设于 所述绝缘层上的像素电极，所述像素电极通过所述平坦层上的第三过孔与漏极相连接。
本发明还提供一种阵列基板，包括基板、设于所述基板上的遮光层、设于所述基板及遮光层上的缓冲层、设于所述缓冲层上的多晶硅层、设于所述多晶硅层上的栅极绝缘层、设于所述栅极绝缘层上的栅极、源极、及漏极、设于所述栅极绝缘层、栅极、源极、及漏极上的平坦层、以及设于所述平坦层上的公共电极与透明电极；
所述多晶硅层包括位于所述多晶硅层两端的N型重掺杂区、及位于两N型重掺杂区之间的沟道区；
所述栅极绝缘层上设有对应于所述N型重掺杂区上方的第一过孔，所述平坦层上设有对应于所述栅极上方的第二过孔、及对应于所述漏极上方的第三过孔，所述透明电极通过第二过孔与所述栅极相连接，从而栅极扫描信号可以通过该透明电极输入到栅极上；
其中，所述多晶硅层还包括位于沟道区与N型重掺杂区之间的N型轻掺杂区；所述源极、及漏极分别通过第一过孔与所述N型重掺杂区相连接；
其中，所述栅极、源极、及漏极通过同一金属层经光刻制程制得，所述公共电极与所述透明电极通过同一ITO薄膜经光刻制程制得；
其中，所述阵列基板还包括设于公共电极与透明电极上的绝缘层、以及设于所述绝缘层上的像素电极，所述像素电极通过所述平坦层上的第三过孔与漏极相连接。
本发明的有益效果：本发明提供一种阵列基板及其制备方法，本发明的阵列基板的制备方法，将栅极与源漏极制作在同一金属层内，并将传统的整面型的公共电极层分割为两部分，其中一部分用作公共电极，另一部分用于实现栅极扫描信号输入，从而减少一道层间绝缘层制程，节省工艺制作成本；本发明的阵列基板，栅极与源漏极位于同一金属层内，栅极与源漏极之间不存在层间绝缘层，结构简化，从而降低了阵列基板的工艺制作成本。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有CMOS型低温多晶硅薄膜晶体管阵列基板的结构示意图；
图2为图1的CMOS型低温多晶硅薄膜晶体管阵列基板的俯视图；
图3为本发明的阵列基板的制备方法步骤1的示意图；
图4为本发明的阵列基板的制备方法步骤2的示意图；
图5为本发明的阵列基板的制备方法步骤3的示意图；
图6为本发明的阵列基板的制备方法步骤4的示意图；
图7为本发明的阵列基板的制备方法步骤4的俯视示意图；
图8为本发明的阵列基板的制备方法步骤5的示意图；
图9为本发明的阵列基板的制备方法步骤6的示意图；
图10为本发明的阵列基板的制备方法步骤6的俯视示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3-10，本发明提供一种阵列基板的制备方法，包括如下步骤：
步骤1、如图3所示，提供一基板11，在所述基板11上依次形成遮光层12、缓冲层13，在所述缓冲层13上形成多晶硅层14，对所述多晶硅层14的两端进行N型离子注入，得到位于所述多晶硅层14两端的N型重掺杂区141、及位于两N型重掺杂区141之间的未掺杂区145，在所述多晶硅层14上沉积栅极绝缘层15。
具体的，所述缓冲层12为由氮化硅薄膜和氧化硅薄膜所组成的叠层结构。
具体的，所述多晶硅层14的材料为低温多晶硅。
步骤2、如图4所示，在所述栅极绝缘层15上涂布光刻胶，利用半灰阶掩模板对该光刻胶进行曝光、显影，得到光阻层50，所述光阻层50上对应所述N型重掺杂区141上方设有通孔51，并且所述光阻层50上对应于所述未掺杂区145上方的厚度大于其它区域的厚度。
具体的，所述半灰阶掩模板包括透光区、半透光区、及遮光区，在曝光过程中，所述透光区对应于所述N型重掺杂区141上方，用于在所述N型重掺杂区142上方的栅极绝缘层15上形成过孔，所述遮光区对应于所述未掺杂区145上方。
步骤3、如图5所示，以光阻层50为遮蔽层，对所述栅极绝缘层15进行干法刻蚀，从而得到位于所述N型重掺杂区141上方的第一过孔151，对所述光阻层50进行氧气灰化处理，经氧气灰化处理后，剩余的光阻层50位于所述多晶硅层14的未掺杂区145的上方，且尺寸小于该未掺杂区145的尺寸。
步骤4、如图6所示，以剩余的光阻层50为遮蔽层，对所述未掺杂区145的两端进行N型离子注入，在所述未掺杂区145的两端形成N型轻掺杂区142，定义两N型轻掺杂区142之间的未掺杂区域为沟道区143；去除光阻层50，在所述栅极绝缘层15上通过物理气相沉积法沉积形成金属层，图案化该金属层，得到栅极16、源极17、及漏极18，所述栅极16、源极17、及漏极18不相连，所述源极17、及漏极18分别通过第一过孔151与所述N型重掺杂区141相连接；此时，基板的俯视图如图7所示。
具体的，所述步骤4中，进行沉积金属层之前，还需要对所述基板11进行快速热退火(RTA,Rapid Thermal Annealing)处理，以对多晶硅层14进行补氢和活化。
步骤5、如图8所示，在所述栅极16、源极17、及漏极18上形成平坦层19，通过光刻制程在所述平坦层19上形成对应于所述栅极16上方的第二过孔191、及对应于所述漏极18上方的第三过孔192。
步骤6、如图9所示，在所述平坦层19上形成一ITO薄膜，图案化该ITO薄膜，得到公共电极201、及透明电极202，所述透明电极202通过第二过孔191与所述栅极16相连接，从而栅极扫描信号可以通过该透明电极202输入到栅极16上，使得源极17与漏极18之间导通；此时，基板的俯视图如图10所示，具体的，透明电极202通过同一行内的第二过孔191将该行的栅极16进行连接，从而实现栅极扫描信号线的输入，并形成与所述源极17、及漏极18之间的垂直电路。
具体的，所述阵列基板的制作方法还包括步骤7、在所述公共电极201、及透明电极202上形成绝缘层，在所述绝缘层上形成像素电极，所述像素电极通过所述平坦层19上的第三过孔192与漏极18相连接。
请参阅图9-10，本发明还提供一种阵列基板，包括基板11、设于所述基板11上的遮光层12、设于所述基板11及遮光层12上的缓冲层13、设于所述缓冲层13上的多晶硅层14、设于所述多晶硅层14上的栅极绝缘层15、设于所述栅极绝缘层15上的栅极16、源极17、及漏极18、设于所述栅极绝缘层15、栅极16、源极17、及漏极18上的平坦层19、以及设于所述平坦层19上的公共电极201与透明电极202；
所述多晶硅层14包括位于中间的沟道区143、位于两端的N型重掺杂区141、以及位于沟道区143与N型重掺杂区141之间的N型轻掺杂区142；
所述栅极绝缘层15上设有对应于所述N型重掺杂区141上方的第一过孔151，所述平坦层19上设有对应于所述栅极16上方的第二过孔191、及对应于所述漏极18上方的第三过孔192，所述透明电极202通过第二过孔 191与所述栅极16相连接，从而栅极扫描信号可以通过该透明电极202输入到栅极16上，使得源极17与漏极18之间导通。
具体的，所述源极17、及漏极18分别通过第一过孔151与所述N型重掺杂区141相连接。
具体的，所述阵列基板还包括设于公共电极201与透明电极202上的绝缘层、以及设于所述绝缘层上的像素电极，所述像素电极通过所述平坦层19上的第三过孔192与漏极18相连接。
具体的，所述栅极16、源极17、及漏极18通过同一金属层经光刻制程制得，所述公共电极201与所述透明电极202通过同一ITO薄膜经光刻制程制得；
具体的，本发明的阵列基板为CMOS型低温多晶硅薄膜晶体管阵列基板；本发明的阵列基板可用于IPS(In-Plane Switching，平面转换)型液晶显示装置、或者FFS(Fringe Field Switching，边缘场开关)型液晶显示装置。
具体的，所述缓冲层12为由氮化硅薄膜和氧化硅薄膜所组成的叠层结构。
具体的，所述多晶硅层14的材料为低温多晶硅。
综上所述，本发明提供一种阵列基板及其制备方法，本发明的阵列基板的制备方法，将栅极与源漏极制作在同一金属层内，并将传统的整面型的公共电极层分割为两部分，其中一部分用作公共电极，另一部分用于实现栅极扫描信号输入，从而减少一道层间绝缘层制程，节省工艺制作成本；本发明的阵列基板，栅极与源漏极位于同一金属层内，栅极与源漏极之间不存在层间绝缘层，结构简化，从而降低了阵列基板的工艺制作成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (12)

  1. 一种阵列基板的制备方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上依次形成遮光层、缓冲层，在所述缓冲层上形成多晶硅层，对所述多晶硅层的两端进行N型离子注入，得到位于所述多晶硅层两端的N型重掺杂区、及位于两N型重掺杂区之间的未掺杂区，在所述多晶硅层上沉积栅极绝缘层；
    步骤2、在所述栅极绝缘层上涂布光刻胶，利用半灰阶掩模板对该光刻胶进行曝光、显影，得到光阻层，所述光阻层上对应所述N型重掺杂区上方设有通孔，并且所述光阻层上对应于所述未掺杂区上方的厚度大于其它区域的厚度；
    步骤3、以光阻层为遮蔽层，对所述栅极绝缘层进行干法刻蚀，从而得到位于所述N型重掺杂区上方的第一过孔，对所述光阻层进行氧气灰化处理，经氧气灰化处理后，剩余的光阻层位于所述多晶硅层的未掺杂区的上方，且尺寸小于该未掺杂区的尺寸；
    步骤4、以剩余的光阻层为遮蔽层，对所述未掺杂区的两端进行N型离子注入，在所述未掺杂区的两端形成N型轻掺杂区，定义两N型轻掺杂区之间的未掺杂区域为沟道区；去除光阻层，在所述栅极绝缘层上沉积形成金属层，图案化该金属层，得到栅极、源极、及漏极，所述栅极、源极、及漏极不相连，所述源极、及漏极分别通过第一过孔与所述N型重掺杂区相连接；
    步骤5、在所述栅极、源极、及漏极上形成平坦层，通过光刻制程在所述平坦层上形成对应于所述栅极上方的第二过孔、以及对应于所述漏极上方的第三过孔；
    步骤6、在所述平坦层上形成一ITO薄膜，图案化该ITO薄膜，得到公共电极、及透明电极，所述透明电极通过第二过孔与所述栅极相连接，从而栅极扫描信号可以通过该透明电极输入到栅极上。
  2. 如权利要求1所述的阵列基板的制备方法，其中，所述步骤2中，所述半灰阶掩模板包括透光区、半透光区、及遮光区，在曝光过程中，所述透光区对应于所述N型重掺杂区上方，所述遮光区对应于所述未掺杂区上方。
  3. 如权利要求1所述的阵列基板的制备方法，其中，所述步骤4中，进行沉积金属层之前，还需要对所述基板进行快速热退火处理。
  4. 如权利要求1所述的阵列基板的制备方法，其中，所述缓冲层为由氮化硅薄膜和氧化硅薄膜所组成的叠层结构；所述多晶硅层的材料为低温多晶硅。
  5. 如权利要求1所述的阵列基板的制备方法，其中，还包括步骤7、在所述公共电极、及透明电极上形成绝缘层，在所述绝缘层上形成像素电极，所述像素电极通过所述平坦层上的第三过孔与漏极相连接。
  6. 一种阵列基板，包括基板、设于所述基板上的遮光层、设于所述基板及遮光层上的缓冲层、设于所述缓冲层上的多晶硅层、设于所述多晶硅层上的栅极绝缘层、设于所述栅极绝缘层上的栅极、源极、及漏极、设于所述栅极绝缘层、栅极、源极、及漏极上的平坦层、以及设于所述平坦层上的公共电极与透明电极；
    所述多晶硅层包括位于所述多晶硅层两端的N型重掺杂区、及位于两N型重掺杂区之间的沟道区；
    所述栅极绝缘层上设有对应于所述N型重掺杂区上方的第一过孔，所述平坦层上设有对应于所述栅极上方的第二过孔、及对应于所述漏极上方的第三过孔，所述透明电极通过第二过孔与所述栅极相连接，从而栅极扫描信号可以通过该透明电极输入到栅极上。
  7. 如权利要求6所述的阵列基板，其中，所述多晶硅层还包括位于沟道区与N型重掺杂区之间的N型轻掺杂区；所述源极、及漏极分别通过第一过孔与所述N型重掺杂区相连接。
  8. 如权利要求6所述的阵列基板，其中，所述栅极、源极、及漏极通过同一金属层经光刻制程制得，所述公共电极与所述透明电极通过同一ITO薄膜经光刻制程制得。
  9. 如权利要求8所述的阵列基板，其中，所述缓冲层为由氮化硅薄膜和氧化硅薄膜所组成的叠层结构；所述多晶硅层的材料为低温多晶硅。
  10. 如权利要求6所述的阵列基板，其中，所述阵列基板还包括设于公共电极与透明电极上的绝缘层、以及设于所述绝缘层上的像素电极，所述像素电极通过所述平坦层上的第三过孔与漏极相连接。
  11. 一种阵列基板，包括基板、设于所述基板上的遮光层、设于所述基板及遮光层上的缓冲层、设于所述缓冲层上的多晶硅层、设于所述多晶硅层上的栅极绝缘层、设于所述栅极绝缘层上的栅极、源极、及漏极、设于所述栅极绝缘层、栅极、源极、及漏极上的平坦层、以及设于所述平坦层上的公共电极与透明电极；
    所述多晶硅层包括位于所述多晶硅层两端的N型重掺杂区、及位于两 N型重掺杂区之间的沟道区；
    所述栅极绝缘层上设有对应于所述N型重掺杂区上方的第一过孔，所述平坦层上设有对应于所述栅极上方的第二过孔、及对应于所述漏极上方的第三过孔，所述透明电极通过第二过孔与所述栅极相连接，从而栅极扫描信号可以通过该透明电极输入到栅极上；
    其中，所述多晶硅层还包括位于沟道区与N型重掺杂区之间的N型轻掺杂区；所述源极、及漏极分别通过第一过孔与所述N型重掺杂区相连接；
    其中，所述栅极、源极、及漏极通过同一金属层经光刻制程制得，所述公共电极与所述透明电极通过同一ITO薄膜经光刻制程制得；
    其中，所述阵列基板还包括设于公共电极与透明电极上的绝缘层、以及设于所述绝缘层上的像素电极，所述像素电极通过所述平坦层上的第三过孔与漏极相连接。
  12. 如权利要求11所述的阵列基板，其中，所述缓冲层为由氮化硅薄膜和氧化硅薄膜所组成的叠层结构；所述多晶硅层的材料为低温多晶硅。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112635495A (zh) * 2021-01-06 2021-04-09 Tcl华星光电技术有限公司 一种阵列基板及其制备方法、显示装置

Families Citing this family (20)

* Cited by examiner, † Cited by third party
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CN105572958A (zh) * 2016-02-29 2016-05-11 武汉华星光电技术有限公司 液晶显示面板
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CN106653695B (zh) * 2016-12-27 2018-07-06 武汉华星光电技术有限公司 一种低温多晶硅阵列基板及其制作方法
CN106816446A (zh) * 2017-03-08 2017-06-09 武汉华星光电技术有限公司 Tft阵列基板及液晶显示面板
CN107086181B (zh) * 2017-04-18 2021-08-13 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板和显示器
CN108198820B (zh) * 2017-12-26 2020-07-10 武汉华星光电技术有限公司 一种阵列基板及其制备方法
CN108598089B (zh) * 2018-04-27 2020-09-29 武汉华星光电技术有限公司 Tft基板的制作方法及tft基板
CN109212854B (zh) * 2018-08-29 2021-06-01 武汉华星光电技术有限公司 一种ltps阵列基板的制造方法
CN109346482B (zh) * 2018-09-30 2024-01-05 武汉华星光电技术有限公司 薄膜晶体管阵列基板及其制造方法、显示面板
CN110137182A (zh) * 2019-04-04 2019-08-16 惠科股份有限公司 一种阵列基板及其制造方法和显示面板
CN110112149A (zh) * 2019-05-23 2019-08-09 武汉华星光电技术有限公司 阵列基板检测键及显示面板
CN110993645A (zh) * 2019-11-06 2020-04-10 深圳市华星光电半导体显示技术有限公司 显示面板及其制备方法、显示装置
CN111223875A (zh) * 2019-11-06 2020-06-02 深圳市华星光电半导体显示技术有限公司 显示面板及其制备方法、显示装置
CN110993612A (zh) * 2019-11-27 2020-04-10 深圳市华星光电半导体显示技术有限公司 阵列基板及其制作方法
CN111129083A (zh) * 2019-12-11 2020-05-08 深圳市华星光电半导体显示技术有限公司 显示面板的制造方法及显示面板
CN111584509B (zh) * 2020-05-14 2023-03-31 深圳市华星光电半导体显示技术有限公司 显示面板及其制备方法、显示装置
CN111951729B (zh) * 2020-08-17 2023-06-09 武汉天马微电子有限公司 一种阵列基板、显示面板及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103383946A (zh) * 2013-07-12 2013-11-06 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制备方法
CN103472646A (zh) * 2013-08-30 2013-12-25 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
CN104637955A (zh) * 2015-01-30 2015-05-20 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN104681624A (zh) * 2014-12-24 2015-06-03 上海交通大学 单晶硅基底tft器件

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI309889B (en) * 2006-09-01 2009-05-11 Au Optronics Corp Liquid crystal display structure and method for manufacturing the same
KR102235725B1 (ko) * 2009-10-16 2021-04-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
TWI525818B (zh) * 2010-11-30 2016-03-11 半導體能源研究所股份有限公司 半導體裝置及半導體裝置之製造方法
US20140176886A1 (en) * 2011-08-09 2014-06-26 Sharp Kabushiki Kaisha Display device
KR20130016980A (ko) * 2011-08-09 2013-02-19 삼성디스플레이 주식회사 표시 장치
WO2013129239A1 (ja) * 2012-02-29 2013-09-06 シャープ株式会社 駆動装置および表示装置
CN103928472A (zh) * 2014-03-26 2014-07-16 京东方科技集团股份有限公司 一种阵列基板及其制作方法和显示装置
CN104362125B (zh) * 2014-09-25 2017-10-13 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104538357B (zh) * 2015-01-13 2018-05-01 合肥京东方光电科技有限公司 制作阵列基板的方法和阵列基板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103383946A (zh) * 2013-07-12 2013-11-06 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制备方法
CN103472646A (zh) * 2013-08-30 2013-12-25 京东方科技集团股份有限公司 一种阵列基板及其制备方法和显示装置
CN104681624A (zh) * 2014-12-24 2015-06-03 上海交通大学 单晶硅基底tft器件
CN104637955A (zh) * 2015-01-30 2015-05-20 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112635495A (zh) * 2021-01-06 2021-04-09 Tcl华星光电技术有限公司 一种阵列基板及其制备方法、显示装置
CN112635495B (zh) * 2021-01-06 2023-03-24 Tcl华星光电技术有限公司 一种阵列基板及其制备方法、显示装置

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