CN106816446A - Tft阵列基板及液晶显示面板 - Google Patents

Tft阵列基板及液晶显示面板 Download PDF

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CN106816446A
CN106816446A CN201710136806.7A CN201710136806A CN106816446A CN 106816446 A CN106816446 A CN 106816446A CN 201710136806 A CN201710136806 A CN 201710136806A CN 106816446 A CN106816446 A CN 106816446A
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doped region
heavily doped
grid
lightly doped
array substrate
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陈成
马亮
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to CN201710136806.7A priority Critical patent/CN106816446A/zh
Priority to US15/535,656 priority patent/US20180364503A1/en
Priority to PCT/CN2017/079702 priority patent/WO2018161397A1/zh
Publication of CN106816446A publication Critical patent/CN106816446A/zh
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Abstract

本发明提供一种TFT阵列基板，其包括基板及形成于基板上的TFT开关，所述TFT开关包括多晶硅层、栅极、第一轻掺杂区及重掺杂区，所述多晶硅层包括两个相对的延伸段及连接两个延伸段端部的主体段，所述栅极横跨两个所述延伸段设置，所述重掺杂区形成于所述多晶硅层的主体段并位于所述栅极一侧，所述第一轻掺杂区形成于所述重掺杂区中部位置。

Description

TFT阵列基板及液晶显示面板
技术领域
本发明涉及触摸屏技术领域，尤其涉及一种TFT阵列基板及液晶显示面板。
背景技术
液晶显示屏的薄膜晶体管(Thin Film Transistor，TFT)在关闭状态下掺杂区存在漏电现象，引起像素电极与公共电极之间电压差变化，漏电严重时会导致像素灰阶变化，产生串电等不良反应，使液晶屏幕的光学品质下降。目前主要从以下两方面来改善，1.增大像素储存电容；2.降低薄膜晶体管漏电流。其中降低薄膜晶体管漏电流一是通过增加TFT的沟道区长度或沟道数，但这样会降低像素开口率。
发明内容
本发明提供一种不影响像素开口率而降低薄膜晶体管开关漏电流的TFT阵列基板。
本申请还提供一种液晶显示面板。
本申请所述的TFT阵列基板包括基板及形成于基板上的TFT开关，所述TFT开关包括多晶硅层、栅极、第一轻掺杂区及重掺杂区，所述多晶硅层包括两个相对的延伸段及连接两个延伸段端部的主体段，所述栅极横跨两个所述延伸段设置，所述重掺杂区形成于所述多晶硅层的主体段并位于所述栅极一侧，所述第一轻掺杂区形成于所述重掺杂区中部位置。
其中，所述多晶硅层上位于所述栅极另一侧还设有辅助重掺杂区。
其中，所述第一轻掺杂区为所述重掺杂区进行第二次掺杂形成。
其中，所述TFT开关包括第二轻掺杂区，所述第二轻掺杂区位于所述栅极两侧与所述重掺杂区及辅助重掺杂区之间。
其中，所述第一轻掺杂区与第二轻掺杂区同一工艺步骤形成。
本申请提供一种液晶显示面板，包括彩膜基板、TFT阵列基板及位于彩膜基板与TFT阵列基板之间的液晶层，所述TFT阵列基板，包括基板即形成与基板上的TFT开关，所述TFT开关包括多晶硅层、栅极、第一轻掺杂区及重掺杂区，所述多晶硅层包括两个相对的延伸段及连接两个延伸段端部的主体段，所述栅极横跨两个所述延伸段设置，所述重掺杂区形成于所述多晶硅层的主体段并位于所述栅极一侧，所述第一轻掺杂区形成于所述重掺杂区中部位置。
其中，所述多晶硅层上位于所述栅极另一侧还设有辅助重掺杂区。
其中，所述第一轻掺杂区为所述重掺杂区进行第二次掺杂形成。
其中，所述TFT开关包括第二轻掺杂区，所述第二轻掺杂区位于所述栅极两侧与所述重掺杂区及辅助重掺杂区之间。
其中，所述第一轻掺杂区与第二轻掺杂区同一工艺步骤形成。
本申请所述的TFT开关在不影响阵列基板开口率及工艺制程的前提在重掺杂区内设置轻掺杂区，有效地降低TFT开关漏电流，且不影响开口率。
附图说明
为更清楚地阐述本发明的构造特征和功效，下面结合附图与具体实施例来对其进行详细说明。
图1是本发明液晶显示面板结构示意图；
图2是图1所示的TFT阵列基板的俯视图。
具体实施例
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。其中，附图仅用于示例性说明，表示的仅是示意图，不能理解为对本专利的限制。
请参阅图1与图2，本发明提供一种TFT阵列基板及液晶显示面板，其中，液晶显示面板包括彩膜基板20、所述TFT阵列基板10及位于彩膜基板20与TFT阵列基板10之间的液晶层30。所述液晶显示面板包括多个像素及与像素对应的设于TFT阵列基板上的TFT开关。所述TFT开关101与像素区域对应为像素提供电能。
请参阅图2，本实施例中，所述TFT阵列基板10包括基板11及形成于基板上的数个TFT开关101。本实施例以一个TFT开关为例进行说明。所述TFT开关101包括多晶硅层12、栅极13、第一轻掺杂区14及重掺杂区15。所述多晶硅层12包括两个相对的延伸段121及连接两个延伸段121端部的主体段122，所述栅极13横跨两个所述延伸段121设置，所述重掺杂区15形成于所述多晶硅层12的主体段122并位于所述栅极13一侧，所述第一轻掺杂区14形成于所述重掺杂区15中部位置。
本实施例中，所述多晶硅层12呈U型结构。所述重掺杂区15形成后，所述第一轻掺杂区14为所述重掺杂区15进行第二次掺杂形成。当所述TFT开关101关闭状态下，重掺杂区15区域的电阻成为控制漏电流的关键，由于重掺杂区15上设置有第一轻掺杂区14，增大了TFT开关的电阻，进而可以降低漏电流。而且在制造过程中，第一轻掺杂区14的长度可以根据TFT开关像素充电和漏电情况进行调整，以在满足充电要求的前提下有效降低漏电流。
所述栅极13横跨两个所述延伸段121并覆盖部分所述延伸段121。栅极13与所述延伸段121重叠区域构成沟道区。所述TFT开关101还设有辅助重掺杂区16。所述重掺杂区15与辅助重掺杂区16位于所述栅极13相对两侧，并均与所述栅极13间隔设置。所述重掺杂区15与辅助重掺杂区16在同一工艺步骤形成。
所述TFT开关101还包括第二轻掺杂区17，所述第二轻掺杂区17位于所述栅极13与所述重掺杂区15之间的间隔位置，以及栅极13与辅助重掺杂区16之间的间隔位置。所述第一轻掺杂区14与第二轻掺杂区17同一工艺步骤形成。
本申请所述的TFT开关在不影响阵列基板开口率及工艺制程的前提在重掺杂区内设置轻掺杂区，有效地降低TFT开关漏电流，同时能够满足TFT开关像素充电要求。
以上所述是本发明的优选实施例，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (10)

1.一种TFT阵列基板，包括基板及形成于基板上的TFT开关，其特征在于，所述TFT开关包括多晶硅层、栅极、第一轻掺杂区及重掺杂区，所述多晶硅层包括两个相对的延伸段及连接两个延伸段端部的主体段，所述栅极横跨两个所述延伸段设置，所述重掺杂区形成于所述多晶硅层的主体段并位于所述栅极一侧，所述第一轻掺杂区形成于所述重掺杂区中部位置。
2.如权利要求1所述的TFT阵列基板，其特征在于，所述多晶硅层上位于所述栅极另一侧还设有辅助重掺杂区。
3.如权利要求2所述的TFT阵列基板，其特征在于，所述第一轻掺杂区为所述重掺杂区进行第二次掺杂形成。
4.如权利要求3所述的TFT阵列基板，其特征在于，所述TFT开关包括第二轻掺杂区，所述第二轻掺杂区位于所述栅极两侧与所述重掺杂区及辅助重掺杂区之间。
5.如权利要求4所述的TFT阵列基板，其特征在于，所述第一轻掺杂区与第二轻掺杂区同一工艺步骤形成。
6.一种液晶显示面板，包括彩膜基板、TFT阵列基板及位于彩膜基板与TFT阵列基板之间的液晶层，其特征在于，所述TFT阵列基板，包括基板即形成与基板上的TFT开关，所述TFT开关包括多晶硅层、栅极、第一轻掺杂区及重掺杂区，所述多晶硅层包括两个相对的延伸段及连接两个延伸段端部的主体段，所述栅极横跨两个所述延伸段设置，所述重掺杂区形成于所述多晶硅层的主体段并位于所述栅极一侧，所述第一轻掺杂区形成于所述重掺杂区中部位置。
7.如权利要求6所述的液晶显示面板，其特征在于，所述多晶硅层上位于所述栅极另一侧还设有辅助重掺杂区。
8.如权利要求7所述的液晶显示面板，其特征在于，所述第一轻掺杂区为所述重掺杂区进行第二次掺杂形成。
9.如权利要求7所述的液晶显示面板，其特征在于，所述TFT开关包括第二轻掺杂区，所述第二轻掺杂区位于所述栅极两侧与所述重掺杂区及辅助重掺杂区之间。
10.如权利要求9所述的液晶显示面板，其特征在于，所述第一轻掺杂区与第二轻掺杂区同一工艺步骤形成。
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