CN109742088B - 一种tft阵列基板 - Google Patents
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Abstract
本发明提供一种TFT阵列基板,包括显示器件板和设置在所述显示器件板上的半导体层;其中,所述半导体层的厚度小于或等于35纳米。有益效果:在省遮光层,从而降低TFT阵列基板的生产周期和成本的基础上,通过降低半导体层的厚度以及有源岛的宽度,同时减小离子轻掺杂区的宽度来减少光生载流子,从而降低背光光生漏电流,从而减小显示面板的能耗。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种TFT阵列基板。
背景技术
液晶显示器(Liquid Crystal Display,LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点,成为显示装置中的主流。特别是LTPS(低温多晶硅)显示技术,由于其较高载流子迁移率可以使薄膜晶体管获得更高的开关电流比,提高面板开口率,改善面板亮点和高分辨率,降低面板功耗的效果,从而获得更好的视觉体验。
由于液晶显示器是一种靠电场来调节液晶分子的排列状态,从而实现光通量调制的被动型显示器件,需要精细的有源驱动矩阵(Array)配合各像素区液晶的偏转状况。鉴于低温多晶硅有源矩阵朝着不断缩小特征尺寸方向发展,为了降低低温多晶硅array基板的生产成本和周期,行业内有进行省LS(遮光层)mask工艺技术开发。
然而,省LS mask工艺后,会导致薄膜晶体管(TFT)中光生载流子增加,从而导致Ioff(光生漏电流)增加,从而导致面板功耗增加。
发明内容
本发明提供一种TFT阵列基板,以解决省遮光层工艺后,导致光生载流子增加,从而导致面板功耗增加的技术问题。
为解决上述问题,本发明提供的技术方案如下:
一种TFT阵列基板,包括显示器件板和设置在所述显示器件板上的半导体层;
其中,所述半导体层的厚度小于或等于35纳米。
进一步的,所述半导体层包括有源岛和与所述有源岛连接且垂直于所述有源岛的半导体走线,所述有源岛的宽度小于或等于1.8微米。
进一步的,所述半导体走线包括离子轻掺杂区和沟道连接区,所述离子轻掺杂区的宽度小于所述有源岛的宽度。
进一步的,所述沟道连接区的宽度与所述有源岛的宽度相同。
进一步的,所述沟道连接区的宽度小于所述有源岛的宽度。
进一步的,所述离子轻掺杂区的宽度与所述沟道连接区的宽度相同。
进一步的,所述离子轻掺杂区的宽度小于所述沟道连接区的宽度。
进一步的,所述显示器件板包括:
衬底基板;
设置在所述衬底基板上的缓冲层;
设置在所述缓冲层上的栅极绝缘层;
设置在所述栅极绝缘层上的栅极金属层;
设置在所述绝缘层上且覆盖所述栅极金属层的层间介质层;
设置在所述层间介质层上的源漏金属层;
其中,所述半导体层设置在所述缓冲层且被所述栅极绝缘层覆盖;所述半导体走线还包括搭接区,所述源漏金属层与所述搭接区接触连接。
进一步的,所述搭接区的宽度大于所述有源岛的宽度。
进一步的,所述栅极金属层的宽度大于所述沟道连接区的长度。
本发明的有益效果为:在省遮光层,从而降低TFT阵列基板的生产周期和成本的基础上,通过降低半导体层的厚度以及有源岛的宽度,同时减小离子轻掺杂区的宽度来减少光生载流子,从而降低背光光生漏电流,从而减小显示面板的能耗。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单介绍,显而易见地,下面描述中的附图仅仅是发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明具体实施方式中TFT阵列基板的结构示意图;
图2为本发明实施一中半导体层和栅极金属层的示意图;
图3为本发明实施二中半导体层和栅极金属层的示意图;
图4为本发明实施三中半导体层和栅极金属层的示意图。
附图标记:
10、衬底基板;20、缓冲层;30、栅极绝缘层;40、栅极金属层;50、层间介质层;61、源极;62、漏极;70、半导体层;71、有源岛;72、离子轻掺杂区;73、沟道连接区;74、搭接区。
具体实施方式
以下各实施例的说明是参考附加的图示,用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语,例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。在图中,结构相似的单元是用以相同标号表示。
本发明针对现有的TFT阵列基板中,省遮光层工艺后,导致光生载流子增加,从而导致面板功耗增加的技术问题。本发明可以解决上述问题。
实施例一:
一种TFT阵列基板,如图1所示,所述TFT阵列基板包括显示器件板和设置在所述显示器件板上的半导体层70。
其中,所述半导体层70的厚度小于或等于35纳米,在一实施方式中,所述半导体层70的厚度为30纳米。
具体的,所述显示器件板包括衬底基板10、设置在所述衬底基板10上的缓冲层20、设置在所述缓冲层20上的栅极绝缘层30、设置在所述栅极绝缘层30上的栅极金属层40、设置在所述绝缘层上且覆盖所述栅极金属层40的层间介质层50,以及,设置在所述层间介质层50上且与所述半导体层70接触连接的源漏金属层。
其中,所述半导体层70设置在所述缓冲层20且被所述栅极绝缘层30覆盖。
在省遮光层,从而降低TFT阵列基板的生产周期和成本的基础上,通过降低半导体层70的厚度,从而减小光照体积,从而减少光生载流子,降低背光光生漏电流,减小显示面板的功耗。
如图2所示,所述半导体层70整体呈“┌┐”形;所述半导体层70包括有源岛71和与所述有源岛71连接且垂直于所述有源岛71的半导体走线,所述有源岛71的宽度小于或等于1.8微米。
通过降低半导体层70的宽度,从而进一步减小光照体积,从而降低背光光生漏电流,减小显示面板的功耗。
需要说明的是,在实际实施中已确认,在有源岛71的宽度小于或等于1.8微米,并且半导体层70的厚度小于或等于35纳米的前提下,光生漏电流大幅度下降,处于较低水平。
在一实施方式中,所述有源岛71的宽度为1.5微米。
具体的,所述半导体走线包括离子轻掺杂区72和沟道连接区73;所述沟道连接区73的宽度与所述有源岛71的宽度相同,并且,所述离子轻掺杂区72的宽度小于所述有源岛71的宽度。
通过减小离子轻掺杂区72的宽度尺寸,进一步降低背光光生漏电流。
进一步的,所述栅极金属层40的宽度大于所述沟道连接区73的长度,即沟道的宽度尺寸大于沟道连接区73的长度尺寸,从而增加薄膜晶体管的充电率。
具体的,所述半导体走线还包括搭接区74,所述源漏金属层包括与所述搭接区74接触连接的源极61和漏极62。
进一步的,所述搭接区74的宽度大于所述有源岛71的宽度。便于源极61和漏极62与所述半导体层70的接触连接,降低显示面板生产制程的工艺难度。
实施二:
一种TFT阵列基板,如图3所示,其与实施一的不同之处仅在于所述沟道连接区73的宽度不同。
具体的,所述沟道连接区73的宽度小于所述有源岛71的宽度,并且,所述离子轻掺杂区72的宽度与所述沟道连接区73的宽度相同。
实施例三:
一种TFT阵列基板,如图4所示,其与实施二的不同之处仅在于所述离子轻掺杂区72的宽度不同。
具体的,所述离子轻掺杂区72的宽度小于所述沟道连接区73的宽度。
本发明的有益效果为:在省遮光层,从而降低TFT阵列基板的生产周期和成本的基础上,通过降低半导体层70的厚度以及有源岛71的宽度,同时减小离子轻掺杂区72的宽度来减少光生载流子,从而降低背光光生漏电流,从而减小显示面板的能耗。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。
Claims (9)
1.一种TFT阵列基板,其特征在于,所述TFT阵列基板包括显示器件板和设置在所述显示器件板上的半导体层;
其中,所述半导体层的厚度小于或等于35纳米;所述半导体层包括有源岛和与所述有源岛连接的半导体走线,所述半导体走线包括离子轻掺杂区和沟道连接区,所述离子轻掺杂区的宽度小于所述有源岛的宽度。
2.根据权利要求1所述的TFT阵列基板,其特征在于,所述半导体走线垂直于所述有源岛,所述有源岛的宽度小于或等于1.8微米。
3.根据权利要求2所述的TFT阵列基板,其特征在于,所述沟道连接区的宽度与所述有源岛的宽度相同。
4.根据权利要求2所述的TFT阵列基板,其特征在于,所述沟道连接区的宽度小于所述有源岛的宽度。
5.根据权利要求4的TFT阵列基板,其特征在于,所述离子轻掺杂区的宽度与所述沟道连接区的宽度相同。
6.根据权利要求4的TFT阵列基板,其特征在于,所述离子轻掺杂区的宽度小于所述沟道连接区的宽度。
7.根据权利要求2所述的TFT阵列基板,其特征在于,所述显示器件板包括:
衬底基板;
设置在所述衬底基板上的缓冲层;
设置在所述缓冲层上的栅极绝缘层;
设置在所述栅极绝缘层上的栅极金属层;
设置在所述绝缘层上且覆盖所述栅极金属层的层间介质层;
设置在所述层间介质层上的源漏金属层;
其中,所述半导体层设置在所述缓冲层且被所述栅极绝缘层覆盖;所述半导体走线还包括搭接区,所述源漏金属层与所述搭接区接触连接。
8.根据权利要求7所述的TFT阵列基板,其特征在于,所述搭接区的宽度大于所述有源岛的宽度。
9.根据权利要求7所述的TFT阵列基板,其特征在于,所述栅极金属层的宽度大于所述沟道连接区的长度。
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