WO2020133747A1 - 一种tft阵列基板 - Google Patents

一种tft阵列基板 Download PDF

Info

Publication number
WO2020133747A1
WO2020133747A1 PCT/CN2019/079416 CN2019079416W WO2020133747A1 WO 2020133747 A1 WO2020133747 A1 WO 2020133747A1 CN 2019079416 W CN2019079416 W CN 2019079416W WO 2020133747 A1 WO2020133747 A1 WO 2020133747A1
Authority
WO
WIPO (PCT)
Prior art keywords
width
array substrate
tft array
region
active island
Prior art date
Application number
PCT/CN2019/079416
Other languages
English (en)
French (fr)
Inventor
张鑫
李立胜
何鹏
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/475,137 priority Critical patent/US11114468B2/en
Publication of WO2020133747A1 publication Critical patent/WO2020133747A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to the field of display technology, in particular to a TFT array substrate.
  • LTPS low temperature polysilicon
  • a liquid crystal display is a passive display device that adjusts the arrangement state of liquid crystal molecules by an electric field, thereby realizing luminous flux modulation
  • a fine active drive matrix is required to match the deflection status of liquid crystal in each pixel area.
  • LS light-shielding layer
  • TFT thin film transistor
  • a TFT array substrate including a display device board and a semiconductor layer provided on the display device board;
  • the thickness of the semiconductor layer is less than or equal to 35 nanometers; the whole semiconductor layer is in the shape of " ⁇ ".
  • the semiconductor layer includes an active island and a semiconductor trace connected to the active island and perpendicular to the active island, and the width of the active island is less than or equal to 1.8 microns.
  • the semiconductor trace includes an ion lightly doped region and a channel connection region, and the width of the ion lightly doped region is smaller than the width of the active island.
  • the width of the channel connection region is the same as the width of the active island.
  • the width of the channel connection region is smaller than the width of the active island.
  • the width of the lightly doped ion region is the same as the width of the channel connection region.
  • the width of the lightly doped ion region is smaller than the width of the channel connection region.
  • the display device board includes:
  • a buffer layer provided on the base substrate
  • a gate insulating layer provided on the buffer layer
  • a gate metal layer provided on the gate insulating layer
  • An interlayer dielectric layer disposed on the insulating layer and covering the gate metal layer;
  • a source-drain metal layer provided on the interlayer dielectric layer
  • the semiconductor layer is disposed on the buffer layer and is covered by the gate insulating layer; the semiconductor trace further includes an overlap region, and the source-drain metal layer is in contact connection with the overlap region.
  • the width of the overlapping area is larger than the width of the active island.
  • the width of the gate metal layer is greater than the length of the channel connection region.
  • a TFT array substrate including a display device board and a semiconductor layer provided on the display device board;
  • the thickness of the semiconductor layer is less than or equal to 35 nm.
  • the semiconductor layer includes an active island and a semiconductor trace connected to the active island and perpendicular to the active island, and the width of the active island is less than or equal to 1.8 microns.
  • the semiconductor trace includes an ion lightly doped region and a channel connection region, and the width of the ion lightly doped region is smaller than the width of the active island.
  • the width of the channel connection region is the same as the width of the active island.
  • the width of the channel connection region is smaller than the width of the active island.
  • the width of the lightly doped ion region is the same as the width of the channel connection region.
  • the width of the lightly doped ion region is smaller than the width of the channel connection region.
  • the display device board includes:
  • a buffer layer provided on the base substrate
  • a gate insulating layer provided on the buffer layer
  • a gate metal layer provided on the gate insulating layer
  • An interlayer dielectric layer disposed on the insulating layer and covering the gate metal layer;
  • a source-drain metal layer provided on the interlayer dielectric layer
  • the semiconductor layer is disposed on the buffer layer and is covered by the gate insulating layer; the semiconductor trace further includes an overlap region, and the source-drain metal layer is in contact connection with the overlap region.
  • the width of the overlapping area is larger than the width of the active island.
  • the width of the gate metal layer is greater than the length of the channel connection region.
  • FIG. 1 is a schematic structural diagram of a TFT array substrate in a specific embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a semiconductor layer and a gate metal layer in the first embodiment of the present invention
  • FIG. 3 is a schematic diagram of a semiconductor layer and a gate metal layer in the second embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a semiconductor layer and a gate metal layer in the third embodiment of the present invention.
  • Base substrate 20, buffer layer; 30, gate insulating layer; 40, gate metal layer; 50, interlayer dielectric layer; 61, source; 62, drain; 70, semiconductor layer; 71, yes Source island; 72, lightly doped ion region; 73, channel connection region; 74, overlapping region.
  • the present invention is directed to the technical problem that after the light-shielding layer process is saved in the existing TFT array substrate, the photogenerated carriers are increased, which leads to increased power consumption of the panel.
  • the present invention can solve the above problems.
  • the TFT array substrate includes a display device board and a semiconductor layer 70 provided on the display device board.
  • the thickness of the semiconductor layer 70 is less than or equal to 35 nm. In an embodiment, the thickness of the semiconductor layer 70 is 30 nm.
  • the display device board includes a base substrate 10, a buffer layer 20 disposed on the base substrate 10, a gate insulating layer 30 disposed on the buffer layer 20, and a gate insulating
  • the semiconductor layer 70 is disposed on the buffer layer 20 and is covered by the gate insulating layer 30.
  • the semiconductor layer 70 has a “ ⁇ ” shape as a whole; the semiconductor layer 70 includes an active island 71 and a semiconductor walk connected to the active island 71 and perpendicular to the active island 71 Line, the width of the active island 71 is less than or equal to 1.8 microns.
  • the illumination volume is further reduced, thereby reducing the backlight leakage current and reducing the power consumption of the display panel.
  • the photogenerated leakage current greatly decreases and is at a low level. Level.
  • the width of the active island 71 is 1.5 microns.
  • the semiconductor trace includes an ion lightly doped region 72 and a channel connection region 73; the width of the channel connection region 73 is the same as the width of the active island 71, and the ion lightly doped region The width of the area 72 is smaller than the width of the active island 71.
  • the backlight photogenerated leakage current is further reduced.
  • the width of the gate metal layer 40 is greater than the length of the channel connection region 73, that is, the width dimension of the channel is greater than the length dimension of the channel connection region 73, thereby increasing the charging rate of the thin film transistor.
  • the semiconductor trace further includes an overlap region 74
  • the source-drain metal layer includes a source electrode 61 and a drain electrode 62 connected in contact with the overlap region 74.
  • the width of the overlapping region 74 is greater than the width of the active island 71. This facilitates the contact connection between the source electrode 61 and the drain electrode 62 and the semiconductor layer 70, and reduces the process difficulty of the display panel production process.
  • a TFT array substrate, as shown in FIG. 3, differs from Embodiment 1 only in that the width of the channel connection region 73 is different.
  • the width of the channel connection region 73 is smaller than the width of the active island 71, and the width of the ion lightly doped region 72 is the same as the width of the channel connection region 73.
  • a TFT array substrate, as shown in FIG. 4, is different from Embodiment 2 only in that the width of the ion lightly doped region 72 is different.
  • the width of the lightly doped ion region 72 is smaller than the width of the channel connection region 73.
  • the beneficial effects of the present invention are: on the basis of saving the shading layer, thereby reducing the production cycle and cost of the TFT array substrate, by reducing the thickness of the semiconductor layer 70 and the width of the active island 71, while reducing the ion lightly doped region 72 To reduce the photo-generated carriers and the backlight photo-generated leakage current, thereby reducing the power consumption of the display panel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Nanotechnology (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种TFT阵列基板，包括显示器件板和设置在显示器件板上的半导体层（70）；半导体层（70）的厚度小于或等于35纳米。

Description

一种TFT阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板。
 背景技术
液晶显示器（Liquid Crystal Display，LCD）等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，成为显示装置中的主流。特别是LTPS（低温多晶硅）显示技术，由于其较高载流子迁移率可以使薄膜晶体管获得更高的开关电流比，提高面板开口率，改善面板亮点和高分辨率，降低面板功耗的效果，从而获得更好的视觉体验。
由于液晶显示器是一种靠电场来调节液晶分子的排列状态，从而实现光通量调制的被动型显示器件，需要精细的有源驱动矩阵（Array）配合各像素区液晶的偏转状况。鉴于低温多晶硅有源矩阵朝着不断缩小特征尺寸方向发展，为了降低低温多晶硅array基板的生产成本和周期，行业内有进行省LS（遮光层）mask工艺技术开发。
然而，省LS mask工艺后，会导致薄膜晶体管（TFT）中光生载流子增加，从而导致Ioff（光生漏电流）增加，从而导致面板功耗增加。
 技术问题
省LS mask工艺后，会导致薄膜晶体管（TFT）中光生载流子增加，从而导致Ioff（光生漏电流）增加，从而导致面板功耗增加。
 技术解决方案
一种TFT阵列基板，包括显示器件板和设置在所述显示器件板上的半导体层；
其中，所述半导体层的厚度小于或等于35纳米；所述半导体层整体呈“┌┐”形。
进一步的，所述半导体层包括有源岛和与所述有源岛连接且垂直于所述有源岛的半导体走线，所述有源岛的宽度小于或等于1.8微米。
进一步的，所述半导体走线包括离子轻掺杂区和沟道连接区，所述离子轻掺杂区的宽度小于所述有源岛的宽度。
进一步的，所述沟道连接区的宽度与所述有源岛的宽度相同。
进一步的，所述沟道连接区的宽度小于所述有源岛的宽度。
进一步的，所述离子轻掺杂区的宽度与所述沟道连接区的宽度相同。
进一步的，所述离子轻掺杂区的宽度小于所述沟道连接区的宽度。
进一步的，所述显示器件板包括：
衬底基板；
设置在所述衬底基板上的缓冲层；
设置在所述缓冲层上的栅极绝缘层；
设置在所述栅极绝缘层上的栅极金属层；
设置在所述绝缘层上且覆盖所述栅极金属层的层间介质层；
设置在所述层间介质层上的源漏金属层；
其中，所述半导体层设置在所述缓冲层且被所述栅极绝缘层覆盖；所述半导体走线还包括搭接区，所述源漏金属层与所述搭接区接触连接。
进一步的，所述搭接区的宽度大于所述有源岛的宽度。
进一步的，所述栅极金属层的宽度大于所述沟道连接区的长度。
一种TFT阵列基板，包括显示器件板和设置在所述显示器件板上的半导体层；
其中，所述半导体层的厚度小于或等于35纳米。
进一步的，所述半导体层包括有源岛和与所述有源岛连接且垂直于所述有源岛的半导体走线，所述有源岛的宽度小于或等于1.8微米。
进一步的，所述半导体走线包括离子轻掺杂区和沟道连接区，所述离子轻掺杂区的宽度小于所述有源岛的宽度。
进一步的，所述沟道连接区的宽度与所述有源岛的宽度相同。
进一步的，所述沟道连接区的宽度小于所述有源岛的宽度。
进一步的，所述离子轻掺杂区的宽度与所述沟道连接区的宽度相同。
进一步的，所述离子轻掺杂区的宽度小于所述沟道连接区的宽度。
进一步的，所述显示器件板包括：
衬底基板；
设置在所述衬底基板上的缓冲层；
设置在所述缓冲层上的栅极绝缘层；
设置在所述栅极绝缘层上的栅极金属层；
设置在所述绝缘层上且覆盖所述栅极金属层的层间介质层；
设置在所述层间介质层上的源漏金属层；
其中，所述半导体层设置在所述缓冲层且被所述栅极绝缘层覆盖；所述半导体走线还包括搭接区，所述源漏金属层与所述搭接区接触连接。
进一步的，所述搭接区的宽度大于所述有源岛的宽度。
进一步的，所述栅极金属层的宽度大于所述沟道连接区的长度。
 有益效果
在省遮光层，从而降低TFT阵列基板的生产周期和成本的基础上，通过降低半导体层的厚度以及有源岛的宽度，同时减小离子轻掺杂区的宽度来减少光生载流子，从而降低背光光生漏电流，从而减小显示面板的能耗。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明具体实施方式中TFT阵列基板的结构示意图；
图2为本发明实施一中半导体层和栅极金属层的示意图；
图3为本发明实施二中半导体层和栅极金属层的示意图；
图4为本发明实施三中半导体层和栅极金属层的示意图。
附图标记：
10、衬底基板；20、缓冲层；30、栅极绝缘层；40、栅极金属层；50、层间介质层；61、源极；62、漏极；70、半导体层；71、有源岛；72、离子轻掺杂区；73、沟道连接区；74、搭接区。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的TFT阵列基板中，省遮光层工艺后，导致光生载流子增加，从而导致面板功耗增加的技术问题。本发明可以解决上述问题。
实施例一：
一种TFT阵列基板，如图1所示，所述TFT阵列基板包括显示器件板和设置在所述显示器件板上的半导体层70。
其中，所述半导体层70的厚度小于或等于35纳米，在一实施方式中，所述半导体层70的厚度为30纳米。
具体的，所述显示器件板包括衬底基板10、设置在所述衬底基板10上的缓冲层20、设置在所述缓冲层20上的栅极绝缘层30、设置在所述栅极绝缘层30上的栅极金属层40、设置在所述绝缘层上且覆盖所述栅极金属层40的层间介质层50，以及，设置在所述层间介质层50上且与所述半导体层70接触连接的源漏金属层。
其中，所述半导体层70设置在所述缓冲层20且被所述栅极绝缘层30覆盖。
在省遮光层，从而降低TFT阵列基板的生产周期和成本的基础上，通过降低半导体层70的厚度，从而减小光照体积，从而减少光生载流子，降低背光光生漏电流，减小显示面板的功耗。
如图2所示，所述半导体层70整体呈“┌┐”形；所述半导体层70包括有源岛71和与所述有源岛71连接且垂直于所述有源岛71的半导体走线，所述有源岛71的宽度小于或等于1.8微米。
通过降低半导体层70的宽度，从而进一步减小光照体积，从而降低背光光生漏电流，减小显示面板的功耗。
需要说明的是，在实际实施中已确认，在有源岛71的宽度小于或等于1.8微米，并且半导体层70的厚度小于或等于35纳米的前提下，光生漏电流大幅度下降，处于较低水平。
在一实施方式中，所述有源岛71的宽度为1.5微米。
具体的，所述半导体走线包括离子轻掺杂区72和沟道连接区73；所述沟道连接区73的宽度与所述有源岛71的宽度相同，并且，所述离子轻掺杂区72的宽度小于所述有源岛71的宽度。
通过减小离子轻掺杂区72的宽度尺寸，进一步降低背光光生漏电流。
进一步的，所述栅极金属层40的宽度大于所述沟道连接区73的长度，即沟道的宽度尺寸大于沟道连接区73的长度尺寸，从而增加薄膜晶体管的充电率。
具体的，所述半导体走线还包括搭接区74，所述源漏金属层包括与所述搭接区74接触连接的源极61和漏极62。
进一步的，所述搭接区74的宽度大于所述有源岛71的宽度。便于源极61和漏极62与所述半导体层70的接触连接，降低显示面板生产制程的工艺难度。
实施二：
一种TFT阵列基板，如图3所示，其与实施一的不同之处仅在于所述沟道连接区73的宽度不同。
具体的，所述沟道连接区73的宽度小于所述有源岛71的宽度，并且，所述离子轻掺杂区72的宽度与所述沟道连接区73的宽度相同。
实施例三：
一种TFT阵列基板，如图4所示，其与实施二的不同之处仅在于所述离子轻掺杂区72的宽度不同。
具体的，所述离子轻掺杂区72的宽度小于所述沟道连接区73的宽度。
本发明的有益效果为：在省遮光层，从而降低TFT阵列基板的生产周期和成本的基础上，通过降低半导体层70的厚度以及有源岛71的宽度，同时减小离子轻掺杂区72的宽度来减少光生载流子，从而降低背光光生漏电流，从而减小显示面板的能耗。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种TFT阵列基板，其中，所述TFT阵列基板包括显示器件板和设置在所述显示器件板上的半导体层；
    其中，所述半导体层的厚度小于或等于35纳米；所述半导体层整体呈“┌┐”形。
  2. 根据权利要求1所述的TFT阵列基板，其中，所述半导体层包括有源岛和与所述有源岛连接且垂直于所述有源岛的半导体走线，所述有源岛的宽度小于或等于1.8微米。
  3. 根据权利要求2所述的TFT阵列基板，其中，所述半导体走线包括离子轻掺杂区和沟道连接区，所述离子轻掺杂区的宽度小于所述有源岛的宽度。
  4. 根据权利要求3所述的TFT阵列基板，其中，所述沟道连接区的宽度与所述有源岛的宽度相同。
  5. 根据权利要求3所述的TFT阵列基板，其中，所述沟道连接区的宽度小于所述有源岛的宽度。
  6. 根据权利要求5的TFT阵列基板，其中，所述离子轻掺杂区的宽度与所述沟道连接区的宽度相同。
  7. 根据权利要求5的TFT阵列基板，其中，所述离子轻掺杂区的宽度小于所述沟道连接区的宽度。
  8. 根据权利要求3所述的TFT阵列基板，其中，所述显示器件板包括：
    衬底基板；
    设置在所述衬底基板上的缓冲层；
    设置在所述缓冲层上的栅极绝缘层；
    设置在所述栅极绝缘层上的栅极金属层；
    设置在所述绝缘层上且覆盖所述栅极金属层的层间介质层；
    设置在所述层间介质层上的源漏金属层；
    其中，所述半导体层设置在所述缓冲层且被所述栅极绝缘层覆盖；所述半导体走线还包括搭接区，所述源漏金属层与所述搭接区接触连接。
  9. 根据权利要求8所述的TFT阵列基板，其中，所述搭接区的宽度大于所述有源岛的宽度。
  10. 根据权利要求8所述的TFT阵列基板，其中，所述栅极金属层的宽度大于所述沟道连接区的长度。
  11. 一种TFT阵列基板，其中，所述TFT阵列基板包括显示器件板和设置在所述显示器件板上的半导体层；
    其中，所述半导体层的厚度小于或等于35纳米。
  12. 根据权利要求11所述的TFT阵列基板，其中，所述半导体层包括有源岛和与所述有源岛连接且垂直于所述有源岛的半导体走线，所述有源岛的宽度小于或等于1.8微米。
  13. 根据权利要求12所述的TFT阵列基板，其中，所述半导体走线包括离子轻掺杂区和沟道连接区，所述离子轻掺杂区的宽度小于所述有源岛的宽度。
  14. 根据权利要求13所述的TFT阵列基板，其中，所述沟道连接区的宽度与所述有源岛的宽度相同。
  15. 根据权利要求13所述的TFT阵列基板，其中，所述沟道连接区的宽度小于所述有源岛的宽度。
  16. 根据权利要求15的TFT阵列基板，其中，所述离子轻掺杂区的宽度与所述沟道连接区的宽度相同。
  17. 根据权利要求15的TFT阵列基板，其中，所述离子轻掺杂区的宽度小于所述沟道连接区的宽度。
  18. 根据权利要求13所述的TFT阵列基板，其中，所述显示器件板包括：
    衬底基板；
    设置在所述衬底基板上的缓冲层；
    设置在所述缓冲层上的栅极绝缘层；
    设置在所述栅极绝缘层上的栅极金属层；
    设置在所述绝缘层上且覆盖所述栅极金属层的层间介质层；
    设置在所述层间介质层上的源漏金属层；
    其中，所述半导体层设置在所述缓冲层且被所述栅极绝缘层覆盖；所述半导体走线还包括搭接区，所述源漏金属层与所述搭接区接触连接。
  19. 根据权利要求18所述的TFT阵列基板，其中，所述搭接区的宽度大于所述有源岛的宽度。
  20. 根据权利要求18所述的TFT阵列基板，其中，所述栅极金属层的宽度大于所述沟道连接区的长度。
PCT/CN2019/079416 2018-12-29 2019-03-25 一种tft阵列基板 WO2020133747A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/475,137 US11114468B2 (en) 2018-12-29 2019-03-25 Thin film transistor array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811647150.6A CN109742088B (zh) 2018-12-29 2018-12-29 一种tft阵列基板
CN201811647150.6 2018-12-29

Publications (1)

Publication Number Publication Date
WO2020133747A1 true WO2020133747A1 (zh) 2020-07-02

Family

ID=66362741

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/079416 WO2020133747A1 (zh) 2018-12-29 2019-03-25 一种tft阵列基板

Country Status (3)

Country Link
US (1) US11114468B2 (zh)
CN (1) CN109742088B (zh)
WO (1) WO2020133747A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110416286B (zh) * 2019-07-30 2023-07-18 京东方科技集团股份有限公司 一种显示面板、其制作方法及显示装置
CN114156288A (zh) * 2021-11-30 2022-03-08 武汉华星光电技术有限公司 阵列基板及显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101114086A (zh) * 2006-07-27 2008-01-30 爱普生映像元器件有限公司 液晶显示装置
CN103346093A (zh) * 2013-06-13 2013-10-09 北京大学深圳研究生院 源/漏区抬高的顶栅自对准薄膜晶体管及其制作方法
US20140103349A1 (en) * 2012-08-31 2014-04-17 Apple Inc. Different lightly doped drain length control for self-align light drain doping process
CN103746000A (zh) * 2013-12-25 2014-04-23 深圳市华星光电技术有限公司 一种多晶硅tft器件及其制造方法
CN106128963A (zh) * 2016-09-23 2016-11-16 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示面板
CN106505071A (zh) * 2016-10-18 2017-03-15 武汉华星光电技术有限公司 薄膜晶体管阵列基板及其制作方法
CN206628473U (zh) * 2017-04-26 2017-11-10 厦门天马微电子有限公司 一种薄膜晶体管、显示面板和显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09298305A (ja) * 1996-05-08 1997-11-18 Semiconductor Energy Lab Co Ltd 薄膜トランジスタおよびかかる薄膜トランジスタを有する液晶表示装置
JP4470395B2 (ja) * 2003-05-30 2010-06-02 日本電気株式会社 半導体薄膜の製造方法及び製造装置、並びに薄膜トランジスタ
KR101186292B1 (ko) * 2006-01-10 2012-09-27 삼성전자주식회사 트랜지스터와 트랜지스터의 제조방법 및 이를 적용하는유기발광 디스플레이 및 그 제조방법
KR102226234B1 (ko) * 2014-06-16 2021-03-11 엘지디스플레이 주식회사 박막 트랜지스터 어레이 기판 및 이의 제조 방법
KR102397799B1 (ko) * 2015-06-30 2022-05-16 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이를 포함하는 표시장치
TWI578509B (zh) * 2015-07-23 2017-04-11 友達光電股份有限公司 畫素結構
CN105742240B (zh) * 2016-04-05 2019-09-13 武汉华星光电技术有限公司 一种ltps阵列基板的制造方法
CN206003775U (zh) * 2016-08-31 2017-03-08 鸿之微科技（上海）有限公司 量子隧穿场效应晶体管
CN106816446A (zh) * 2017-03-08 2017-06-09 武汉华星光电技术有限公司 Tft阵列基板及液晶显示面板
CN109427911B (zh) * 2017-08-31 2021-12-14 昆山国显光电有限公司 一种柔性薄膜晶体管及其制备方法
CN108417580B (zh) * 2018-01-30 2020-12-18 上海天马有机发光显示技术有限公司 阵列基板及其制作方法和显示面板
CN108598175B (zh) * 2018-06-07 2021-10-22 京东方科技集团股份有限公司 薄膜晶体管及制造方法和显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101114086A (zh) * 2006-07-27 2008-01-30 爱普生映像元器件有限公司 液晶显示装置
US20140103349A1 (en) * 2012-08-31 2014-04-17 Apple Inc. Different lightly doped drain length control for self-align light drain doping process
CN103346093A (zh) * 2013-06-13 2013-10-09 北京大学深圳研究生院 源/漏区抬高的顶栅自对准薄膜晶体管及其制作方法
CN103746000A (zh) * 2013-12-25 2014-04-23 深圳市华星光电技术有限公司 一种多晶硅tft器件及其制造方法
CN106128963A (zh) * 2016-09-23 2016-11-16 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示面板
CN106505071A (zh) * 2016-10-18 2017-03-15 武汉华星光电技术有限公司 薄膜晶体管阵列基板及其制作方法
CN206628473U (zh) * 2017-04-26 2017-11-10 厦门天马微电子有限公司 一种薄膜晶体管、显示面板和显示装置

Also Published As

Publication number Publication date
CN109742088B (zh) 2021-03-16
US20200251503A1 (en) 2020-08-06
CN109742088A (zh) 2019-05-10
US11114468B2 (en) 2021-09-07

Similar Documents

Publication Publication Date Title
WO2017101204A1 (zh) 液晶显示装置
US9741752B1 (en) Method for manufacturing TFT substrate
WO2021012344A1 (zh) 一种TFT驱动背板及Micro-LED显示器
WO2021027059A1 (zh) 一种阵列基板及其制备方法、触控显示面板
US20210126022A1 (en) Array substrate and method for manufacturing same
WO2017016014A1 (zh) Coa阵列基板及液晶面板
US20210041733A1 (en) Array substrate, method manufacturing same and touch display panel
US11800749B2 (en) Display panel and a display device including a pixel circuit and a driver circuit
WO2020107723A1 (zh) 一种阵列基板及显示面板
WO2020133747A1 (zh) 一种tft阵列基板
WO2020118952A1 (zh) 一种 oled 显示装置及其制作方法
US20190326335A1 (en) Manufacturing method for a tft array substrate and tft array substrate
US20140204305A1 (en) Tft structure, lcd device, and method for manufacturing tft
WO2020206811A1 (zh) 一种tft阵列基板、其制备方法及其显示面板
WO2021082266A1 (zh) 一种阵列基板、其制备方法及其显示面板
WO2020215547A1 (zh) Tft阵列基板及其制作方法
WO2020232784A1 (zh) Tft基板的制作方法及tft基板
CN105140298A (zh) 薄膜晶体管和阵列基板
CN113299666B (zh) 显示面板及其驱动方法、显示装置
KR101831080B1 (ko) 박막 트랜지스터 기판의 제조 방법 및 이를 이용하여 제조된 박막 트랜지스터 기판
US11887990B2 (en) Method for manufacturing array substrate
WO2023082349A1 (zh) 阵列基板及其制备方法、显示面板
WO2023065392A1 (zh) 阵列基板和显示面板
US10749037B2 (en) Low temperature poly-silicon TFT substrate and manufacturing method thereof
US8912542B2 (en) TFT structure and LCD device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19906225

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19906225

Country of ref document: EP

Kind code of ref document: A1