WO2020107723A1 - 一种阵列基板及显示面板 - Google Patents

一种阵列基板及显示面板 Download PDF

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Publication number
WO2020107723A1
WO2020107723A1 PCT/CN2019/075611 CN2019075611W WO2020107723A1 WO 2020107723 A1 WO2020107723 A1 WO 2020107723A1 CN 2019075611 W CN2019075611 W CN 2019075611W WO 2020107723 A1 WO2020107723 A1 WO 2020107723A1
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Prior art keywords
metal
layer
metal unit
doped region
unit
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PCT/CN2019/075611
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English (en)
French (fr)
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蔡光育
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武汉华星光电技术有限公司
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Priority to US16/466,657 priority Critical patent/US20200266301A1/en
Publication of WO2020107723A1 publication Critical patent/WO2020107723A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate

Definitions

  • the present application relates to the field of display, in particular to an array substrate and a display panel.
  • a liquid crystal display includes a display panel and a backlight module.
  • the display panel is composed of a color filter substrate, an array substrate, and a liquid crystal layer disposed between the color filter substrate and the array substrate. Its working principle is to control the rotation of the liquid crystal molecules of the liquid crystal layer by applying a driving voltage, and refract the light of the backlight module to generate a picture.
  • Array substrates usually use thin film transistor (Thin Film Transistor, TFT) and other semiconductor devices as switching elements for whether the pixel unit receives image data.
  • TFT Thin Film Transistor
  • thin film transistors need to use semiconductor materials as conductive channels, and light is transmitted in the display panel.
  • the semiconductor material is prone to photoelectric effect when receiving light, and when the semiconductor material in the conductive channel generates photoelectric effect, it will affect the switching characteristics of the thin film transistor. Therefore, a light-shielding layer is provided at the position corresponding to the conductive channel of the thin film transistor in the display panel.
  • the light shielding layer requires a separate process to be prepared, which further increases the production cost of the array substrate.
  • an array substrate including:
  • a first insulating layer provided on the first metal layer
  • a second insulating layer provided on the active layer
  • a second metal layer provided on the second insulating layer
  • the first metal unit is connected to at least one of the second metal unit and the third metal unit, and the first metal unit is disposed opposite to the channel region to realize the channel For light shielding of the region, the second metal unit and the third metal unit are connected to the source doped region and the drain doped region, respectively.
  • the first metal unit is a light-shielding metal
  • the second metal unit is a source metal
  • the third metal unit is a drain metal
  • a first via hole and a second via hole are provided in the first insulating layer, the source doped region is connected to the second metal unit through the first via hole, the The drain doped region is connected to the third metal unit through the second via.
  • the second metal layer includes a gate metal, and the gate metal is disposed opposite to the channel region.
  • the active layer further includes a first lightly doped region and a second lightly doped region, the first lightly doped region is disposed in the channel of the source doped region Between the regions, the second lightly doped region is disposed between the channel region of the drain doped region.
  • the array substrate further includes:
  • a planarization layer provided on the second metal layer
  • a first transparent electrode layer provided on the planarization layer
  • a passivation layer provided on the first transparent electrode layer
  • a second transparent electrode layer provided on the passivation layer.
  • a third via is provided on the array substrate, and the third via penetrates the passivation layer, the planarization layer, the second insulating layer, and the first Insulation;
  • the second transparent electrode layer is connected to the third metal unit through the third via hole.
  • the first transparent electrode layer and the second transparent electrode layer are insulated from each other.
  • the first metal unit, the second metal unit, and the third metal unit are prepared in the same photomask process.
  • preparation materials of the first metal unit, the second metal unit, and the third metal unit are the same.
  • a display panel is also provided.
  • the display panel includes a backlight module and an array substrate.
  • the array substrate includes:
  • a first insulating layer provided on the first metal layer
  • a second insulating layer provided on the active layer
  • a second metal layer provided on the second insulating layer
  • the first metal unit is connected to at least one of the second metal unit and the third metal unit, and the first metal unit is disposed opposite to the channel region to realize the channel For light shielding of the region, the second metal unit and the third metal unit are connected to the source doped region and the drain doped region, respectively.
  • the first metal unit is a light-shielding metal
  • the second metal unit is a source metal
  • the third metal unit is a drain metal
  • a first via and a second via are provided in the first insulating layer, and the source doped region is connected to the second metal unit through the first via, The drain doped region is connected to the third metal unit through the second via hole.
  • the second metal layer includes a gate metal, and the gate metal is disposed opposite to the channel region.
  • the active layer further includes a first lightly doped region and a second lightly doped region, the first lightly doped region is disposed in the channel of the source doped region Between the regions, the second lightly doped region is disposed between the channel region of the drain doped region.
  • it further includes:
  • a planarization layer provided on the second metal layer
  • a first transparent electrode layer provided on the planarization layer
  • a passivation layer provided on the first transparent electrode layer
  • a second transparent electrode layer provided on the passivation layer.
  • a third via is provided on the array substrate, and the third via penetrates the passivation layer, the planarization layer, the second insulating layer, and the first Insulation;
  • the second transparent electrode layer is connected to the third metal unit through the third via hole.
  • the first transparent electrode layer and the second transparent electrode layer are insulated from each other.
  • the first metal unit, the second metal unit, and the third metal unit are prepared in the same photomask process.
  • preparation materials of the first metal unit, the second metal unit, and the third metal unit are the same.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by a first embodiment of this application;
  • FIG. 2 is a schematic structural diagram of an array substrate provided by a second embodiment of this application.
  • FIG. 3 is a schematic structural diagram of an array substrate provided by a third embodiment of the present application.
  • the present application provides a display panel and a manufacturing method thereof to solve the problem of high manufacturing cost of the existing array substrate.
  • FIG. 1 is a schematic structural diagram of an array substrate 100 according to a first embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of the array substrate 100 according to the third embodiment of the present application.
  • an array substrate 100 including a substrate 11, a first metal layer 12, a first insulating layer 13, an active layer 14, a second insulating layer 15, and a second metal layer 16.
  • the substrate 11 is one of a flexible substrate and a rigid substrate.
  • the first metal layer 12 is disposed on the substrate 11.
  • the first metal layer 12 includes a first metal unit 121 in the middle, and second and third metal units 122 and 123 at both ends.
  • the first metal unit 121 is a light-shielding metal used to provide light-shielding protection for the channel region 141 in the active layer 14, the second metal unit 122 is a source metal, and the first The tri-metal unit 123 is a drain metal.
  • the first metal layer 12 is made of molybdenum.
  • the first metal layer 12, the second metal layer 16, and the third metal layer are made of the same material.
  • the first metal layer 12, the second metal layer 16, and the third metal layer are prepared in the same photomask process. Furthermore, the effect of saving one mask process can be achieved.
  • the first metal unit 121 is connected to at least one of the second metal unit 122 and the third metal unit 123. Furthermore, the second metal unit 122 and the third metal unit 123 are connected to each other and short-circuited.
  • the first metal unit 121, the second metal unit 122, and the third metal unit 123 are insulated from each other.
  • the first metal unit 121 is connected to the second metal unit 122 and insulated from the third metal unit 123.
  • the first metal unit 121 is connected to the third metal unit 123 and insulated from the second metal unit 122.
  • the first insulating layer 13 is disposed on the first metal layer 12.
  • the material for preparing the first insulating layer 13 includes at least one of silicon nitride and silicon oxide.
  • the first insulating layer 13 includes a silicon oxide layer and a silicon nitride layer.
  • the active layer 14 is disposed on the first insulating layer 13.
  • the active layer 14 includes an intermediate channel region 141 and source doped regions 142 and drain doped regions 143 disposed at both ends of the channel region 141.
  • the channel region 141 is opposite to the first metal unit 121.
  • the active layer 14 further includes a first lightly doped region 144 and a second lightly doped region 145, the first lightly doped region 144 is disposed in the source doped region 142 Between the channel region 141, the second lightly doped region 145 is disposed between the channel region 141 and the drain doped region 143. The presence of the first lightly doped region 144 and the second lightly doped region 145 can enhance the electrical characteristics of the thin film transistor.
  • the second insulating layer 15 is disposed on the active layer 14.
  • the material of the second insulating layer 15 includes silicon nitride.
  • the second metal layer 16 is disposed on the second insulating layer 15.
  • the second metal layer 16 includes a gate metal.
  • first metal unit 121 and the channel region 141 are oppositely arranged to shield the channel region 141, and the second metal unit 122 and the third metal unit 123 are respectively separated from the source
  • the polar doped region 142 and the drain doped region 143 are connected.
  • the source metal and the drain metal are provided below the active layer 14.
  • the light shielding metal, the source metal, and the drain metal in the array substrate 100 can be integrated in the same film layer, and the polysilicon
  • the layer is connected to the source metal and the drain metal by digging holes in the first insulating layer 13, so that an insulating layer can be omitted, and the effect of saving a light mask can be achieved.
  • the first insulating layer 13 is provided with a first via 131 and a second via 132, and the source doped region 142 passes through the first via 131 and the second metal unit 122 is connected, and the drain doped region 143 is connected to the third metal unit 123 through the second via 132.
  • FIG. 2 is a schematic structural diagram of an array substrate 100 according to a second embodiment of the present application.
  • the array substrate 100 further includes a planarization layer 17, a first transparent electrode layer 18, a passivation layer 19, and a second transparent electrode layer 20 disposed on the second metal layer 16.
  • a third via 21 is provided on the array substrate 100, and the third via 21 penetrates the passivation layer 19, the planarization layer 17, and the second insulating layer 15 And the first insulating layer 13;
  • the second transparent electrode layer 20 is connected to the third metal unit 123 through the third via hole 21.
  • the first transparent electrode layer 18 and the second transparent electrode layer 20 are insulated from each other.
  • a display panel is also provided.
  • the display panel includes a backlight module and an array substrate 100.
  • the array substrate 100 includes:
  • a first insulating layer 13 provided on the first metal layer 12;
  • a second insulating layer 15 provided on the active layer 14;
  • a second metal layer 16 provided on the second insulating layer 15;
  • the first metal unit 121 is connected to at least one of the second metal unit 122 and the third metal unit 123, and the first metal unit 121 and the channel region 141 are oppositely arranged for To shield the channel region 141 from light, the second metal unit 122 and the third metal unit 123 are respectively connected to the source doped region 142 and the drain doped region 143.
  • the first metal unit 121 is a light-shielding metal
  • the second metal unit 122 is a source metal
  • the third metal unit 123 is a drain metal
  • the first insulating layer 13 is provided with a first via 131 and a second via 132, and the source doped region 142 passes through the first via 131 and the second The metal unit 122 is connected, and the drain doped region 143 is connected to the third metal unit 123 through the second via 132.
  • the second metal layer 16 includes a gate metal, and the gate metal is disposed opposite to the channel region 141.
  • the active layer 14 further includes a first lightly doped region 144 and a second lightly doped region 145, the first lightly doped region 144 is disposed in the source doped region 142 Between the channel region 141, the second lightly doped region 145 is disposed between the channel region 141 and the drain doped region 143.
  • the array substrate 100 further includes:
  • a planarization layer 17 provided on the second metal layer 16;
  • a first transparent electrode layer 18 provided on the planarization layer 17;
  • a passivation layer 19 provided on the first transparent electrode layer 18.
  • a third via 21 is provided on the array substrate 100, and the third via 21 penetrates the passivation layer 19, the planarization layer 17, and the second insulating layer 15 And the first insulating layer 13;
  • the second transparent electrode layer 20 is connected to the third metal unit 123 through the third via hole 21.
  • the first transparent electrode layer 18 and the second transparent electrode layer 20 are insulated from each other.
  • the first metal unit 121, the second metal unit 122, and the third metal unit 123 are prepared in the same photomask process.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

本申请提出了一种阵列基板及显示面板。阵列基板包括第一金属层和有源层。第一金属层包括中间的第一金属单元以及两端的第二金属单元和第三金属单元。有源层包括中间的沟道区以及两端的源极掺杂区和漏极掺杂区。其中，第一金属单元与沟道区相对设置，第二金属单元和第三金属单元分别与源极掺杂区和漏极掺杂区连接。

Description

一种阵列基板及显示面板 技术领域
本申请涉及显示领域，特别涉及一种阵列基板及显示面板。
 背景技术
已知，液晶显示器包括显示面板与背光模组。显示面板由一彩膜基板、一阵列基板以及一设置于所述彩膜基板和所述阵列基板之间的液晶层构成。其工作原理是通过施加驱动电压来控制液晶层的液晶分子旋转，将背光模组的光线折射出来产生画面。
阵列基板通常采用薄膜晶体管(Thin Film Transistor，TFT)等半导体器件作为像素单元是否接收图像数据的开关元件。众所周知，薄膜晶体管需要通过半导体材料作为导电沟道，而显示面板中均有光线的传送。然而，半导体材料在接收到光照时容易产生光电效应，当导电沟道内的半导体材料产生光电效应时将会对薄膜晶体管的开关特性产生影响。因此，显示面板中对应薄膜晶体管导电沟道的位置会设置有遮光层。但是遮光层需要一道单独的工艺来制备，进而增加了阵列基板的生产成本。
 技术问题
现有阵列基板的制作成本较高的问题。
 技术解决方案
为实现上述目的，本申请提供的技术方案如下：
根据本申请的一个方面，提供了一种阵列基板，包括:
衬底；
设置于所述衬底上的第一金属层，所述第一金属层包括中间的第一金属单元以及两端的第二金属单元和第三金属单元；
设置于所述第一金属层上的第一绝缘层；
设置于所述第一绝缘层上的有源层，所述有源层包括中间的沟道区以及两端的源极掺杂区和漏极掺杂区；
设置于所述有源层上的第二绝缘层；
设置于所述第二绝缘层上的第二金属层；
其中，所述第一金属单元与所述第二金属单元和所述第三金属单元中的至多一者连接，所述第一金属单元与所述沟道区相对设置用以实现所述沟道区的遮光，所述第二金属单元和所述第三金属单元分别与所述源极掺杂区和所述漏极掺杂区连接。
根据本申请一种实施例，所述第一金属单元为遮光金属，所述第二金属单元为源极金属，所述第三金属单元为漏极金属。
根据本申请一种实施例，所述第一绝缘层内设置有第一过孔和第二过孔，所述源极掺杂区通过第一过孔与所述第二金属单元连接，所述漏极掺杂区通过所述第二过孔与所述第三金属单元连接。
根据本申请一种实施例，所述第二金属层包括栅极金属，所述栅极金属与所述沟道区相对设置。
根据本申请一种实施例，所述有源层还包括第一轻掺杂区和第二轻掺杂区，所述第一轻掺杂区设置于所述源极掺杂区域所述沟道区之间，所述第二轻掺杂区设置于所述漏极掺杂区域所述沟道区之间。
根据本申请一种实施例，所述阵列基板还包括：
设置于所述第二金属层上的平坦化层；
设置于所述平坦化层上的第一透明电极层；
设置于所述第一透明电极层上的钝化层；以及
设置于所述钝化层上的第二透明电极层。
根据本申请一种实施例，所述阵列基板上设置有第三过孔，所述第三过孔贯穿所述钝化层、所述平坦化层、所述第二绝缘层和所述第一绝缘层；
其中，所述第二透明电极层通过所述第三过孔与所述第三金属单元相连。
根据本申请一种实施例，所述第一透明电极层与所述第二透明电极层相互绝缘设置。
根据本申请一种实施例，所述第一金属单元、所述第二金属单元和所述第三金属单元在同一道光罩工艺中制备。
根据本申请一种实施例，所述第一金属单元、所述第二金属单元和所述第三金属单元的制备材料相同。
根据本申请另一个方面，还提供了一种显示面板，所述显示面板包括背光模组和阵列基板，所述阵列基板包括：
衬底；
设置于所述衬底上的第一金属层，所述第一金属层包括中间的第一金属单元以及两端的第二金属单元和第三金属单元；
设置于所述第一金属层上的第一绝缘层；
设置于所述第一绝缘层上的有源层，所述有源层包括中间的沟道区以及两端的源极掺杂区和漏极掺杂区；
设置于所述有源层上的第二绝缘层；
设置于所述第二绝缘层上的第二金属层；
其中，所述第一金属单元与所述第二金属单元和所述第三金属单元中的至多一者连接，所述第一金属单元与所述沟道区相对设置用以实现所述沟道区的遮光，所述第二金属单元和所述第三金属单元分别与所述源极掺杂区和所述漏极掺杂区连接。
根据本申请一种实施例，所述第一金属单元为遮光金属，所述第二金属单元为源极金属，所述第三金属单元为漏极金属。
根据本申请一种实施例，所述第一绝缘层内设置有第一过孔和第二过孔，所述源极掺杂区通过所述第一过孔与所述第二金属单元连接，所述漏极掺杂区通过所述第二过孔与所述第三金属单元连接。
根据本申请一种实施例，所述第二金属层包括栅极金属，所述栅极金属与所述沟道区相对设置。
根据本申请一种实施例，所述有源层还包括第一轻掺杂区和第二轻掺杂区，所述第一轻掺杂区设置于所述源极掺杂区域所述沟道区之间，所述第二轻掺杂区设置于所述漏极掺杂区域所述沟道区之间。
根据本申请一种实施例，还包括：
设置于所述第二金属层上的平坦化层；
设置于所述平坦化层上的第一透明电极层；
设置于所述第一透明电极层上的钝化层；以及
设置于所述钝化层上的第二透明电极层。
根据本申请一种实施例，所述阵列基板上设置有第三过孔，所述第三过孔贯穿所述钝化层、所述平坦化层、所述第二绝缘层和所述第一绝缘层；
其中，所述第二透明电极层通过所述第三过孔与所述第三金属单元相连。
根据本申请一种实施例，所述第一透明电极层与所述第二透明电极层相互绝缘设置。
根据本申请一种实施例，所述第一金属单元、所述第二金属单元和所述第三金属单元在同一道光罩工艺中制备。
根据本申请一种实施例，所述第一金属单元、所述第二金属单元和所述第三金属单元的制备材料相同。
 有益效果
有益效果：本申请通过将遮光金属、源极金属和漏极金属集成在同一道膜层中，不仅能够节省一绝缘层，而且能够减少一道光罩，降低了产品的生产成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请第一实施例提供的阵列基板的结构示意图；
图2为本申请第二实施例提供的阵列基板的结构示意图；
图3为本申请第三实施例提供的阵列基板的俯视结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本申请提供了一种显示面板及其制作方法，以解决现有阵列基板的制作成本较高的问题。
请参阅图1，图1为本申请第一实施例提供的阵列基板100的结构示意图。
请参阅图3，图3为本申请第三实施例提供的阵列基板100的俯视结构示意图。
根据本申请的一个方面，提供了一种阵列基板100，包括衬底11、第一金属层12、第一绝缘层13、有源层14、第二绝缘层15以及第二金属层16。
在一种实施例中，所述衬底11为柔性衬底和刚性衬底中的其中一者。
所述第一金属层12设置于所述衬底11上。所述第一金属层12包括中间的第一金属单元121以及两端的第二金属单元122和第三金属单元123。
在一种实施例中，所述第一金属单元121为用以为所述有源层14中沟道区141提供遮光保护的遮光金属，所述第二金属单元122为源极金属，所述第三金属单元123为漏极金属。
在一种实施例中，所述第一金属层12的制备材料为钼。
在一种实施例中，所述第一金属层12、所述第二金属层16和所述第三金属层的制备材料相同。
在一种实施例中，所述第一金属层12、所述第二金属层16和所述第三金属层在同一道光罩工艺中制备。进而达到节省一道光罩工艺的效果。
在一种实施例中，所述第一金属单元121至多与所述第二金属单元122和第三金属单元123中的其中一者相连。进而防止第二金属单元122与所述第三金属单元123互相连接发生短路。
在一种实施例中，所述第一金属单元121、所述第二金属单元122和所述第三金属单元123之间相互绝缘。
在一种实施例中，所述第一金属单元121与所述第二金属单元122连接并与所述第三金属单元123绝缘。
在一种实施例中，所述第一金属单元121与所述第三金属单元123连接并与所述第二金属单元122绝缘。
所述第一绝缘层13设置在所述第一金属层12上。
在一种实施例中，所述第一绝缘层13的制备材料包括氮化硅和氧化硅中的至少一者。
在一种实施例中，所述第一绝缘层13包括氧化硅层和氮化硅层。
所述有源层14设置在所述第一绝缘层13上。所述有源层14包括中间的沟道区141以及设置在所述沟道区141两端的源极掺杂区142和漏极掺杂区143。
在一种实施例中，所述沟道区141与所述第一金属单元121相对设置。
在一种实施例中，所述有源层14还包括第一轻掺杂区144和第二轻掺杂区145，所述第一轻掺杂区144设置于所述源极掺杂区142域所述沟道区141之间，所述第二轻掺杂区145设置于所述漏极掺杂区143域所述沟道区141之间。所述第一轻掺杂区144和所述第二轻掺杂区145的存在能够增强薄膜晶体管的电学特性。
在一种实施例中，所述第二绝缘层15设置在所述有源层14上。
在一种实施例中，所述第二绝缘层15的材料包括氮化硅。
在一种实施例中，所述第二金属层16设置在所述第二绝缘层15上。
在一种实施例中，所述第二金属层16包括栅极金属。
其中，所述第一金属单元121与所述沟道区141相对设置用以实现所述沟道区141的遮光，所述第二金属单元122和所述第三金属单元123分别于所述源极掺杂区142和所述漏极掺杂区143连接。
本申请将源极金属和漏极金属设置在所述有源层14的下方，通过上述方案能够将阵列基板100中遮光金属和源极金属、漏极金属设置集成在同一膜层中，将多晶硅层通过在第一绝缘层13中挖孔与所述源极金属和所述漏极金属连接，从而能够省掉一层绝缘层，达到省光罩的效果。
在一种实施例中，所述第一绝缘层13内设置有第一过孔131和第二过孔132，所述源极掺杂区142通过第一过孔131与所述第二金属单元122连接，所述漏极掺杂区143通过所述第二过孔132与所述第三金属单元123连接。
请参阅图2，图2为本申请第二实施例提供的阵列基板100的结构示意图。
在一种实施例中，所述阵列基板100还包括设置在所述第二金属层16上的平坦化层17、第一透明电极层18、钝化层19以及第二透明电极层20。
在一种实施例中，所述阵列基板100上设置有第三过孔21，所述第三过孔21贯穿所述钝化层19、所述平坦化层17、所述第二绝缘层15和所述第一绝缘层13；
其中，所述第二透明电极层20通过所述第三过孔21与所述第三金属单元123相连。
在一种实施例中，所述第一透明电极层18与所述第二透明电极层20相互绝缘设置。
根据本发明的另一个方面，还提供了一种显示面板，所述显示面板包括背光模组和阵列基板100，所述阵列基板100包括:
衬底11；
设置于所述衬底11上的第一金属层12，所述第一金属层12包括中间的第一金属单元121以及两端的第二金属单元122和第三金属单元123；
设置于所述第一金属层12上的第一绝缘层13；
设置于所述第一绝缘层13上的有源层14，所述有源层14包括中间的沟道区141以及两端的源极掺杂区142和漏极掺杂区143；
设置于所述有源层14上的第二绝缘层15；
设置于所述第二绝缘层15上的第二金属层16；
其中，所述第一金属单元121与所述第二金属单元122和所述第三金属单元123中的至多一者连接，所述第一金属单元121与所述沟道区141相对设置用以实现所述沟道区141的遮光，所述第二金属单元122和所述第三金属单元123分别与所述源极掺杂区142和所述漏极掺杂区143连接。
在一种实施例中，所述第一金属单元121为遮光金属，所述第二金属单元122为源极金属，所述第三金属单元123为漏极金属。
在一种实施例中，所述第一绝缘层13内设置有第一过孔131和第二过孔132，所述源极掺杂区142通过所述第一过孔131与所述第二金属单元122连接，所述漏极掺杂区143通过所述第二过孔132与所述第三金属单元123连接。
在一种实施例中，所述第二金属层16包括栅极金属，所述栅极金属与所述沟道区141相对设置。
在一种实施例中，所述有源层14还包括第一轻掺杂区144和第二轻掺杂区145，所述第一轻掺杂区144设置于所述源极掺杂区142域所述沟道区141之间，所述第二轻掺杂区145设置于所述漏极掺杂区143域所述沟道区141之间。
在一种实施例中，所述阵列基板100还包括：
设置于所述第二金属层16上的平坦化层17；
设置于所述平坦化层17上的第一透明电极层18；
设置于所述第一透明电极层18上的钝化层19；以及
设置于所述钝化层19上的第二透明电极层20。
在一种实施例中，所述阵列基板100上设置有第三过孔21，所述第三过孔21贯穿所述钝化层19、所述平坦化层17、所述第二绝缘层15和所述第一绝缘层13；
其中，所述第二透明电极层20通过所述第三过孔21与所述第三金属单元123相连。
在一种实施例中，所述第一透明电极层18与所述第二透明电极层20相互绝缘设置。
在一种实施例中，所述第一金属单元121、所述第二金属单元122和所述第三金属单元123在同一道光罩工艺中制备。
有益效果：本申请通过将遮光金属、源极金属和漏极金属集成在同一道膜层中，不仅能够节省一绝缘层，而且能够减少一道光罩，降低了产品的生产成本。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，其包括:
    衬底；
    设置于所述衬底上的第一金属层，所述第一金属层包括中间的第一金属单元以及两端的第二金属单元和第三金属单元；
    设置于所述第一金属层上的第一绝缘层；
    设置于所述第一绝缘层上的有源层，所述有源层包括中间的沟道区以及两端的源极掺杂区和漏极掺杂区；
    设置于所述有源层上的第二绝缘层；
    设置于所述第二绝缘层上的第二金属层；
    其中，所述第一金属单元与所述第二金属单元和所述第三金属单元中的至多一者连接，所述第一金属单元与所述沟道区相对设置用以实现所述沟道区的遮光，所述第二金属单元和所述第三金属单元分别与所述源极掺杂区和所述漏极掺杂区连接。
  2. 根据权利要求1所述的阵列基板，其中，所述第一金属单元为遮光金属，所述第二金属单元为源极金属，所述第三金属单元为漏极金属。
  3. 根据权利要求1所述的阵列基板，其中，所述第一绝缘层内设置有第一过孔和第二过孔，所述源极掺杂区通过所述第一过孔与所述第二金属单元连接，所述漏极掺杂区通过所述第二过孔与所述第三金属单元连接。
  4. 根据权利要求1所述的阵列基板，其中，所述第二金属层包括栅极金属，所述栅极金属与所述沟道区相对设置。
  5. 根据权利要求1所述的阵列基板，其中，所述有源层还包括第一轻掺杂区和第二轻掺杂区，所述第一轻掺杂区设置于所述源极掺杂区域所述沟道区之间，所述第二轻掺杂区设置于所述漏极掺杂区域所述沟道区之间。
  6. 根据权利要求1所述的阵列基板，其中，还包括：
    设置于所述第二金属层上的平坦化层；
    设置于所述平坦化层上的第一透明电极层；
    设置于所述第一透明电极层上的钝化层；以及
    设置于所述钝化层上的第二透明电极层。
  7. 根据权利要求6所述的阵列基板，其中，所述阵列基板上设置有第三过孔，所述第三过孔贯穿所述钝化层、所述平坦化层、所述第二绝缘层和所述第一绝缘层；
    其中，所述第二透明电极层通过所述第三过孔与所述第三金属单元相连。
  8. 根据权利要求7所述的阵列基板，其中，所述第一透明电极层与所述第二透明电极层相互绝缘设置。
  9. 根据权利要求1所述的阵列基板，其中，所述第一金属单元、所述第二金属单元和所述第三金属单元在同一道光罩工艺中制备。
  10. 根据权利要求9所述的阵列基板，其中，所述第一金属单元、所述第二金属单元和所述第三金属单元的制备材料相同。
  11. 一种显示面板，其包括背光模组和阵列基板，所述阵列基板包括：
    衬底；
    设置于所述衬底上的第一金属层，所述第一金属层包括中间的第一金属单元以及两端的第二金属单元和第三金属单元；
    设置于所述第一金属层上的第一绝缘层；
    设置于所述第一绝缘层上的有源层，所述有源层包括中间的沟道区以及两端的源极掺杂区和漏极掺杂区；
    设置于所述有源层上的第二绝缘层；
    设置于所述第二绝缘层上的第二金属层；
    其中，所述第一金属单元与所述第二金属单元和所述第三金属单元中的至多一者连接，所述第一金属单元与所述沟道区相对设置用以实现所述沟道区的遮光，所述第二金属单元和所述第三金属单元分别与所述源极掺杂区和所述漏极掺杂区连接。
  12. 根据权利要求11所述的显示面板，其中，所述第一金属单元为遮光金属，所述第二金属单元为源极金属，所述第三金属单元为漏极金属。
  13. 根据权利要求11所述的显示面板，其中，所述第一绝缘层内设置有第一过孔和第二过孔，所述源极掺杂区通过所述第一过孔与所述第二金属单元连接，所述漏极掺杂区通过所述第二过孔与所述第三金属单元连接。
  14. 根据权利要求11所述的显示面板，其中，所述第二金属层包括栅极金属，所述栅极金属与所述沟道区相对设置。
  15. 根据权利要求11所述的显示面板，其中，所述有源层还包括第一轻掺杂区和第二轻掺杂区，所述第一轻掺杂区设置于所述源极掺杂区域所述沟道区之间，所述第二轻掺杂区设置于所述漏极掺杂区域所述沟道区之间。
  16. 根据权利要求11所述的显示面板，其中，还包括：
    设置于所述第二金属层上的平坦化层；
    设置于所述平坦化层上的第一透明电极层；
    设置于所述第一透明电极层上的钝化层；以及
    设置于所述钝化层上的第二透明电极层。
  17. 根据权利要求16所述的显示面板，其中，所述阵列基板上设置有第三过孔，所述第三过孔贯穿所述钝化层、所述平坦化层、所述第二绝缘层和所述第一绝缘层；
    其中，所述第二透明电极层通过所述第三过孔与所述第三金属单元相连。
  18. 根据权利要求17所述的显示面板，其中，所述第一透明电极层与所述第二透明电极层相互绝缘设置。
  19. 根据权利要求11所述的显示面板，其中，所述第一金属单元、所述第二金属单元和所述第三金属单元在同一道光罩工艺中制备。
  20. 根据权利要求19所述的显示面板，其中，所述第一金属单元、所述第二金属单元和所述第三金属单元的制备材料相同。
PCT/CN2019/075611 2018-11-30 2019-02-20 一种阵列基板及显示面板 WO2020107723A1 (zh)

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