WO2017024744A1 - 显示基板及其制作方法和显示装置 - Google Patents

显示基板及其制作方法和显示装置 Download PDF

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WO2017024744A1
WO2017024744A1 PCT/CN2015/099876 CN2015099876W WO2017024744A1 WO 2017024744 A1 WO2017024744 A1 WO 2017024744A1 CN 2015099876 W CN2015099876 W CN 2015099876W WO 2017024744 A1 WO2017024744 A1 WO 2017024744A1
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electrode
sub
common electrode
pixel
common
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PCT/CN2015/099876
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English (en)
French (fr)
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金熙哲
崔贤植
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京东方科技集团股份有限公司
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Priority to US15/526,289 priority Critical patent/US10790306B2/en
Publication of WO2017024744A1 publication Critical patent/WO2017024744A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • Embodiments of the present invention relate to a display substrate, a method of fabricating the same, and a display device.
  • Liquid crystal display technology has replaced cathode ray tube technology. It has become the mainstream technology in the field of daily display; due to its own advantages, it has become an ideal display device in the market and consumers.
  • stereoscopic display technology is on the rise in the market, so it is increasingly important to solve the technical shortcomings of the stereoscopic display technology and improve the imaging quality (such as reducing color shift, reducing stereo crosstalk, flickering the screen, increasing the viewing angle, etc.).
  • ADSDS liquid crystal display technology has the advantages of high transmittance, large viewing angle, and easy cost reduction. It has become the mainstream technology in the field of high-precision display. The technology is widely used in high-end mobile phone screens, mobile applications, television and other fields.
  • At least one embodiment of the present invention provides a display substrate, a manufacturing method thereof, and a display device for solving the problem of low charging rate in a large-sized display panel.
  • At least one embodiment of the present invention provides a display substrate including a substrate substrate, gate lines arranged on the substrate substrate, data lines, and matrix arrays divided by the gate lines and the data lines a pixel unit, wherein the pixel unit is provided with a thin film transistor, a pixel electrode, and a common electrode; wherein the pixel electrode and the common electrode are insulated from each other, and the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes.
  • the common electrode includes a plurality of strip-shaped sub-common electrodes, and the plurality of strip-shaped sub-pixel electrodes are alternately distributed with the plurality of strip-shaped sub-common electrodes, and each of the sub-pixel electrodes and adjacent thereto
  • the width between the sub-common electrodes is 1-5 ⁇ m.
  • the interval width between the sub-pixel electrode and the sub-common electrode is 1-2 ⁇ m.
  • the common electrode further includes a first connection region for electrically connecting the plurality of strip-shaped sub-common electrodes, the first connection region and the plurality of strip-shaped sub-common electrodes forming a closed region, Distributed around the pixel electrode.
  • the width of the sub-pixel electrode and the sub-common electrode are both 2-10 ⁇ m.
  • the display substrate may further include a common electrode line including a gate, a gate insulating layer, an active layer, a source, and a drain.
  • a common electrode line including a gate, a gate insulating layer, an active layer, a source, and a drain.
  • the gate and the common electrode line are disposed in the same layer above the base substrate; the gate insulating layer is located above the gate and the common electrode line; the active layer is located at the gate insulation Above the layer; the source and drain are above the active layer.
  • the gate electrode and the common electrode line are disposed in the same layer, and can be formed by one process and the same material, which is advantageous for simplifying the manufacturing process of the display substrate, improving production efficiency, and reducing production cost.
  • the common electrode does not overlap the data line in the forward projection direction.
  • the common electrode may be provided with a second connection region; the common electrode overlaps at least partially with the common electrode line in a right projection direction, and the common electrode and the common electrode line pass the second connection
  • the first via between the region and the sub-common electrode line is electrically connected.
  • the display substrate further includes a passivation layer disposed between the layer where the pixel electrode and the common electrode are located and the layer where the thin film transistor is located, and the first via hole passes through the corresponding portion of the second connection region.
  • a passivation layer and the gate insulating layer are disposed between the layer where the pixel electrode and the common electrode are located and the layer where the thin film transistor is located, and the first via hole passes through the corresponding portion of the second connection region.
  • At least one embodiment of the present invention also provides a display device including the display substrate described above.
  • At least one embodiment of the present invention further provides a method of fabricating a display substrate, the method comprising: forming a pattern including a common electrode on a substrate; forming a pixel including the pixel electrode on the substrate including the pattern of the common electrode a pattern; or a pattern including a pixel electrode formed on the substrate, and a pattern including the common electrode formed on the substrate including the pattern of the pixel electrode; wherein the pixel electrode and the common electrode are insulated from each other in a layer,
  • the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes, the common electrode includes a plurality of strip-shaped sub-common electrodes, and the plurality of strip-shaped sub-pixel electrodes alternate with the plurality of strip-shaped sub-common electrodes
  • the distribution width between each of the sub-pixel electrodes and the sub-common electrode adjacent thereto is 1-5 ⁇ m.
  • a first transparent conductive film layer is formed on the base substrate; Depositing a photoresist over the first transparent conductive film layer, forming a first photoresist pattern matching the first electrode in a region where the first electrode is pre-formed by a patterning process; and pre-forming the first electrode by a patterning process Forming a first electrode including a plurality of strip-shaped sub-first electrodes, and a width of the sub-first electrode is smaller than a width of the first photoresist pattern located above the first lithography layer; Forming a second transparent conductive film layer on the substrate of the glue pattern, peeling off the first photoresist pattern and the second transparent conductive film layer directly above the first photoresist pattern to form a plurality of strips a second electrode of the second electrode; wherein the first electrode is a common electrode, the second electrode is a pixel electrode, the sub-first electrode is a sub-common electrode, and the sub-second electrode is a sub-pixel electrode Or the first electrode is a common electrode, the second
  • the interval width between the sub-pixel electrode and the sub-common electrode is 1-2 ⁇ m.
  • the method may further include: forming a pattern including the gate line and the common electrode line on the substrate by using a patterning process; Forming a pattern including a gate insulating layer on a substrate of a pattern of gate lines and a common electrode line; forming a pattern including an active layer on the substrate including the pattern of the gate insulating layer; and a substrate on the pattern including the active layer A pattern including a data line, a source and a drain is formed thereon; and a pattern including a passivation layer is formed on the substrate including the pattern of the data line, the source and the drain.
  • the common electrode formed further includes a first connection region for electrically connecting the plurality of strip-shaped sub-common electrodes, the first connection region and the plurality of strip-shaped sub-common electrodes forming a closed region Surrounding the sub-pixel electrode distribution.
  • the common electrode does not overlap the data line in the forward projection direction.
  • the width of the sub-pixel electrode and the sub-common electrode are both 2-10 ⁇ m.
  • the common electrode may further be provided with a second connection region; the common electrode overlaps at least partially with the common electrode line in a right projection direction, and the common electrode and the common electrode line pass through the first The first via between the second connection region and the common electrode line is electrically connected.
  • 1 is a schematic plan view showing a planar structure of a substrate
  • Figure 2 is a cross-sectional view showing the structure of the substrate shown in Figure 1 along A-A';
  • FIG. 3 is a schematic plan view showing a planar structure of a display substrate according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic cross-sectional view of the display substrate of FIG. 1 taken along B-B';
  • FIG. 5 is a schematic diagram of a planar structure of a display substrate according to Embodiment 2 of the present invention.
  • FIG. 6 is a schematic cross-sectional structural view of a display substrate according to Embodiment 3 of the present invention.
  • FIG. 7 to FIG. 15 are schematic cross-sectional views showing the flow of the method for fabricating the display substrate shown in FIG. 4.
  • the common electrode of the ADS type and the high-grade super-dimension-switching type (HADS) type liquid crystal panel may be composed of a strip-shaped ITO common electrode or a plate-shaped ITO common electrode connected to the entire surface, and the common electrode and the pixel electrode are at least Partial overlap, see Figure 1 and Figure 2.
  • a constant voltage signal is applied to the common electrode, and a thin film transistor (TFT) is turned on, and a different voltage signal is supplied to the pixel electrode through the data line, so that a common electrode and a pixel electrode are generated.
  • TFT thin film transistor
  • the electric field in turn drives the liquid crystal molecules to rotate to achieve image display.
  • the pixel size of the liquid crystal display panel also increases, and the storage capacitance C st between the common electrode and the pixel electrode also increases; but when the storage capacitor C st becomes large, the charging rate is difficult. Guaranteed.
  • TFT Thin Film Transistor
  • increasing the size of the TFT not only reduces the aperture ratio of the pixel, but also increases the coupling capacitance between the gate and the source and the gate and the drain in the corresponding thin film transistor as the TFT size increases. , thereby affecting the performance of the thin film transistor, thereby reducing the picture quality of the display panel.
  • At least one embodiment of the present invention provides a display substrate, a manufacturing method thereof, and a display device for solving the problem of low charging rate in a large-sized display panel.
  • Embodiment 1 of the present invention provides a display substrate, see FIG. 3 and FIG. 4; the display substrate a base substrate 101, a gate line 102 disposed on the base substrate 101, a data line 103, and a pixel unit arranged in a matrix divided by the gate line 102 and the data line 103, the pixel a thin film transistor, a pixel electrode and a common electrode are disposed in the unit; wherein the pixel electrode and the common electrode are insulated from each other, the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes 104, and the common electrode includes a plurality of Strip-shaped sub-common electrodes 105, the plurality of strip-shaped sub-pixel electrodes 104 are alternately distributed with the plurality of strip-shaped sub-common electrodes 105, and each of the sub-pixel electrodes 104 and its adjacent sub-pixels The width between the common electrodes 105 is 1-5 ⁇ m.
  • the display substrate includes a substrate substrate, gate lines arranged on the substrate substrate, data lines, and pixel units sequentially arranged by the gate lines and the data lines
  • a thin film transistor, a pixel electrode, and a common electrode are disposed in the pixel unit.
  • the pixel electrode and the common electrode are provided in the same layer, and are disposed on the same insulating layer and spaced apart from each other.
  • the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes, and the common electrode includes a plurality of strips.
  • the plurality of strip-shaped sub-pixel electrodes are alternately distributed with the plurality of strip-shaped sub-common electrodes, and an interval width between each of the sub-pixel electrodes and a sub-common electrode adjacent thereto is 1-5 ⁇ m.
  • the storage capacitor C st in the pixel unit of the large-size liquid crystal display panel can be reduced, thereby ensuring the size of the thin film transistor without increasing the size of the thin film transistor.
  • the charging rate of the storage capacitor C st can not only improve the aperture ratio of the pixel, but also ensure good performance of the thin film transistor, thereby improving the display quality of the display panel.
  • the common electrode includes a plurality of strip-shaped sub-common electrodes, and the plurality of strip-shaped sub-pixel electrodes and the plurality of strip-shaped sub-pixels
  • the common electrodes are alternately distributed, and the interval width between each of the sub-pixel electrodes and the sub-common electrode adjacent thereto is 1-5 ⁇ m, which can generate a uniform driving electric field when the pixel unit operates to display, thereby driving liquid crystal molecules. Deflection occurs to achieve image realization, further improving the display quality of the liquid crystal display panel.
  • the base substrate may be a glass substrate, a plastic substrate, or the like.
  • the interval width between the sub-pixel electrode 104 and the sub-common electrode 105 is 1-2 ⁇ m.
  • the interval width is controlled within a range of 1-2 ⁇ m, thereby further improving the uniformity of the driving electric field, avoiding display defects caused by uneven distribution of electric field strength in the driving electric field due to excessive spacing, and further improving the display of the liquid crystal display panel. quality.
  • the common electrode may further include a first connection region 116 for electrically connecting the plurality of strip-shaped sub-common electrodes 105, and the first connection region 116 may be
  • the plurality of strip-shaped sub-common electrodes 105 form a closed region or a partially closed region, which is distributed around the pixel electrode 104.
  • the material used for the sub-pixel electrode 104 and the sub-common electrode 105 is the same, and the material for the fabrication may be a transparent conductive material such as indium tin oxide (ITO).
  • the common electrode is distributed around the pixel electrode, and the common electrode and the pixel electrode can respectively receive an externally applied driving voltage through a via hole, which is advantageous for simplifying the manufacturing process and improving the production efficiency.
  • the sub-pixel electrode 104 and the sub-common electrode 105 have a width of 2 to 10 ⁇ m.
  • the widths of the sub-pixel electrode and the sub-common electrode are both 2-10 ⁇ m, and the width range can be fabricated by using an existing fabrication process, and the sub-pixel electrode and the sub-common electrode can be formed.
  • the electric field is uniformly driven, and it is possible to prevent the display line from being further broken due to the excessively small width of the sub-pixel electrode and the sub-common electrode.
  • a common electrode line 106 for transmitting a voltage signal to the common electrode is further disposed in the display substrate.
  • the thin film transistor includes a gate electrode 107, a gate insulating layer 108, an active layer 109, a source 110, and a drain 111 in this order from bottom to top.
  • the thin film crystal is of a bottom gate type, but the present invention is not limited to the specific structure of the thin film transistor, and for example, the thin film transistor may be of a top gate type.
  • the display substrate further includes a passivation layer 112 disposed between the layer where the pixel electrode and the common electrode are located and the layer where the thin film transistor is located.
  • a passivation layer disposed between the layer where the pixel electrode and the common electrode are located and the layer where the thin film transistor is located may be used to protect the thin film transistor from damage, and at the same time, the source and the drain may be a layer where the data line is located and the layer where the common electrode and the pixel electrode are located The insulation is isolated to form a common electrode and a pixel electrode.
  • the structure of the display substrate according to the first embodiment of the present invention includes: the gate electrode 107 and the common electrode line 106 disposed in the same layer above the substrate substrate 101; a gate insulating layer 108 over the layer where the electrode 107 and the common electrode line 106 are located; an active layer 109 over the gate insulating layer 108; the data line 103, the source 110 and the drain located above the active layer 109 a gate 111; a passivation layer 112 over the layer where the data line 103, the source 110 and the drain 111 are located; a pixel electrode and a common electrode above the passivation layer 112.
  • the pixel electrode and the common electrode are insulated from each other, the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes 104, and the common electrode includes a plurality of strip-shaped sub-common electrodes 105.
  • the plurality of strip-shaped sub-pixel electrodes 104 are alternately distributed with the plurality of strip-shaped sub-common electrodes 105, and the interval width between each of the sub-pixel electrodes 104 and the sub-common electrode 105 adjacent thereto is 1 -5 ⁇ m.
  • the gate electrode and the common electrode line are disposed in the same layer, the two can be formed by one process and the same material, which is advantageous for simplifying the manufacturing process of the display substrate, improving production efficiency, and reducing production cost.
  • the common electrode does not overlap the data line 103 in the forward projection direction.
  • the common electrode does not overlap with the data line in the forward projection direction, which can reduce the coupling capacitance in the thin film transistor and improve the electrical characteristics of the thin film transistor.
  • the common electrode may further be provided with a second connection region 113; the common electrode overlaps at least a part of the common electrode line 106 in a right projection direction, the common electrode and the common electrode line
  • the electrical connection is made through the first via 114 between the second connection region 113 and the common electrode line 106.
  • the first via 114 penetrates the gate insulating layer 108 and the passivation layer 112.
  • the display panel further includes a second via 115 disposed through the passivation layer 112, and the sub-pixel electrode 104 is electrically connected to the drain 111 through the second via 115.
  • the second embodiment of the present invention further provides a display substrate.
  • the structure of the display substrate provided by the second embodiment of the present invention is substantially the same as that of the display substrate provided by the first embodiment of the present invention.
  • the difference between the two is that the sub-common electrode 105 and the sub-pixel electrode 104 are distributed in the direction parallel to the gate line 102 in the display substrate provided by the first embodiment of the present invention, and the display base provided in the second embodiment of the present invention
  • the plate neutron common electrode 105 and the sub-pixel electrode 104 are distributed parallel to the direction of the data line 103; the specific structure will not be described herein.
  • the third embodiment of the present invention further provides a display substrate.
  • the structure of the display substrate provided by the third embodiment of the present invention and the structure of the display substrate provided by the first embodiment of the present invention are basically the same.
  • the thin film transistor in the display substrate provided by the first embodiment of the present invention is a bottom gate thin film transistor
  • the thin film transistor in the display substrate provided by the third embodiment of the present invention is a top gate thin film transistor, wherein the source is 110 and a drain 111 are located above the base substrate 101; the active layer 109 is located above a layer where the source 110 and the drain 111 are located; the gate insulating layer 108 is located above the active layer 109
  • the gate electrode 107 and the common electrode line 106 are located above the gate insulating layer 108; the passivation layer 112 is located above the layer where the gate electrode 107 and the common electrode line 106 are located; the sub-pixel electrode 104 and the sub-pixel
  • the common electrode 105 is located above the passivation layer 112.
  • a first via 114' for electrically connecting the sub-common electrode 105 and the common electrode line 106 penetrates the passivation layer 112; for electrically connecting the drain 111 and the sub-pixel
  • a second via 115' of the electrode 105 penetrates the gate insulating layer 108 and the passivation layer 112.
  • Embodiment 4 of the present invention provides a method for fabricating a display substrate, the method comprising: forming a common electrode and a pixel electrode on a substrate. For example, a pattern including a common electrode is formed on a base substrate; a pattern including a pixel electrode is formed on the substrate including the pattern of the common electrode; or a pattern including a pixel electrode is formed on the base substrate, including A pattern including a common electrode is formed on the substrate of the pattern of the pixel electrode; or, the common electrode and the pixel electrode are formed by the same electrode material in the same patterning process.
  • the pixel electrode and the common electrode are insulated from each other, the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes, and the common electrode includes a plurality of strip-shaped sub-common electrodes, and the plurality of strip-shaped sub-children
  • the pixel electrode is alternately distributed with the plurality of strip-shaped sub-common electrodes, and a width between each of the sub-pixel electrodes and a sub-common electrode adjacent thereto is 1-5 ⁇ m.
  • the display substrate produced by the method provided in the fourth embodiment of the present invention includes a pixel electrode and a common electrode disposed in the same layer, the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes, and the common electrode includes a plurality of strips a sub-common electrode, the plurality of strip-shaped sub-pixel electrodes are alternately distributed with the plurality of strip-shaped sub-common electrodes, and an interval between each of the sub-pixel electrodes and a sub-common electrode adjacent thereto The width is 1-5 ⁇ m.
  • the storage capacitor C st in the large-size liquid crystal display panel can be reduced, thereby ensuring the charging rate of the storage capacitor C st without increasing the size of the thin film transistor; Since it is not necessary to increase the size of the thin film transistor, not only the aperture ratio of the pixel can be increased, but also the thin film transistor can be ensured to have good performance, thereby improving the display quality of the display panel.
  • the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes
  • the common electrode includes a plurality of strip-shaped sub-common electrodes
  • the plurality of strip-shaped sub-pixel electrodes and the plurality of strip-shaped sub-commons are alternately distributed, and the interval width between each of the sub-pixel electrodes and the sub-common electrode adjacent thereto is 1-5 ⁇ m, so that a uniform driving electric field can be generated, thereby driving liquid crystal molecules to deflect to realize image realization, further Improve the display quality of the liquid crystal display panel.
  • the step of fabricating the display substrate includes: forming a first transparent conductive film layer on the base substrate; depositing a photoresist over the first transparent conductive film layer, and pre-forming the first electrode by a patterning process Forming a first photoresist pattern matching the first electrode; forming a first electrode including a plurality of strip-shaped sub-first electrodes in a region where the first electrode is pre-formed by a patterning process, and the sub-first The width of the electrode is smaller than the width of the first photoresist pattern located above the second photoresist film layer on the substrate including the first photoresist pattern, and the first photoresist pattern is peeled off and a second transparent conductive film layer directly above the first photoresist pattern to form a second electrode including a plurality of strip-shaped sub-second electrodes.
  • the first electrode is a sub-common electrode
  • the second electrode is a sub-pixel electrode
  • the sub-first electrode is a sub-common electrode
  • the sub-second electrode is a sub-pixel electrode
  • the first The electrode is a sub-pixel electrode
  • the second electrode is a sub-common electrode
  • the sub-first electrode is a sub-pixel electrode
  • the sub-second electrode is a sub-common electrode
  • a photoresist is first deposited over the first transparent conductive film layer, and a first photolithography matching the first electrode is formed in a region where the first electrode is pre-formed by a patterning process.
  • a glue pattern and forming a first electrode including a plurality of strip-shaped sub-first electrodes in a region where the first electrode is pre-formed by a patterning process, and a width of the sub-first electrode is smaller than the first portion located above a width of the photoresist pattern, then forming a second transparent conductive film layer on the substrate including the first photoresist pattern, stripping the first photoresist pattern and directly above the first photoresist pattern a second transparent conductive film layer to form a second electrode including a plurality of strip-shaped sub-second electrodes, and the first electrode and the second electrode formed by the method can effectively reduce the sub-first electrode and the second second The spacing between the electrodes makes the distribution of the driving electric field more uniform.
  • the interval width between the sub-pixel electrode and the sub-common electrode is 1-2 ⁇ m.
  • the interval width between the sub-pixel electrode and the sub-common electrode is set to 1-2 ⁇ m, which can further improve the uniformity of the driving electric field, and avoid the uneven distribution of the electric field intensity in the driving electric field due to the excessive spacing.
  • the display is poor, and the display quality of the liquid crystal display panel is further improved.
  • the method may further include: forming a pattern including the gate line and the common electrode line on the substrate by using a patterning process; Forming a pattern including a gate insulating layer on a substrate of a pattern of gate lines and a common electrode line; forming a pattern including an active layer on the substrate including the pattern of the gate insulating layer; and a substrate on the pattern including the active layer A pattern including a data line, a source and a drain is formed thereon; and a pattern including a passivation layer is formed on the substrate including the pattern of the data line, the source and the drain.
  • the gate electrode and the common electrode line are disposed in the same layer, and can be formed by one process and the same material, which is advantageous for simplifying the manufacturing process of the display substrate, improving production efficiency, and reducing production cost.
  • the common electrode formed further includes a first connection region for electrically connecting the plurality of strip-shaped sub-common electrodes, the first connection region and the The plurality of strip-shaped sub-common electrodes form a closed region that is distributed around the pixel electrode.
  • the common electrode is distributed around the pixel electrode, so that the common electrode and the pixel electrode can respectively receive the driving voltage applied by the external circuit through one via hole, which is advantageous for simplifying the manufacturing process and improving the production efficiency.
  • the common electrode does not overlap the data line in the forward projection direction.
  • the common electrode does not overlap with the data line in the forward projection direction, which can reduce the coupling capacitance in the thin film transistor and improve the electrical characteristics of the thin film transistor.
  • the widths of the sub-pixel electrode and the sub-common electrode are both set to 2 to 10 ⁇ m.
  • the width range can be fabricated by using an existing fabrication process, and between the sub-pixel electrode and the sub-common electrode. A uniform driving electric field is formed, and it is possible to prevent the display line from being further broken due to the excessively small width of the sub-pixel electrode and the sub-common electrode.
  • the common electrode may further be provided with a second connection region 113; the common electrode overlaps at least partially with the common electrode line 106 in a front projection direction, the common electrode and the common electrode line 106 electrically connecting through the first via 114 between the second connection region 113 and the common electrode line 106, the common electrode line 106 providing a drive for the common electrode Dynamic voltage.
  • the method for forming the display substrate specifically includes the following steps.
  • Step 1 referring to FIG. 7, a metal thin film for forming the gate line 102, the gate electrode 107, and the common electrode line 106 is formed (eg, sputtered or coated, etc.) on the base substrate 101; Coating a photoresist on the film; then, exposing the photoresist with a mask provided with a pattern including the gate line 102, the gate 107 and the common electrode line 106; finally, developing and etching to form a gate including the gate The pattern of the pole 107 and the common electrode line 106.
  • the manufacturing process of the film layer formed by the patterning process is the same as that of the substrate, and will not be described in detail hereinafter.
  • Step 2 referring to FIG. 8, a silicon dioxide or silicon nitride layer, gate insulating layer 108 is deposited by plasma enhanced chemical vapor deposition on the substrate including the pattern of the gate electrode 107 and the common electrode line 106. And forming a via hole in a region corresponding to the second connection region overlapping the common electrode line.
  • Step 3 referring to FIG. 9, a pattern including the active layer 109 is formed on the substrate including the gate insulating layer 108; the active layer 109 may be formed of amorphous silicon, polysilicon, or a metal oxide semiconductor material.
  • Step 4 referring to FIG. 10, depositing a metal layer such as molybdenum (Mo), aluminum (Al) or cadmium (Cr) on the substrate including the pattern of the active layer 109, and then forming a data line 103 by a patterning process. , the pattern of the source 110 and the drain 111.
  • a metal layer such as molybdenum (Mo), aluminum (Al) or cadmium (Cr)
  • a passivation layer 112 is formed on the pattern substrate including the data line 103, the source 110, and the drain 111. And forming a via hole penetrating the passivation layer over the via hole corresponding to the step 602 by a patterning process, forming a first through-gate insulating layer and a passivation layer for electrically connecting the common electrode and the common electrode line.
  • the via hole 114; and a second via 115 penetrating the passivation layer is formed in a region where the pixel electrode overlaps the drain, so that the pixel electrode and the drain are electrically connected through the second via 115.
  • Step 6 referring to FIG. 12, a layer of indium tin oxide (ITO) transparent conductive film is deposited on the passivation layer 112 by magnetron sputtering to form a first transparent conductive film layer 61.
  • ITO indium tin oxide
  • Step 7 referring to FIG. 13, depositing a photoresist over the first transparent conductive film layer, and forming a first photoresist pattern 62 matching the pixel electrode in a region where the pixel electrode is pre-formed by a patterning process.
  • Step 8 referring to FIG. 14, forming a pixel electric field in a region where the pixel electrode is pre-formed by a patterning process
  • the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes 104 (see also FIG. 4), and the width of the sub-pixel electrode 104 is smaller than the width of the first photoresist pattern located above the pixel.
  • Step 9 referring to FIG. 15, an indium tin oxide (ITO) transparent conductive film is deposited on the substrate including the first photoresist pattern by magnetron sputtering to form a second transparent conductive film layer 63.
  • ITO indium tin oxide
  • Step 10 peeling off the first photoresist pattern and the second transparent conductive film layer directly above the first photoresist pattern to form a common electrode.
  • the common electrode includes a plurality of strip-shaped sub-common electrodes 105, and the plurality of strip-shaped sub-pixel electrodes 104 are alternately distributed with the plurality of strip-shaped sub-common electrodes 105, and each of the sub-pixel electrodes 104 and The interval between the sub-common electrodes 105 adjacent thereto is 1-5 ⁇ m.
  • the common electrode may be fabricated first, and then the pixel electrode is fabricated.
  • a photoresist is deposited over the first transparent conductive film layer, and a region where the common electrode is pre-formed by a patterning process.
  • a first photoresist pattern 62 matching the common electrode is formed.
  • Forming a common electrode in a region where the common electrode is pre-formed by a patterning process, the common electrode including a plurality of strip-shaped sub-common electrodes 105, and a width of the sub-common electrode 105 is smaller than the first photoresist located above the strip The width of the pattern.
  • the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes 104, and the plurality of strip-shaped sub-pixel electrodes 104 are alternately distributed with the plurality of strip-shaped sub-common electrodes 105, and each of the sub-pixel electrodes 104 and The interval between the sub-common electrodes 105 adjacent thereto is 1-5 ⁇ m.
  • At least one embodiment of the present invention also provides a display device including the above display substrate.
  • an embodiment of the present invention provides a display substrate, a manufacturing method thereof, and a display panel.
  • the display substrate includes a substrate substrate, gate lines arranged on the substrate substrate, data lines, and pixel units arranged in a matrix divided by the gate lines and the data lines, in the pixel unit a thin film transistor, a pixel electrode, and a common electrode are disposed; wherein the pixel electrode and the common electrode are insulated from each other, the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes, and the common electrode includes a plurality of strips Sub-sub-electrode electrodes, the plurality of strip-shaped sub-pixel electrodes are alternately distributed with the plurality of strip-shaped sub-common electrodes, and each of the sub-pixel electrodes and a sub-common electrode adjacent thereto The interval between the widths is 1-5 ⁇ m.
  • the storage capacitor C st in the large-size liquid crystal display panel can be reduced, thereby ensuring the storage capacitor C st without increasing the size of the thin film transistor.
  • the charging rate since it is not necessary to increase the size of the thin film transistor, not only the aperture ratio of the pixel can be improved, but also the thin film transistor can be ensured to have good performance, thereby improving the display quality of the display panel.
  • the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes
  • the common electrode includes a plurality of strip-shaped sub-common electrodes
  • the plurality of strip-shaped sub-pixel electrodes and the plurality of strip-shaped sub-commons are alternately distributed, and the interval width between each of the sub-pixel electrodes and the sub-common electrode adjacent thereto is 1-5 ⁇ m, so that a uniform driving electric field can be generated, thereby driving liquid crystal molecules to deflect to realize image realization, further Improve the display quality of the liquid crystal display panel.

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Abstract

一种显示基板及其制作方法和显示装置，该显示基板包括：衬底基板(101)、在该衬底基板(101)上交叉布置的栅线(102)、数据线(103)以及由该栅线(102)和该数据线(103)划分出的呈矩阵排列的像素单元，该像素单元内设置有薄膜晶体管、像素电极和公共电极；其中，该像素电极和该公共电极同层绝缘设置，该像素电极包括多条条状的子像素电极(104)，该公共电极包括多条条状的子公共电极(105)，该多条条状的子像素电极(104)与该多条条状的子公共电极(105)交替分布，每一条该子像素电极(104)和与之相邻的子公共电极(105)之间的间隔宽度为1-5μm。该显示基板能够解决大尺寸显示面板中充电率较低的问题。

Description

显示基板及其制作方法和显示装置 技术领域
本发明的实施例涉及一种显示基板及其制作方法和显示装置。
背景技术
随着薄膜晶体管液晶显示(Thin Film Transistor Liquid Crystal Display,TFT-LCD)技术的发展和工业技术的进步，液晶显示器件生产成本降低、制造工艺的日益完善，液晶显示技术已经取代了阴极射线管技术显示成为日常显示领域的主流技术；由于其本身所具有的优点,在市场和消费者心中成为理想的显示器件。目前市场上立体显示技术日益兴起，故而解决立体显示技术上的技术缺点，改善成像质量(如减小色偏，降低立体串扰，画面闪烁，增大可视角度等)也日益重要。
高级超维场转换(Advanced Super Dimension Switch，缩写为ADSDS)液晶显示技术具有高透过率，可视角度大，容易降低成本等优点，目前已成为高精尖显示领域的主流技术。该技术被广泛应用于高端手机屏幕，移动应用产品，电视等领域。
发明内容
本发明至少一实施例提供了一种显示基板及其制作方法和显示装置，用以解决大尺寸显示面板中充电率较低的问题。
本发明至少一实施例提供一种显示基板，包括衬底基板、在所述衬底基板上交叉布置的栅线、数据线以及由所述栅线和所述数据线划分出的呈矩阵排列的像素单元，所述像素单元内设置有薄膜晶体管、像素电极和公共电极；其中，所述像素电极和所述公共电极同层绝缘设置，所述像素电极包括多条条状的子像素电极，所述公共电极包括多条条状的子公共电极，所述多条条状的子像素电极与所述多条条状的子公共电极交替分布，每一条所述子像素电极和与之相邻的子公共电极之间的间隔宽度为1-5μm。
例如，所述子像素电极和所述子公共电极之间的间隔宽度为1-2μm。
例如，所述公共电极还包括用于将所述多条条状的子公共电极电连接的第一连接区，所述第一连接区与所述多条条状的子公共电极形成闭合区域，环绕所述像素电极分布。
例如，所述子像素电极和所述子公共电极的宽度均为2-10μm。
例如，所述显示基板还可以包括公共电极线，所述薄膜晶体管包括栅极、栅绝缘层、有源层、源极和漏极。例如，所述栅极和公共电极线同层设置，位于所述衬底基板的上方；所述栅绝缘层位于所述栅极和公共电极线的上方；所述有源层位于所述栅绝缘层的上方；所述源极和漏极位于所述有源层的上方。
本发明至少一实施中栅极和公共电极线同层设置，可以通过一次工艺和相同的材料形成，有利于简化显示基板的制作工艺，提高生产效率，降低生产成本。
例如，所述公共电极在正投影方向上与所述数据线不重叠。
例如，所述公共电极可以设置有第二连接区；所述公共电极在正投影方向上与至少部分与所述公共电极线重叠，所述公共电极与所述公共电极线通过所述第二连接区与所述子公共电极线之间的第一过孔实现电连接。
例如，所述显示基板还包括设置在所述像素电极和公共电极所在层与所述薄膜晶体管所在层之间的钝化层，所述第一过孔穿过所述第二连接区对应的所述钝化层和所述栅绝缘层。
本发明至少一实施例还提供了一种显示装置，所述显示装置包括上述所述的显示基板。
本发明至少一实施例还提供了一种显示基板的制作方法，所述方法包括：在衬底基板上形成包括公共电极的图形；在所述包括公共电极的图形的基板上形成包括像素电极的图形；或者，在衬底基板上形成包括像素电极的图形，在所述包括像素电极的图形的基板上形成包括公共电极的图形；其中，所述像素电极和所述公共电极同层绝缘设置，所述像素电极包括多条条状的子像素电极，所述公共电极包括多条条状的子公共电极，所述多条条状的子像素电极与所述多条条状的子公共电极交替分布，每一条所述子像素电极和与之相邻的子公共电极之间的间隔宽度为1-5μm。
例如，在所述方法中，在所述衬底基板上形成第一透明导电膜层；在所 述第一透明导电膜层上方沉积光刻胶，通过构图工艺在预形成第一电极的区域形成与所述第一电极匹配的第一光刻胶图案；通过构图工艺在预形成第一电极的区域形成包括多个条状的子第一电极的第一电极，且所述子第一电极的宽度小于所述位于其上方的第一光刻胶图案的宽度；在所述包括第一光刻胶图案的基板上形成第二透明导电膜层，剥离所述第一光刻胶图案以及位于所述第一光刻胶图案正上方的第二透明导电膜层，以形成包括多个条状的子第二电极的第二电极；其中，所述第一电极为公共电极，所述第二电极为像素电极，所述子第一电极为子公共电极，所述子第二电极为子像素电极；或者，所述第一电极为像素电极，所述第二电极为公共电极，所述子第一电极为子像素电极，所述子第二电极为子公共电极。
例如，所述子像素电极和所述子公共电极之间的间隔宽度为1-2μm。
例如，在形成包括所述第一电极的图形之前，所述方法还可以包括：在所述衬底基板上采用构图工艺形成包括所述栅线和公共电极线的图形；在所述包括所述栅线和公共电极线的图形的基板上形成包括栅绝缘层的图形；在所述包括栅绝缘层的图形的基板上形成包括有源层的图形；在所述包括有源层的图形的基板上形成包括数据线、源极和漏极的图形；在所述包括数据线、源极和漏极的图形的基板上形成包括钝化层的图形。
例如，形成的所述公共电极还包括用于所述多条条状的子公共电极电连接的第一连接区，所述第一连接区与所述多条条状的子公共电极形成闭合区域，环绕所述子像素电极分布。
例如，所述公共电极在正投影方向上与所述数据线不重叠。
例如，所述子像素电极和所述子公共电极的宽度均为2-10μm。
例如，所述公共电极上还可以设置有第二连接区；所述公共电极在正投影方向上与至少部分与所述公共电极线重叠，所述公共电极与所述公共电极线通过所述第二连接区与所述公共电极线之间的第一过孔实现电连接。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种显示基板的平面结构示意图；
图2为图1中显示基板沿A-A’的剖面结构示意图；
图3为本发明实施例一提供的一种显示基板的平面结构示意图；
图4为图1中显示基板沿B-B’的剖面结构示意图；
图5为本发明实施例二提供的一种显示基板的平面结构示意图；
图6为本发明实施例三提供的一种显示基板的剖面结构示意图；
图7至图15为图4所示的显示基板的制作方法流程剖面示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
ADS型和超高级超维场(HADS，High Advanced Super Dimension Switch)型液晶面板的公共电极可由整面连接的条状ITO公共电极或板状ITO公共电极组成，且所述公共电极与像素电极至少部分重叠，参见图1和图2。在液晶显示面板为显示模式时，对公共电极施加恒定的电压信号，薄膜晶体管(Thin Film Transistor，TFT)导通，通过数据线对像素电极提供不同电压信号，这样公共电极和像素电极之间产生电场进而驱动液晶分子发生旋转，以实现图像显示。随着液晶显示面板尺寸的增大，液晶显示面板的像素尺寸也变大，公共电极与像素电极之间的存储电容Cst也变大；但当存储电容Cst变大时，其充电率难以得到保证。为了提高存储电容Cst的充电率，通常是通过增大薄膜晶体管(Thin Film Transistor，TFT)的尺寸来实现。但是，增大TFT尺寸后不仅会降低像素的开口率，而且当TFT尺寸增大后，相应的薄膜晶体管中的栅极与源极、以及栅极与漏极之间的耦合电容也会变大，从而影响薄膜晶体管的性能，进而降低显示面板的画面质量。
本发明至少一实施例提供了一种显示基板及其制作方法和显示装置，用以解决大尺寸显示面板中充电率较低的问题。
本发明实施例一提供了一种显示基板，参见图3和图4；所述显示基板 包括衬底基板101、在所述衬底基板101上交叉布置的栅线102、数据线103以及由所述栅线102和所述数据线103划分出的呈矩阵排列的像素单元，所述像素单元内设置有薄膜晶体管、像素电极和公共电极；其中，所述像素电极和所述公共电极同层绝缘设置，所述像素电极包括多条条状的子像素电极104，所述公共电极包括多条条状的子公共电极105，所述多条条状的子像素电极104与所述多条条状的子公共电极105交替分布，每一条所述子像素电极104和与之相邻的子公共电极105之间的间隔宽度为1-5μm。
本发明的实施例中，所述显示基板包括衬底基板、在所述衬底基板上交叉布置的栅线、数据线以及由所述栅线和所述数据线划分出的依次排列的像素单元，所述像素单元内设置有薄膜晶体管、像素电极、公共电极。所述像素电极和所述公共电极同层绝缘设置，如设置在同一绝缘层上且彼此间隔开，所述像素电极包括多条条状的子像素电极，所述公共电极包括多条条状的子公共电极，所述多条条状的子像素电极与所述多条条状的子公共电极交替分布，每一条所述子像素电极和与之相邻的子公共电极之间的间隔宽度为1-5μm。
本发明实施中通过将所述像素电极和所述公共电极同层绝缘设置，可以减小大尺寸液晶显示面板的像素单元中的存储电容Cst，从而在不增大薄膜晶体管尺寸的前提下保证存储电容Cst的充电率；由于不需要增大薄膜晶体管的尺寸，因此不但可以提高像素的开口率，还可以保证薄膜晶体管具有良好的性能，从而提高显示面板的显示质量。
此外，由于所述像素电极包括多条条状的子像素电极，所述公共电极包括多条条状的子公共电极，所述多条条状的子像素电极与所述多条条状的子公共电极交替分布，每一条所述子像素电极和与之相邻的子公共电极之间的间隔宽度为1-5μm，可以在像素单元工作以进行显示时刻产生均匀的驱动电场，从而驱动液晶分子发生偏转以实现图像实现，进一步提高液晶显示面板的显示品质。
例如，衬底基板可以为玻璃基板、塑料基板等。
例如，所述子像素电极104和所述子公共电极105之间的间隔宽度为1-2μm。
本发明的一个实施例中，可以将所述子像素电极和所述子公共电极之间 的间隔宽度控制在1-2μm范围内，由此可以进一步提高驱动电场的均匀性，避免因间距过大而造成驱动电场内电场强度分布不均所导致的显示不良，进一步提高液晶显示面板的显示品质。
从图3中还可以看出，所述公共电极还可以包括用于将所述多条条状的子公共电极105电连接的第一连接区116，所述第一连接区116可以与所述多条条状的子公共电极105形成闭合区域或部分闭合区域，环绕所述像素电极104分布。所述子像素电极104和所述子公共电极105所采用的材料制作相同，其制作材料可以为氧化铟锡(ITO)等透明导电材料。
所述公共电极环绕所述像素电极分布，所述公共电极和像素电极均可以分别通过一个过孔接收外部所施加的驱动电压，这有利于简化制作工艺，提高生产效率。
例如，所述子像素电极104和所述子公共电极105的宽度均为2-10μm。
本发明实施例中所述子像素电极和所述子公共电极的宽度均为2-10μm，该宽度范围利用现有制作工艺可以制作，所述子像素电极和所述子公共电极之间可以形成均匀的驱动电场，且可以避免因所述子像素电极和所述子公共电极的宽度过细而断线进一步导致显示不良。
所述显示基板进行工作时，需要对所述公共电极施加恒定的电压信号，由此使得相应的薄膜晶体管导通，并通过数据线对像素电极提供不同电压信号，使得公共电极和像素电极之间产生电场进而驱动液晶分子发生旋转，以实现图像显示。因此，所述显示基板中还设置有为所述公共电极传输电压信号的公共电极线106。
本发明的实施例中，如图4所示，所述薄膜晶体管自下而上依次包括栅极107、栅绝缘层108、有源层109、源极110和漏极111。在该实施例中，薄膜晶体为底栅型的，但是本发明不限制于薄膜晶体管的具体结构，例如该薄膜晶体管可以为顶栅型。
此外，所述显示基板还包括设置在所述像素电极和公共电极所在层与所述薄膜晶体管所在层之间的钝化层112。
所述显示基板中，设置在所述像素电极和公共电极所在层与所述薄膜晶体管所在层之间的钝化层，可用于保护薄膜晶体管免受损坏，同时还可以将所述源极、漏极、数据线所在层与所述公共电极和所述像素电极所在层进行 绝缘隔离，以便形成公共电极和像素电极。
因此，如图4所示，本发明实施例一所述显示基板的结构包括：位于所述衬底基板101的上方的同层设置的所述栅极107和公共电极线106；位于所述栅极107和公共电极线106所在层上方的栅绝缘层108；位于所述栅绝缘层108上方的有源层109；位于所述有源层109上方的所述数据线103、源极110和漏极111；位于所述数据线103、源极110和漏极111所在层上方的钝化层112；位于所述钝化层112上方的像素电极和公共电极。
如图所示，所述像素电极和所述公共电极同层绝缘设置，所述像素电极包括多条条状的子像素电极104，所述公共电极包括多条条状的子公共电极105，所述多条条状的子像素电极104与所述多条条状的子公共电极105交替分布，每一条所述子像素电极104和与之相邻的子公共电极105之间的间隔宽度为1-5μm。
由于所述栅极和公共电极线同层设置，因此二者可以通过一次工艺和相同的材料形成，这有利于简化显示基板的制作工艺，提高生产效率，降低生产成本。
例如，所述公共电极在正投影方向上与所述数据线103不重叠。
本发明实施中，在像素单元中，所述公共电极在正投影方向上与所述数据线不重叠，可以降低薄膜晶体管中的耦合电容，提高薄膜晶体管的电学特性。
例如，参见图4，所述公共电极还可以设置有第二连接区113；所述公共电极在正投影方向上与至少部分所述公共电极线106重叠，所述公共电极与所述公共电极线106通过所述第二连接区113与所述公共电极线106之间的第一过孔114实现电连接。所述第一过孔114贯穿所述栅绝缘层108和钝化层112。此外，所述显示面板还包括设置在像贯穿所述钝化层112的第二过孔115，通过所述第二过孔115使得所述子像素电极104与所述漏极111电连接。
本发明实施例二还提供了一种显示基板，参见图5；本发明实施例二提供的显示基板的结构与本发明实施例一提供的显示基板的结构基本相同。二者不同之处在于，本发明实施例一提供的显示基板中子公共电极105和子像素电极104的平行于栅线102的方向分布，而本发明实施例二提供的显示基 板中子公共电极105和子像素电极104的平行于数据线103的方向分布；具体结构此处不再赘述。
本发明实施例三还提供了一种显示基板，参见图6(其剖面位置与图3相同)；本发明实施例三提供的显示基板的结构与本发明实施例一提供的显示基板的结构基本相同。二者不同之处在于,本发明实施例一提供的显示基板中薄膜晶体管为底栅薄膜晶体管，而本发明实施例三提供的显示基板中薄膜晶体管为顶栅薄膜晶体管，其中，所述源极110和漏极111位于所述衬底基板101上方；所述有源层109位于所述源极110和漏极111所在层的上方；所述栅绝缘层108位于所述有源层109的上方；所述栅极107和公共电极线106位于所述栅绝缘层108的上方；所述钝化层112位于所述栅极107和公共电极线106所在层的上方；所述子像素电极104和子公共电极105位于所述钝化层112的上方。
在该显示面板中，用于电连接所述子公共电极105与公共电极线106的第一过孔114′贯穿所述钝化层112；用于电连接所述漏极111和所述子像素电极105的第二过孔115′贯穿所述栅绝缘层108和所述钝化层112。
本发明实施例四提供了一种显示基板的制作方法，所述方法包括：在衬底基板上形成公共电极和像素电极。例如，在衬底基板上形成包括公共电极的图形；在所述包括公共电极的图形的基板上形成包括像素电极的图形；或者，在衬底基板上形成包括像素电极的图形，在所述包括像素电极的图形的基板上形成包括公共电极的图形；或者，公共电极和像素电极在同一构图工艺中通过相同的电极材料形成。
所述像素电极和所述公共电极同层绝缘设置，所述像素电极包括多条条状的子像素电极，所述公共电极包括多条条状的子公共电极，所述多条条状的子像素电极与所述多条条状的子公共电极交替分布，每一条所述子像素电极和与之相邻的子公共电极之间的间隔宽度为1-5μm。
通过本发明实施例四提供的方法制作的显示基板，包括同层绝缘设置的像素电极和所述公共电极，所述像素电极包括多条条状的子像素电极，所述公共电极包括多条条状的子公共电极，所述多条条状的子像素电极与所述多条条状的子公共电极交替分布，每一条所述子像素电极和与之相邻的子公共电极之间的间隔宽度为1-5μm。通过将所述像素电极和所述公共电极同层绝 缘设置，可以减小大尺寸液晶显示面板中存储电容Cst，从而在不增大薄膜晶体管尺寸的前提下保证存储电容Cst的充电率；由于不需要增大薄膜晶体管的尺寸，因此不但可以提高像素的开口率，还可以保证薄膜晶体管具有良好的性能，从而提高显示面板的显示质量。
此外，所述像素电极包括多条条状的子像素电极，所述公共电极包括多条条状的子公共电极，所述多条条状的子像素电极与所述多条条状的子公共电极交替分布，每一条所述子像素电极和与之相邻的子公共电极之间的间隔宽度为1-5μm，所以可以产生均匀的驱动电场，从而驱动液晶分子发生偏转以实现图像实现，进一步提高液晶显示面板的显示品质。
例如，上述制作显示基板的步骤包括：在所述衬底基板上形成第一透明导电膜层；在所述第一透明导电膜层上方沉积光刻胶，通过构图工艺在预形成第一电极的区域形成与所述第一电极匹配的第一光刻胶图案；通过构图工艺在预形成第一电极的区域形成包括多个条状的子第一电极的第一电极，且所述子第一电极的宽度小于所述位于其上方的第一光刻胶图案的宽度；在所述包括第一光刻胶图案的基板上形成第二透明导电膜层，剥离所述第一光刻胶图案以及位于所述第一光刻胶图案正上方的第二透明导电膜层，以形成包括多个条状的子第二电极的第二电极。
例如，所述第一电极为子公共电极，所述第二电极为子像素电极，所述子第一电极为子公共电极，所述子第二电极为子像素电极；或者，所述第一电极为子像素电极，所述第二电极为子公共电极，所述子第一电极为子像素电极，所述子第二电极为子公共电极。
在本发明一个实施例的方法中，首先在所述第一透明导电膜层上方沉积光刻胶，利用构图工艺在预形成第一电极的区域形成与所述第一电极匹配的第一光刻胶图案，并再次通过构图工艺在预形成第一电极的区域形成包括多个条状的子第一电极的第一电极，且所述子第一电极的宽度小于所述位于其上方的第一光刻胶图案的宽度，然后在所述包括第一光刻胶图案的基板上形成第二透明导电膜层，剥离所述第一光刻胶图案以及位于所述第一光刻胶图案正上方的第二透明导电膜层，以形成包括多个条状的子第二电极的第二电极，通过该方法形成的第一电极和第二电极时，可以有效减小子第一电极和子第二电极之间的间隔宽度，使驱动电场的分布更加均匀。
例如，所述子像素电极和所述子公共电极之间的间隔宽度为1-2μm。
将所述子像素电极和所述子公共电极之间的间隔宽度设置为1-2μm，可进一步提高驱动电场的均匀性，避免因间距过大而造成驱动电场内电场强度分布不均所导致的显示不良，进一步提高液晶显示面板的显示品质。
例如，在形成包括所述第一电极的图形之前，所述方法还可以包括：在所述衬底基板上采用构图工艺形成包括所述栅线和公共电极线的图形；在所述包括所述栅线和公共电极线的图形的基板上形成包括栅绝缘层的图形；在所述包括栅绝缘层的图形的基板上形成包括有源层的图形；在所述包括有源层的图形的基板上形成包括数据线、源极和漏极的图形；在所述包括数据线、源极和漏极的图形的基板上形成包括钝化层的图形。
本发明实施中栅极和公共电极线同层设置，可以通过一次工艺和相同的材料形成，有利于简化显示基板的制作工艺，提高生产效率，降低生产成本。
利用发明实施例四提供的方法形成的显示基板中，形成的所述公共电极还包括用于所述多条条状的子公共电极电连接的第一连接区，所述第一连接区与所述多条条状的子公共电极形成闭合区域，环绕所述像素电极分布。
所述公共电极环绕所述像素电极分布，使得所述公共电极和像素电极均可以分别通过一个过孔接收外部电路所施加的驱动电压，有利于简化制作工艺，提高生产效率。
并且，所述公共电极在正投影方向上与所述数据线不重叠。
本发明实施中所述公共电极在正投影方向上与所述数据线不重叠，可以降低薄膜晶体管中的耦合电容，提高薄膜晶体管的电学特性。
例如，将所述子像素电极和所述子公共电极的宽度均设置为2-10μm。
本发明实施例中所述子像素电极和所述子公共电极的宽度均为2-10μm时，该宽度范围利用现有制作工艺可以制作，所述子像素电极和所述子公共电极之间可以形成均匀的驱动电场，且可以避免因所述子像素电极和所述子公共电极的宽度过细而断线进一步导致显示不良。
进一步的，例如，所述公共电极还可以设置有第二连接区113；所述公共电极在正投影方向上与至少部分与所述公共电极线106重叠，所述公共电极与所述公共电极线106通过所述第二连接区113与所述公共电极线106之间的第一过孔114实现电连接，所述公共电极线106为所述公共电极提供驱 动电压。
以本发明实施例一提供的显示基板为例，形成所述显示基板的方法具体包括如下步骤。
步骤1，参见图7，在所述衬底基板101上形成(如溅射或涂覆等)一层用于形成栅线102、栅极107和公共电极线106的金属薄膜；接着，在金属薄膜上涂覆一层光刻胶；然后，用设置有包括栅线102、栅极107和公共电极线106的图形的掩模板对光刻胶进行曝光；最后经显影、刻蚀后形成包括栅极107和公共电极线106的图形。本实施例显示基板的制作方法中，涉及到通过构图工艺形成的膜层的制作工艺与此相同，此后不再详细赘述。
步骤2，参见图8，在所述包括栅极107和公共电极线106的图形的基板上通过等离子体增强化学气相沉积法沉积二氧化硅或氮化硅层，栅绝缘层108。并在对应于第二连接区与公共电极线重叠的区域形成过孔。
步骤3，参见图9，在包括所述栅绝缘层108的基板上形成包括有源层109的图形；所述有源层109可采用非晶硅、多晶硅或金属氧化物半导体材料形成。
步骤4，参见图10，在所述包括有源层109的图形的基板上沉积钼(Mo)、铝(Al)或镉(Cr)等金属层，然后通过构图工艺处理，形成包括数据线103、源极110和漏极111的图形。
步骤5，参见图11，在所述包括数据线103、源极110和漏极111的图形基板上形成钝化层112。并通过构图工艺在对应于步骤602中形成的过孔的上方形成贯穿该钝化层的过孔，形成贯穿栅绝缘层和钝化层、用于使公共电极与公共电极线电连接的第一过孔114；以及，在像素电极与漏极重叠的区域形成贯穿该钝化层的第二过孔115，用于使得像素电极与漏极通过该第二过孔115电连接。
步骤6，参见图12，在所述钝化层112上使用磁控溅射法沉积一层氧化铟锡(ITO)透明导电薄膜，以形成第一透明导电膜层61。
步骤7，参见图13，在所述第一透明导电膜层上方沉积光刻胶，通过构图工艺在预形成像素电极的区域形成与所述像素电极匹配的第一光刻胶图案62。
步骤8，参见图14，通过构图工艺在预形成像素电极的区域形成像素电 极，所述像素电极包括多条条状的子像素电极104(也参见图4)，且所述子像素电极104的宽度小于所述位于其上方的第一光刻胶图案的宽度。
步骤9，参见图15，在所述包括第一光刻胶图案的基板上使用磁控溅射法沉积一层氧化铟锡(ITO)透明导电薄膜，以形成第二透明导电膜层63。
步骤10，参见图4，剥离所述第一光刻胶图案以及位于所述第一光刻胶图案正上方的第二透明导电膜层，以形成公共电极。所述公共电极包括多条条状的子公共电极105，所述多条条状的子像素电极104与所述多条条状的子公共电极105交替分布，每一条所述子像素电极104和与之相邻的子公共电极105之间的间隔宽度为1-5μm。
此外，在制作显示面板的过程中，还可以先制作公共电极，然后再制作像素电极，例如，在所述第一透明导电膜层上方沉积光刻胶，通过构图工艺在预形成公共电极的区域形成与所述公共电极匹配的第一光刻胶图案62。通过构图工艺在预形成公共电极的区域形成公共电极，所述公共电极包括多条条状的子公共电极105，且所述子公共电极105的宽度小于所述位于其上方的第一光刻胶图案的宽度。在所述包括第一光刻胶图案的基板上使用磁控溅射法沉积一层氧化铟锡ITO透明导电薄膜，以形成第二透明导电膜层，剥离所述第一光刻胶图案以及位于所述第一光刻胶图案正上方的第二透明导电膜层，以形成像素电极。所述像素电极包括多条条状的子像素电极104，所述多条条状的子像素电极104与所述多条条状的子公共电极105交替分布，每一条所述子像素电极104和与之相邻的子公共电极105之间的间隔宽度为1-5μm。
本发明至少一实施例还提供了一种显示装置，所述显示装置包括上述的显示基板。
综上，本发明实施例提供了一种显示基板及其制作方法和显示面板。所述显示基板包括衬底基板、在所述衬底基板上交叉布置的栅线、数据线以及由所述栅线和所述数据线划分出的呈矩阵排列的像素单元，所述像素单元内设置有薄膜晶体管、像素电极、公共电极；其中，所述像素电极和所述公共电极同层绝缘设置，所述像素电极包括多条条状的子像素电极，所述公共电极包括多条条状的子公共电极，所述多条条状的子像素电极与所述多条条状的子公共电极交替分布，每一条所述子像素电极和与之相邻的子公共电极之 间的间隔宽度为1-5μm。
本发明实施中通过将所述像素电极和所述公共电极同层绝缘设置，可以减小大尺寸液晶显示面板中存储电容Cst，从而在不增大薄膜晶体管尺寸的前提下保证存储电容Cst的充电率；由于不需要增大薄膜晶体管的尺寸，因此不但可以提高像素的开口率，还可以保证薄膜晶体管具有良好的性能，从而提高显示面板的显示质量。
此外，所述像素电极包括多条条状的子像素电极，所述公共电极包括多条条状的子公共电极，所述多条条状的子像素电极与所述多条条状的子公共电极交替分布，每一条所述子像素电极和与之相邻的子公共电极之间的间隔宽度为1-5μm，所以可以产生均匀的驱动电场，从而驱动液晶分子发生偏转以实现图像实现，进一步提高液晶显示面板的显示品质。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年8月7日递交的中国专利申请第201510484644.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (18)

  1. 一种显示基板，包括衬底基板、在所述衬底基板上交叉布置的栅线、数据线以及由所述栅线和所述数据线划分出的呈矩阵排列的像素单元，所述像素单元内设置有薄膜晶体管、像素电极和公共电极；
    其中，所述像素电极和所述公共电极同层绝缘设置，所述像素电极包括多条条状的子像素电极，所述公共电极包括多条条状的子公共电极，所述多条条状的子像素电极与所述多条条状的子公共电极交替分布，每一条所述子像素电极和与之相邻的子公共电极之间的间隔宽度为1-5μm。
  2. 如权利要求1所述的显示基板，其中，所述子像素电极和所述子公共电极之间的间隔宽度为1-2μm。
  3. 如权利要求1或2所述的显示基板，其中，所述公共电极还包括用于所述多条条状的子公共电极电连接的第一连接区，所述第一连接区与所述多条条状的子公共电极形成闭合区域，环绕所述像素电极分布。
  4. 如权利要求1-3任一项所述的显示基板，其中，所述子像素电极和所述子公共电极的宽度均为2-10μm。
  5. 如权利要求1-4任一项所述的显示基板，其中，所述显示基板还包括公共电极线，所述薄膜晶体管包括栅极、栅绝缘层、有源层、源极和漏极。
  6. 如权利要求5所述的显示基板，其中，
    所述栅极和公共电极线同层设置，位于所述衬底基板的上方；
    所述栅绝缘层位于所述栅极和公共电极线的上方；
    所述有源层位于所述栅绝缘层的上方；
    所述源极和漏极位于所述有源层的上方。
  7. 如权利要求6所述的显示基板，其中，所述公共电极在正投影方向上与所述数据线不重叠。
  8. 如权利要求7所述的显示基板，其中，所述公共电极上设置有第二连接区；
    所述公共电极在正投影方向上与至少部分与所述公共电极线重叠，所述公共电极与所述公共电极线通过所述第二连接区与所述公共电极线之间的第一过孔实现电连接。
  9. 如权利要求8所述的显示基板，其中，所述显示基板还包括设置在所述像素电极和公共电极所在层与所述薄膜晶体管所在层之间的钝化层，所述第一过孔穿过所述第二连接区对应的所述钝化层和所述栅绝缘层。
  10. 一种显示装置，包括权利要求1-9任一权项所述的显示基板。
  11. 一种显示基板的制作方法，包括：
    在衬底基板上形成包括公共电极的图形；在所述包括公共电极的图形的基板上形成包括像素电极的图形；或者，
    在衬底基板上形成包括像素电极的图形，在所述包括像素电极的图形的基板上形成包括公共电极的图形；
    其中，所述像素电极和所述公共电极同层绝缘设置，所述像素电极包括多条条状的子像素电极，所述公共电极包括多条条状的子公共电极，所述多条条状的子像素电极与所述多条条状的子公共电极交替分布，每一条所述子像素电极和与之相邻的子公共电极之间的间隔宽度为1-5μm。
  12. 如权利要求11所述的方法，其中，在所述衬底基板上形成第一透明导电膜层；
    在所述第一透明导电膜层上方沉积光刻胶，通过构图工艺在预形成第一电极的区域形成与所述第一电极匹配的第一光刻胶图案；
    通过构图工艺在预形成第一电极的区域形成包括多个条状的子第一电极的第一电极，且所述子第一电极的宽度小于所述位于其上方的第一光刻胶图案的宽度；
    在所述包括第一光刻胶图案的基板上形成第二透明导电膜层，剥离所述第一光刻胶图案以及位于所述第一光刻胶图案正上方的部分第二透明导电膜层，以形成包括多个条状的子第二电极的第二电极；
    其中，所述第一电极为公共电极，所述第二电极为像素电极，所述子第一电极为子公共电极，所述子第二电极为子像素电极；或者，所述第一电极为像素电极，所述第二电极为公共电极，所述子第一电极为子像素电极，所述子第二电极为子公共电极。
  13. 如权利要求11或12所述的方法，其中，所述子像素电极和所述子公共电极之间的间隔宽度为1-2μm。
  14. 如权利要求12所述的方法，在形成包括所述第一电极的图形之前， 所述方法还包括：
    在所述衬底基板上采用构图工艺形成包括栅线和公共电极线的图形；
    在所述包括所述栅线和公共电极线的图形的基板上形成包括栅绝缘层的图形；
    在所述包括栅绝缘层的图形的基板上形成包括有源层的图形；
    在所述包括有源层的图形的基板上形成包括数据线、源极和漏极的图形；
    在所述包括数据线、源极和漏极的图形的基板上形成包括钝化层的图形。
  15. 如权利要求11所述的方法，其中，形成的所述公共电极还包括用于将所述多条条状的子公共电极电连接的第一连接区，所述第一连接区与所述多条条状的子公共电极形成闭合区域，环绕所述像素电极分布。
  16. 如权利要求14所述的方法，其中，所述公共电极在正投影方向上与所述数据线不重叠。
  17. 如权利要求11所述的方法，其中，所述子像素电极和所述子公共电极的宽度均为2-10μm。
  18. 如权利要求14所述的方法，其中，所述公共电极上还设置有第二连接区；所述公共电极在正投影方向上与至少部分与所述公共电极线重叠，所述公共电极与所述公共电极线通过所述第二连接区与所述公共电极线之间的第一过孔实现电连接。
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