WO2023065392A1 - 阵列基板和显示面板 - Google Patents

阵列基板和显示面板 Download PDF

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Publication number
WO2023065392A1
WO2023065392A1 PCT/CN2021/127541 CN2021127541W WO2023065392A1 WO 2023065392 A1 WO2023065392 A1 WO 2023065392A1 CN 2021127541 W CN2021127541 W CN 2021127541W WO 2023065392 A1 WO2023065392 A1 WO 2023065392A1
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Prior art keywords
gate
layer
source
array substrate
insulating layer
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PCT/CN2021/127541
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English (en)
French (fr)
Inventor
罗成志
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武汉华星光电技术有限公司
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Priority to US17/618,580 priority Critical patent/US20240258340A1/en
Publication of WO2023065392A1 publication Critical patent/WO2023065392A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a display panel.
  • liquid crystal displays Liquid Crystal Display, LCD
  • LCD liquid crystal display
  • other flat display devices are widely used in mobile phones, televisions, personal Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become the mainstream of display devices.
  • Thin film transistor is the main driving element in the LCD display device, which is directly related to the development direction of the high-performance flat panel display device.
  • the TFT used in the display device needs to consider various factors such as uniformity, leakage current, effective driving length, area efficiency, and hysteresis. According to different active layer materials, TFT is divided into amorphous silicon (a-Si) TFT, low temperature polysilicon (Low Temperature Poly-silicon, LTPS) TFT, and metal oxide (Metal oxide) TFT. Oxide) TFT.
  • LTPS TFT has the advantages of high mobility, small size, fast charging and switching speed, etc., and has a good effect when used for gate driving; while metal oxide TFT has the advantages of good uniformity and low leakage current, which can be used for Display pixel driver.
  • hybrid TFT that uses LTPS TFT as gate driver and metal oxide TFT as display pixel driver can be prepared, which can not only increase the driving current in the LCD gate driver circuit, but also reduce the leakage of LCD display pixel drive. current.
  • Commonly used hybrid TFTs include LTPS and Indium Gallium Zinc Oxide (Indium Gallium Zinc Oxide) Gallium Zinc Oxide, IGZO) TFT. Since the carrier mobility of IGZO is much lower than that of LTPS, in order to ensure the pixel charging rate, the size of IGZO TFT needs to be increased, but this design will bring about problems such as reduced aperture ratio, and also limit the application of high-end products such as high-resolution LCDs. develop.
  • the present application provides an array substrate and a display panel, which can reduce the projected area of the first thin film transistor in a direction perpendicular to the array substrate, which is conducive to improving the aperture ratio of the display panel, thereby facilitating the development of high-resolution display products.
  • the present application provides an array substrate, including a first thin film transistor with a vertical structure
  • the first thin film transistor includes:
  • the interlayer insulating layer covering at least the first source;
  • the interlayer insulating layer is provided with a through hole penetrating through the interlayer insulating layer and exposing at least part of the first source;
  • a first gate embedded in the interlayer insulating layer and located at least on one side of the through hole
  • a first drain located on a side of the interlayer insulating layer away from the first source
  • the first active layer is at least partially located in the through hole, and is electrically connected to the first source and the first drain respectively.
  • the first active layer is located on the sidewall and the bottom of the through hole, and extends to a side of the interlayer insulating layer away from the first source.
  • the first gate is arranged around the first active layer on the sidewall of the through hole.
  • a gate opening is provided on the first gate; the through hole is nested in the gate opening;
  • a projection of the gate opening in a direction perpendicular to the interlayer insulating layer and a projection of the through hole in a direction perpendicular to the interlayer insulating layer are circular.
  • the first drain is provided with a drain opening corresponding to the through hole, and the first drain at least partially covers the The first active layer on one side of the first source.
  • the interlayer insulating layer includes a silicon nitride layer and a silicon oxide layer stacked sequentially from bottom to top; the first gate is located on the silicon nitride layer, and the The silicon oxide layer covers the first grid.
  • the material of the first active layer includes metal oxide.
  • the array substrate includes a display area and a non-display area, the first thin film transistor is located in the display area; the array substrate also includes a second thin film located in the non-display area transistor;
  • the second thin film transistor includes a second active layer, a second gate, a second source, and a second drain; wherein, the second gate is set on the same layer as the first source, and the The second source, the second drain and the first drain are arranged in the same layer.
  • the second active layer is disposed corresponding to the second gate; the material of the second active layer includes low temperature polysilicon.
  • the array substrate further includes a substrate, a buffer layer on the substrate, and a gate between the second active layer and the second gate Insulation;
  • the second active layer is located on the buffer layer and is disposed corresponding to the second gate, and the first source is located on the gate insulating layer.
  • the present application further provides a display panel, including an array substrate and an opposite substrate disposed opposite to the array substrate;
  • the array substrate includes a first thin film transistor with a vertical structure
  • the first thin film transistor includes:
  • the interlayer insulating layer covering at least the first source;
  • the interlayer insulating layer is provided with a through hole penetrating through the interlayer insulating layer and exposing at least part of the first source;
  • a first gate embedded in the interlayer insulating layer and located at least on one side of the through hole
  • a first drain located on a side of the interlayer insulating layer away from the first source
  • the first active layer is at least partially located in the through hole, and is electrically connected to the first source and the first drain respectively.
  • the first active layer is located on the sidewall and the bottom of the through hole, and extends to a side of the interlayer insulating layer away from the first source.
  • the first gate is disposed around the first active layer on the sidewall of the through hole.
  • a gate opening is provided on the first gate; the through hole is nested in the gate opening;
  • a projection of the gate opening in a direction perpendicular to the interlayer insulating layer and a projection of the through hole in a direction perpendicular to the interlayer insulating layer are circular.
  • the first drain is provided with a drain opening corresponding to the through hole, and the first drain at least partially covers the The first active layer on one side of the first source.
  • the interlayer insulating layer includes a silicon nitride layer and a silicon oxide layer stacked sequentially from bottom to top; the first gate is located on the silicon nitride layer, and the The silicon oxide layer covers the first grid.
  • the material of the first active layer includes metal oxide.
  • the array substrate includes a display area and a non-display area, the first thin film transistor is located in the display area; the array substrate also includes a second thin film located in the non-display area transistor;
  • the second thin film transistor includes a second active layer, a second gate, a second source, and a second drain; wherein, the second gate is set on the same layer as the first source, and the The second source, the second drain and the first drain are arranged in the same layer.
  • the second active layer is disposed corresponding to the second gate; the material of the second active layer includes low temperature polysilicon.
  • the array substrate further includes a substrate, a buffer layer on the substrate, and a gate between the second active layer and the second gate Insulation;
  • the second active layer is located on the buffer layer and is disposed corresponding to the second gate, and the first source is located on the gate insulating layer.
  • the first thin film transistor has a vertical structure, specifically, the first source, the first active layer and the first drain of the first thin film transistor are in the Arranged in sequence in a direction perpendicular to the array substrate, the first gate is embedded in the interlayer insulating layer, and the first active layer of the first thin film transistor is respectively connected to the first source and the first source through a through hole penetrating the interlayer insulating layer.
  • the first drain is electrically connected so that the channel length of the first thin film transistor is equal to the thickness of the first gate, and the channel width of the first thin film transistor is positively related to the aperture of the through hole.
  • This design can ensure that the first thin film Reducing the projected area of the first thin film transistor in the direction perpendicular to the array substrate on the basis of higher mobility of the transistor can effectively increase the aperture ratio of the display panel, thereby facilitating the development of high-resolution display products.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram after forming a silicon nitride layer in the process of fabricating an array substrate in the embodiment of the present application.
  • FIG. 3 is a schematic diagram of the structure after forming the first gate in the process of fabricating the array substrate in the embodiment of the present application.
  • FIG. 4 is a schematic diagram of the top view positional relationship between the first gate and the first source in FIG. 3 .
  • FIG. 5 is a schematic diagram of the structure after the first through hole is formed in the process of fabricating the array substrate in the embodiment of the present application.
  • FIG. 6 is a schematic diagram of the structure after forming the first active layer in the process of fabricating the array substrate in the embodiment of the present application.
  • FIG. 7 is a schematic diagram of the structure after forming the first drain in the process of fabricating the array substrate in the embodiment of the present application.
  • FIG. 8 is a schematic structural diagram after forming a transparent electrode layer in the process of fabricating an array substrate in an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of said features.
  • “plurality” means two or more, unless otherwise specifically defined.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected, or electrically connected, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction of two components relation. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific situations.
  • a first feature being "on” or “under” a second feature may include direct contact between the first and second features, and may also include the first and second features Not in direct contact but through another characteristic contact between them.
  • “above”, “above” and “above” the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature.
  • “Below”, “beneath” and “under” the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.
  • an embodiment of the present application provides an array substrate 1, the array substrate 1 includes a first thin film transistor 2 with a vertical structure; specifically, the first thin film transistor 2 includes a first source 3, an interlayer insulating layer 4. The first gate 5 , the first drain 6 , and the first active layer 7 .
  • the interlayer insulating layer 4 covers at least the first source electrode 3, and the interlayer insulating layer 4 is provided with a through hole penetrating through the interlayer insulating layer 4 and exposing at least part of the first source electrode 3 (that is, the first via hole 8); the first gate 5 is embedded in the interlayer insulating layer 4, and is located at least on one side of the through hole; the first drain 6 is located on the side of the interlayer insulating layer 4 away from the first source 3; the second An active layer 7 is at least partially located in the through hole, and is electrically connected to the first source 3 and the first drain 6 respectively.
  • the through hole penetrating through the interlayer insulating layer 4 and exposing at least part of the first source electrode 3 is the first through hole 8 .
  • the first active layer 7 is located on the sidewall and bottom of the first through hole 8 and extends to a side of the interlayer insulating layer 4 away from the first source 3 .
  • the first gate 5 is disposed around the first active layer 7 on the sidewall of the first through hole 8 .
  • the first drain 6 is provided with a drain opening 9 corresponding to the first through hole 8 , and at least partially covers the first active layer 7 on the side of the interlayer insulating layer 4 away from the first source 3 .
  • the projection of the first through hole 8 in the direction perpendicular to the array substrate 1 is circular.
  • the projection shape of the first through hole 8 in the direction perpendicular to the array substrate 1 is not limited thereto.
  • a circle is taken as an example for illustration.
  • the first gate 5 is provided with a gate opening 10
  • the first through hole 8 is nested in the gate opening 10, so that the first gate 5 surrounds the sidewall of the first through hole 8.
  • the first active layer 7 is provided.
  • the gate opening 10 may be circular, but of course it is not limited thereto.
  • the channel length of the first active layer 7 in the embodiment of the present application is equal to the thickness of the first gate 5, and the channel width of the first active layer 7 is equal to the first Perimeter of the through hole 8. Since the active layer in the conventional thin film transistor structure is usually arranged in the same plane, its channel length is equal to the width of the gate electrode arranged opposite to the active layer, and its channel width is equal to the length of the active layer.
  • the projected area of the first thin film transistor 2 provided in the embodiment of the present application in the direction perpendicular to the array substrate 1 is smaller, and when the first thin film transistor 2 is arranged in the display area, it can effectively
  • the improved aperture ratio is conducive to the development of high-resolution products.
  • the material of the first gate 5 includes any one of molybdenum (Mo), aluminum (Al) and titanium (Ti), or an alloy of Mo, Al and Ti, or a laminate composed of Mo, Al and Ti structure.
  • the thickness of the first grid 5 ranges from 0.5 ⁇ m to 5 ⁇ m; and the diameter of the gate opening 10 of the first grid 5 ranges from 1 ⁇ m to 10 ⁇ m.
  • the diameter of the first through hole 8 penetrating the interlayer insulating layer 4 is 0.2 micron to 1 micron smaller than the diameter of the gate opening 10 of the first gate 5 .
  • the interlayer insulating layer 4 includes a silicon nitride layer 11 and a silicon oxide layer 12 stacked in sequence from bottom to top.
  • the first gate 5 is located on the silicon nitride layer 11 , and the silicon oxide layer 12 covers the first gate 5 , so that the first gate 5 is completely covered by the silicon nitride layer 11 and the silicon oxide layer 12 .
  • the first drain 6 is annular. It can be understood that the first active layer 7 located on the side of the interlayer insulating layer 4 away from the first source 3 is also annular, and the first drain 6 is located on the side of the interlayer insulating layer 4 away from the first source 3 .
  • the first active layer 7 on the side corresponds to the electrical connection.
  • the array substrate 1 includes a display area 13 and a non-display area 14, and the first thin film transistor 2 is located in the display area 13 for driving display pixels.
  • the array substrate 1 also includes a second thin film transistor 15 located in the non-display area 14 for gate driving.
  • the second thin film transistor 15 includes a second active layer 16, a second gate 17, a second source 18 and a second drain 19; wherein, the second gate 17 and the first source 3 are arranged in the same layer , and the second source 18 , the second drain 19 and the first drain 6 are arranged in the same layer.
  • the material of the first active layer 7 includes metal oxide, such as indium gallium zinc oxide; the material of the second active layer 16 includes low temperature polysilicon.
  • the array substrate 1 provided in the embodiment of the present application uses low-temperature polysilicon thin film transistors as gate drivers and metal oxide thin film transistors as display pixel drivers, which can not only increase the drive current in the gate drive circuit of the display panel, but also reduce the Leakage current when the display pixel is driven.
  • the second active layer 16 includes a polysilicon region 20, N-type lightly doped regions 21 located on both sides of the polysilicon region 20, and N-type lightly doped regions 21 located on the side away from the polysilicon region 20 N-type heavily doped regions 22; the second source 18 and the second drain 19 are respectively connected to the two N-type heavily doped regions 22.
  • the specific structure of the second active layer 16 is not limited thereto.
  • the array substrate 1 further includes a substrate 23, a buffer layer 24 located on the substrate 23, a gate insulating layer 25 located between the second active layer 16 and the second gate 17, and sequentially located on the first The passivation layer, the flat layer 27 and the transparent electrode layer on the interlayer insulating layer 4 of the drain electrode 6 .
  • the substrate 23 may be a glass substrate, but of course it is not limited thereto.
  • the second active layer 16 is located on the buffer layer 24 and is disposed corresponding to the second gate 17 ; the first source 3 is located on the gate insulating layer 25 .
  • the array substrate 1 may further include a touch electrode 26 disposed on the same layer as the first drain electrode 6;
  • the passivation layer includes a first passivation layer 28 and a second passivation layer 29, and the transparent electrode layer includes The first transparent electrode layer 30 and the second transparent electrode layer 31;
  • the first passivation layer 28 is located on the interlayer insulating layer 4 on which the first drain electrode 6 is formed, the planar layer 27 is located on the first passivation layer 28, and the first The transparent electrode layer 30 is located on the planar layer 27
  • the second passivation layer 29 is located on the first transparent electrode layer 30 and the planar layer 27
  • the second transparent electrode layer 31 is located on the second passivation layer 29 .
  • the first transparent electrode layer 30 includes a plurality of bottom transparent electrodes
  • the second transparent electrode layer 31 includes a plurality of top transparent electrodes.
  • part of the top transparent electrode is electrically connected to the first drain 6 through the through hole penetrating the first passivation layer 28, the flat layer 27 and the second passivation layer 29, so as to realize the display function; another part of the top transparent electrode passes through the hole
  • the through hole of the second passivation layer 29 is electrically connected to at least part of the bottom transparent electrode, and this part of the top transparent electrode also passes through the through hole of the first passivation layer 28, the planar layer 27 and the second passivation layer 29 to connect with the touch sensor.
  • the electrodes 26 are electrically connected to realize the touch function.
  • a buffer layer 24, a second active layer 16, and a gate insulating layer 25 are sequentially formed on a substrate 23; then a first metal layer is deposited on the gate insulating layer 25, and the first metal The layer is patterned to form the first source 3 located in the display area 13 and the second gate 17 located in the non-display area 14 and corresponding to the second active layer 16; and then the first source 3 is formed A silicon nitride layer 11 is deposited on the gate insulating layer 25 of the second gate 17 .
  • a second metal layer is deposited, and the second metal layer is patterned to form a first gate 5 with a gate opening 10, wherein the gate opening 10 is disposed corresponding to the first source 3 , and the orthographic projection of the gate opening 10 on the substrate 23 covers at least part of the orthographic projection of the first source 3 on the substrate 23 .
  • a silicon oxide layer 12 is deposited on the silicon nitride layer 11 formed with the first gate 5, wherein the silicon nitride layer 11 and the silicon oxide layer 12 together form an interlayer insulation Layer 4; and then open the interlayer insulating layer 4 to form the first through hole 8 located in the display area 13 and expose at least part of the first source electrode 3 and the second active layer located in the non-display area 14 and respectively exposed The second through hole 32 and the third through hole 33 of the two N-type heavily doped regions 22 of 16.
  • a metal oxide layer is deposited on the basis of the previous step, and the metal oxide layer is patterned to form the sidewall and bottom of the first through hole 8 and extend to the silicon oxide layer 12 away from the first through hole.
  • a third metal layer is deposited, and the third metal layer is patterned to form the first drain 6 in the display area 13 and the second source in the non-display area 14 pole 18 and second drain 19; wherein, the first drain 6 partially covers the first active layer 7 on the side of the silicon oxide layer 12 away from the first source 3, and the first drain 6 is provided with The drain opening 9 corresponding to the first through hole 8; the second source 18 and the second drain 19 respectively pass through the second through hole 32 and the third through hole 33 and the two N-type holes of the second active layer 16
  • the heavily doped region 22 is electrically connected.
  • the first passivation layer 28, the flat layer 27, the first transparent electrode layer 30, the second passivation layer 29 and the second transparent electrode layer 31 are sequentially completed, wherein the flat The layer 27 will be filled in the first through hole 8 to ensure the flatness of the film layer.
  • the first thin film transistor 2 has a vertical structure, specifically, the first source 3 , the first active layer 7 and the first drain 6 of the first thin film transistor 2 are arranged in a direction perpendicular to the array substrate 1
  • the first gate 5 is embedded in the interlayer insulating layer 4, and the first active layer 7 of the first thin film transistor 2 is respectively connected to the first source 3 and the first source 7 through the through hole penetrating the interlayer insulating layer 4.
  • the first drain 6 is electrically connected so that the channel length of the first thin film transistor 2 is equal to the thickness of the first gate 5, and the channel width of the first thin film transistor 2 is positively related to the aperture of the through hole, for example, the channel width It is equal to the perimeter of the through hole; this design can reduce the projected area of the first thin film transistor 2 in the direction perpendicular to the array substrate 1 on the basis of ensuring the high mobility of the first thin film transistor 2, and can effectively improve the display panel. Aperture ratio, which is conducive to the development of high-resolution display products.
  • first thin film transistor 2 provided in this application can also be used with other transistors with a structure different from that of the second thin film transistor 15, or that the structure of the second thin film transistor 15 on the array substrate provided in this application is not limited to this application.
  • the present application does not limit the materials of the first active layer and the second active layer.
  • the embodiment of the present application further provides a display panel 34 , including the array substrate 1 in the above embodiments and an opposite substrate 35 disposed opposite to the array substrate 1 .
  • the opposite substrate 35 includes a color filter substrate
  • the display panel 34 further includes a liquid crystal layer disposed between the array substrate 1 and the opposite substrate 35 .
  • the first thin film transistor 2 has a vertical structure, which can reduce the projected area of the first thin film transistor 2 in the direction perpendicular to the array substrate 1 on the basis of ensuring high mobility, and can effectively improve the performance of the display panel. 34 aperture ratio, which is conducive to the development of high-resolution display panel 34.

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Abstract

公开一种阵列基板和显示面板，阵列基板包括第一薄膜晶体管；第一薄膜晶体管包括第一源极、至少覆盖在第一源极上的层间绝缘层；贯穿层间绝缘层且裸露出至少部分第一源极的通孔、包埋于层间绝缘层中的第一栅极、位于层间绝缘层远离第一源极的一侧的第一漏极、以及通过通孔分别与第一源极和第一漏极电连接的第一有源层。

Description

阵列基板和显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板和显示面板。
 背景技术
随着显示技术的发展，液晶显示器( Liquid Crystal Display，LCD )等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
薄膜晶体管(Thin Film Transistor，TFT)是LCD显示装置中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。显示装置所用TFT需要考虑均一性、漏电流、有效驱动长度、面积效率、及滞后作用等多方面的因素。依据有源层材料的不同，TFT分为非晶硅(a-Si) TFT、低温多晶硅(Low Temperature Poly-silicon，LTPS) TFT、及金属氧化物(Metal Oxide) TFT。其中LTPS TFT具有迁移率高，尺寸较小，充电快开关速度快等优点，用于栅极驱动时具有很好的效果；而金属氧化物TFT具有均一性良好及漏电流低的优点，可用于显示像素驱动。
因此，可以制备一种用LTPS TFT做栅极驱动和用金属氧化物TFT做显示像素驱动的混合TFT，这样既能提高LCD栅极驱动电路中的驱动电流，并且降低LCD显示像素驱动时的漏电流。常用的混合TFT有LTPS与铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO) TFT。由于IGZO的载流子迁移率远远低于LTPS，为了保证像素充电率，需要增加IGZO TFT的尺寸，但此设计会带来开口率降低等问题，也限制了高分辨率LCD等高端产品的开发。
 技术问题
本申请提供一种阵列基板和显示面板，可以减小第一薄膜晶体管在垂直于阵列基板方向上的投影面积，有利于提高显示面板的开口率，从而有利于开发高分辨率的显示产品。
 技术解决方案
第一方面，本申请提供一种阵列基板，包括垂直结构的第一薄膜晶体管；
所述第一薄膜晶体管包括：
第一源极；
层间绝缘层，至少覆盖在所述第一源极上；所述层间绝缘层上设有贯穿所述层间绝缘层且裸露出至少部分所述第一源极的通孔；
第一栅极，包埋于所述层间绝缘层中，且至少位于所述通孔的一侧；
第一漏极，位于所述层间绝缘层远离所述第一源极的一侧；以及
第一有源层，至少部分位于所述通孔内，且分别与所述第一源极和所述第一漏极电连接。
在本申请所提供的阵列基板中，所述第一有源层位于所述通孔的侧壁和底部，且延伸至所述层间绝缘层远离所述第一源极的一侧。
在本申请所提供的阵列基板中，所述第一栅极围绕位于所述通孔的侧壁上的第一有源层设置。
在本申请所提供的阵列基板中，所述第一栅极上设有栅极开口；所述通孔嵌套在所述栅极开口中；
所述栅极开口在垂直于所述层间绝缘层方向上的投影和所述通孔在垂直于所述层间绝缘层方向上的投影为圆形。
在本申请所提供的阵列基板中，所述第一漏极上设有与所述通孔对应设置的漏极开口，且所述第一漏极至少部分覆盖位于所述层间绝缘层远离所述第一源极的一侧的第一有源层。
在本申请所提供的阵列基板中，所述层间绝缘层包括由下至上依次层叠设置的氮化硅层和氧化硅层；所述第一栅极位于所述氮化硅层上，且所述氧化硅层覆盖在所述第一栅极上。
在本申请所提供的阵列基板中，所述第一有源层的材料包括金属氧化物。
在本申请所提供的阵列基板中，所述阵列基板包括显示区和非显示区，所述第一薄膜晶体管位于所述显示区；所述阵列基板还包括位于所述非显示区的第二薄膜晶体管；
所述第二薄膜晶体管包括第二有源层、第二栅极、第二源极和第二漏极；其中，所述第二栅极与所述第一源极同层设置，且所述第二源极、所述第二漏极和所述第一漏极同层设置。
在本申请所提供的阵列基板中，所述第二有源层与所述第二栅极对应设置；所述第二有源层的材料包括低温多晶硅。
在本申请所提供的阵列基板中，所述阵列基板还包括衬底、位于所述衬底上的缓冲层、以及位于所述第二有源层和所述第二栅极之间的栅极绝缘层；
其中，所述第二有源层位于所述缓冲层上且与所述第二栅极对应设置，且所述第一源极位于所述栅极绝缘层上。
第二方面，本申请还提供一种显示面板，包括阵列基板和与所述阵列基板相对设置的对置基板；
所述阵列基板包括垂直结构的第一薄膜晶体管；
所述第一薄膜晶体管包括：
第一源极；
层间绝缘层，至少覆盖在所述第一源极上；所述层间绝缘层上设有贯穿所述层间绝缘层且裸露出至少部分所述第一源极的通孔；
第一栅极，包埋于所述层间绝缘层中，且至少位于所述通孔的一侧；
第一漏极，位于所述层间绝缘层远离所述第一源极的一侧；以及
第一有源层，至少部分位于所述通孔内，且分别与所述第一源极和所述第一漏极电连接。
在本申请所提供的显示面板中，所述第一有源层位于所述通孔的侧壁和底部，且延伸至所述层间绝缘层远离所述第一源极的一侧。
在本申请所提供的显示面板中，所述第一栅极围绕位于所述通孔的侧壁上的第一有源层设置。
在本申请所提供的显示面板中，所述第一栅极上设有栅极开口；所述通孔嵌套在所述栅极开口中；
所述栅极开口在垂直于所述层间绝缘层方向上的投影和所述通孔在垂直于所述层间绝缘层方向上的投影为圆形。
在本申请所提供的显示面板中，所述第一漏极上设有与所述通孔对应设置的漏极开口，且所述第一漏极至少部分覆盖位于所述层间绝缘层远离所述第一源极的一侧的第一有源层。
在本申请所提供的显示面板中，所述层间绝缘层包括由下至上依次层叠设置的氮化硅层和氧化硅层；所述第一栅极位于所述氮化硅层上，且所述氧化硅层覆盖在所述第一栅极上。
在本申请所提供的显示面板中，所述第一有源层的材料包括金属氧化物。
在本申请所提供的显示面板中，所述阵列基板包括显示区和非显示区，所述第一薄膜晶体管位于所述显示区；所述阵列基板还包括位于所述非显示区的第二薄膜晶体管；
所述第二薄膜晶体管包括第二有源层、第二栅极、第二源极和第二漏极；其中，所述第二栅极与所述第一源极同层设置，且所述第二源极、所述第二漏极和所述第一漏极同层设置。
在本申请所提供的显示面板中，所述第二有源层与所述第二栅极对应设置；所述第二有源层的材料包括低温多晶硅。
在本申请所提供的显示面板中，所述阵列基板还包括衬底、位于所述衬底上的缓冲层、以及位于所述第二有源层和所述第二栅极之间的栅极绝缘层；
其中，所述第二有源层位于所述缓冲层上且与所述第二栅极对应设置，且所述第一源极位于所述栅极绝缘层上。
 有益效果
相较于现有技术，本申请提供的阵列基板和显示面板中，第一薄膜晶体管为垂直结构，具体的，第一薄膜晶体管的第一源极、第一有源层和第一漏极在垂直于阵列基板的方向上依次设置，第一栅极包埋于层间绝缘层中，且第一薄膜晶体管的第一有源层通过贯穿层间绝缘层的通孔分别与第一源极和第一漏极电连接，使得第一薄膜晶体管的沟道长度等于第一栅极的厚度，且第一薄膜晶体管的沟道宽度与通孔的孔径正向相关，该设计可以在保证第一薄膜晶体管的迁移率较高的基础上减小第一薄膜晶体管在垂直于阵列基板方向上的投影面积，可以有效的提高显示面板的开口率，从而有利于开发高分辨率的显示产品。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的一种阵列基板的结构示意图。
图2为本申请实施例中制作阵列基板过程中形成氮化硅层之后的结构示意图。
图3为本申请实施例中制作阵列基板过程中形成第一栅极之后的结构示意图。
图4为图3中第一栅极与第一源极的俯视位置关系示意图。
图5为本申请实施例中制作阵列基板过程中形成第一通孔之后的结构示意图。
图6为本申请实施例中制作阵列基板过程中形成第一有源层之后的结构示意图。
图7为本申请实施例中制作阵列基板过程中形成第一漏极之后的结构示意图。
图8为本申请实施例中制作阵列基板过程中形成透明电极层之后的结构示意图。
图9为本申请实施例提供的一种显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
如图1所示，本申请实施例提供了一种阵列基板1，阵列基板1包括垂直结构的第一薄膜晶体管2；具体的，第一薄膜晶体管2包括第一源极3、层间绝缘层4、第一栅极5、第一漏极6、以及第一有源层7。其中，层间绝缘层4至少覆盖在第一源极3上，且层间绝缘层4上设有贯穿层间绝缘层4且裸露出至少部分第一源极3的通孔（即第一通孔8）；第一栅极5包埋于层间绝缘层4中，且至少位于通孔的一侧；第一漏极6位于层间绝缘层4远离第一源极3的一侧；第一有源层7至少部分位于通孔内，且分别与第一源极3和第一漏极6电连接。
需要说明的是，为了与其他通孔作区分，贯穿层间绝缘层4且裸露出至少部分第一源极3的通孔为第一通孔8。
在一具体实施方式中，第一有源层7位于第一通孔8的侧壁和底部，且延伸至层间绝缘层4远离第一源极3的一侧。第一栅极5围绕位于第一通孔8的侧壁上的第一有源层7设置。第一漏极6上设有与第一通孔8对应设置的漏极开口9，且至少部分覆盖位于层间绝缘层4远离第一源极3的一侧的第一有源层7。
在本申请实施例中，第一通孔8在垂直于阵列基板1的方向上的投影为圆形，当然，第一通孔8在垂直于阵列基板1的方向上的投影形状不限于此，本申请实施例以圆形为例进行说明。可以理解的，第一栅极5上设有栅极开口10，且第一通孔8嵌套在栅极开口10中，以使第一栅极5围绕位于第一通孔8侧壁上的第一有源层7设置。具体的，栅极开口10可以为圆形，当然不限于此。
可以理解的，本申请实施例中的第一有源层7的沟道长度等于第一栅极5的厚度，且第一有源层7的沟道宽度等于贯穿层间绝缘层4的第一通孔8的周长。由于常规薄膜晶体管结构中的有源层通常在同一平面内设置，其沟道长度等于与有源层相对设置的栅极的宽度，其沟道宽度等于有源层的长度，因此，与具有相同沟道尺寸的常规薄膜晶体管结构相比，本申请实施例提供的第一薄膜晶体管2在垂直于阵列基板1方向上的投影面积较小，当第一薄膜晶体管2设置在显示区时，可以有效的提高开口率，有利于高分辨率产品的开发。
具体的，第一栅极5的材料包括钼（Mo）、铝（Al）以及钛（Ti）中的任意一种、或Mo、Al以及Ti的合金、或Mo、Al以及Ti构成的叠层结构。
在一具体实施方式中，第一栅极5的厚度范围为0.5微米至5微米；且第一栅极5的栅极开口10直径范围为1微米至10微米。贯穿层间绝缘层4的第一通孔8的直径较第一栅极5的栅极开口10的直径小0.2微米至1微米。
在一具体实施方式中，层间绝缘层4包括由下至上依次层叠设置的氮化硅层11和氧化硅层12。第一栅极5位于氮化硅层11上，且氧化硅层12覆盖在第一栅极5上，使得第一栅极5被氮化硅层11和氧化硅层12完全包裹。
在一具体实施方式中，第一漏极6为圆环状。可以理解的，位于层间绝缘层4远离第一源极3一侧的第一有源层7也为圆环状，第一漏极6与位于层间绝缘层4远离第一源极3一侧的第一有源层7对应电连接。
在一具体实施方式中，阵列基板1包括显示区13和非显示区14，且第一薄膜晶体管2位于显示区13，用于显示像素驱动。阵列基板1还包括位于非显示区14的第二薄膜晶体管15，用于栅极驱动。
具体的，第二薄膜晶体管15包括第二有源层16、第二栅极17、第二源极18和第二漏极19；其中，第二栅极17与第一源极3同层设置，且第二源极18、第二漏极19和第一漏极6同层设置。
具体的，第一有源层7的材料包括金属氧化物，例如铟镓锌氧化物；第二有源层16的材料包括低温多晶硅。本申请实施例提供的阵列基板1用低温多晶硅薄膜晶体管做栅极驱动且用金属氧化物薄膜晶体管做显示像素驱动，既能提高显示面板的栅极驱动电路中的驱动电流，又能降低显示面板的显示像素驱动时的漏电流。
在一具体实施方式中，第二有源层16包括多晶硅区20、位于多晶硅区20两侧的N型轻掺杂区21、以及位于每个N型轻掺杂区21远离多晶硅区20一侧的N型重掺杂区22；第二源极18和第二漏极19分别与两个N型重掺杂区22连接。当然，第二有源层16的具体结构不限于此。
具体的，阵列基板1还包括衬底23、位于衬底23上的缓冲层24、位于第二有源层16和第二栅极17之间的栅极绝缘层25、依次位于形成有第一漏极6的层间绝缘层4上的钝化层、平坦层27和透明电极层。其中，衬底23可以为玻璃衬底，当然不限于此。第二有源层16位于缓冲层24上且与第二栅极17对应设置；第一源极3位于栅极绝缘层25上。
在一具体实施方式中，阵列基板1还可以包括与第一漏极6同层设置的触控电极26；钝化层包括第一钝化层28和第二钝化层29，透明电极层包括第一透明电极层30和第二透明电极层31；第一钝化层28位于形成有第一漏极6的层间绝缘层4上，平坦层27位于第一钝化层28上，第一透明电极层30位于平坦层27上，第二钝化层29位于第一透明电极层30和平坦层27上，第二透明电极层31位于第二钝化层29上。具体的，第一透明电极层30包括多个底部透明电极，第二透明电极层31包括多个顶部透明电极。具体的，部分顶部透明电极通过贯穿第一钝化层28、平坦层27和第二钝化层29的通孔与第一漏极6电连接，以实现显示功能；另一部分顶部透明电极通过贯穿第二钝化层29的通孔与至少部分底部透明电极电连接，且该部分顶部透明电极还通过贯穿第一钝化层28、平坦层27和第二钝化层29的通孔与触控电极26电连接，以实现触控功能。
结合图2至图8所示，本申请实施例中的阵列基板1的制作过程可以参考以下描述。
如图2所示，先依次在衬底23上形成缓冲层24、第二有源层16以及栅极绝缘层25；然后在栅极绝缘层25上沉积第一金属层，并对第一金属层进行图案化处理，分别形成位于显示区13的第一源极3以及位于非显示区14且与第二有源层16对应设置的第二栅极17；然后在形成有第一源极3和第二栅极17的栅极绝缘层25上沉积氮化硅层11。
如图3和图4所示，在上一步的基础上沉积第二金属层，并对第二金属层进行图案化处理，形成具有栅极开口10的第一栅极5，其中，栅极开口10与第一源极3对应设置，且栅极开口10在衬底23上的正投影至少覆盖部分第一源极3在衬底23上的正投影。
如图5所示，在上一步的基础上在形成有第一栅极5的氮化硅层11上沉积氧化硅层12，其中，氮化硅层11和氧化硅层12共同构成层间绝缘层4；然后对层间绝缘层4进行开孔，形成位于显示区13且裸露出至少部分第一源极3的第一通孔8以及位于非显示区14且分别裸露出第二有源层16的两个N型重掺杂区22的第二通孔32和第三通孔33。
如图6所示，在上一步的基础上沉积金属氧化物层，并对金属氧化物层进行图案化处理，形成位于第一通孔8的侧壁和底部并延伸至氧化硅层12远离第一源极3的一侧的第一有源层7；其中，第一有源层7在第一通孔8的底部与第一源极3电连接。
如图7所示，在上一步的基础上沉积第三金属层，并对第三金属层进行图案化处理，形成位于显示区13的第一漏极6以及位于非显示区14的第二源极18和第二漏极19；其中，第一漏极6部分覆盖在位于氧化硅层12远离第一源极3一侧的第一有源层7上，且第一漏极6上设有与第一通孔8对应设置的漏极开口9；第二源极18和第二漏极19分别通过第二通孔32和第三通孔33与第二有源层16的两个N型重掺杂区22电连接。
如图8所示，在上一步的基础上依次完成第一钝化层28、平坦层27、第一透明电极层30、第二钝化层29和第二透明电极层31制程，其中，平坦层27将填充在第一通孔8内，以保证膜层的平坦性。
本申请实施例中，第一薄膜晶体管2为垂直结构，具体的，第一薄膜晶体管2的第一源极3、第一有源层7和第一漏极6在垂直于阵列基板1的方向上依次设置，第一栅极5包埋于层间绝缘层4中，且第一薄膜晶体管2的第一有源层7通过贯穿层间绝缘层4的通孔分别与第一源极3和第一漏极6电连接，使得第一薄膜晶体管2的沟道长度等于第一栅极5的厚度，且第一薄膜晶体管2的沟道宽度与通孔的孔径正向相关，例如沟道宽度等于通孔的周长；该设计可以在保证第一薄膜晶体管2的迁移率较高的基础上减小第一薄膜晶体管2在垂直于阵列基板1方向上的投影面积，可以有效的提高显示面板的开口率，从而有利于开发高分辨率的显示产品。
需要说明的是，本申请提供的第一薄膜晶体管2还可以搭配其他不同于第二薄膜晶体管15结构的晶体管使用，或者说本申请提供的阵列基板上的第二薄膜晶体管15的结构不限于本申请实施例中所描述的结构。另外，本申请对第一有源层和第二有源层的材料不做限制。
如图9所示，本申请实施例还提供一种显示面板34，包括上述实施例中的阵列基板1和与阵列基板1相对设置的对置基板35。
具体的，对置基板35包括彩膜基板，显示面板34还包括设置在阵列基板1和对置基板35之间的液晶层。
本申请实施例中，第一薄膜晶体管2为垂直结构，可以在保证迁移率较高的基础上减小第一薄膜晶体管2在垂直于阵列基板1方向上的投影面积，可以有效的提高显示面板34的开口率，从而有利于开发高分辨率显示面板34。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种阵列基板和显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种阵列基板，包括垂直结构的第一薄膜晶体管；
    所述第一薄膜晶体管包括：
    第一源极；
    层间绝缘层，至少覆盖在所述第一源极上；所述层间绝缘层上设有贯穿所述层间绝缘层且裸露出至少部分所述第一源极的通孔；
    第一栅极，包埋于所述层间绝缘层中，且至少位于所述通孔的一侧；
    第一漏极，位于所述层间绝缘层远离所述第一源极的一侧；以及
    第一有源层，至少部分位于所述通孔内，且分别与所述第一源极和所述第一漏极电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述第一有源层位于所述通孔的侧壁和底部，且延伸至所述层间绝缘层远离所述第一源极的一侧。
  3. 根据权利要求2所述的阵列基板，其中，所述第一栅极围绕位于所述通孔的侧壁上的第一有源层设置。
  4. 根据权利要求3所述的阵列基板，其中，所述第一栅极上设有栅极开口；所述通孔嵌套在所述栅极开口中；
    所述栅极开口在垂直于所述层间绝缘层方向上的投影和所述通孔在垂直于所述层间绝缘层方向上的投影为圆形。
  5. 根据权利要求2所述的阵列基板，其中，所述第一漏极上设有与所述通孔对应设置的漏极开口，且所述第一漏极至少部分覆盖位于所述层间绝缘层远离所述第一源极的一侧的第一有源层。
  6. 根据权利要求1所述的阵列基板，其中，所述层间绝缘层包括由下至上依次层叠设置的氮化硅层和氧化硅层；所述第一栅极位于所述氮化硅层上，且所述氧化硅层覆盖在所述第一栅极上。
  7. 根据权利要求1所述的阵列基板，其中，所述第一有源层的材料包括金属氧化物。
  8. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括显示区和非显示区，所述第一薄膜晶体管位于所述显示区；所述阵列基板还包括位于所述非显示区的第二薄膜晶体管；
    所述第二薄膜晶体管包括第二有源层、第二栅极、第二源极和第二漏极；其中，所述第二栅极与所述第一源极同层设置，且所述第二源极、所述第二漏极和所述第一漏极同层设置。
  9. 根据权利要求8所述的阵列基板，其中，所述第二有源层与所述第二栅极对应设置；所述第二有源层的材料包括低温多晶硅。
  10. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括衬底、位于所述衬底上的缓冲层、以及位于所述第二有源层和所述第二栅极之间的栅极绝缘层；
    其中，所述第二有源层位于所述缓冲层上且与所述第二栅极对应设置，且所述第一源极位于所述栅极绝缘层上。
  11. 一种显示面板，包括阵列基板和与所述阵列基板相对设置的对置基板；
    所述阵列基板包括垂直结构的第一薄膜晶体管；
    所述第一薄膜晶体管包括：
    第一源极；
    层间绝缘层，至少覆盖在所述第一源极上；所述层间绝缘层上设有贯穿所述层间绝缘层且裸露出至少部分所述第一源极的通孔；
    第一栅极，包埋于所述层间绝缘层中，且至少位于所述通孔的一侧；
    第一漏极，位于所述层间绝缘层远离所述第一源极的一侧；以及
    第一有源层，至少部分位于所述通孔内，且分别与所述第一源极和所述第一漏极电连接。
  12. 根据权利要求11所述的显示面板，其中，所述第一有源层位于所述通孔的侧壁和底部，且延伸至所述层间绝缘层远离所述第一源极的一侧。
  13. 根据权利要求12所述的显示面板，其中，所述第一栅极围绕位于所述通孔的侧壁上的第一有源层设置。
  14. 根据权利要求13所述的显示面板，其中，所述第一栅极上设有栅极开口；所述通孔嵌套在所述栅极开口中；
    所述栅极开口在垂直于所述层间绝缘层方向上的投影和所述通孔在垂直于所述层间绝缘层方向上的投影为圆形。
  15. 根据权利要求12所述的显示面板，其中，所述第一漏极上设有与所述通孔对应设置的漏极开口，且所述第一漏极至少部分覆盖位于所述层间绝缘层远离所述第一源极的一侧的第一有源层。
  16. 根据权利要求11所述的显示面板，其中，所述层间绝缘层包括由下至上依次层叠设置的氮化硅层和氧化硅层；所述第一栅极位于所述氮化硅层上，且所述氧化硅层覆盖在所述第一栅极上。
  17. 根据权利要求11所述的显示面板，其中，所述第一有源层的材料包括金属氧化物。
  18. 根据权利要求11所述的显示面板，其中，所述阵列基板包括显示区和非显示区，所述第一薄膜晶体管位于所述显示区；所述阵列基板还包括位于所述非显示区的第二薄膜晶体管；
    所述第二薄膜晶体管包括第二有源层、第二栅极、第二源极和第二漏极；其中，所述第二栅极与所述第一源极同层设置，且所述第二源极、所述第二漏极和所述第一漏极同层设置。
  19. 根据权利要求18所述的显示面板，其中，所述第二有源层与所述第二栅极对应设置；所述第二有源层的材料包括低温多晶硅。
  20. 根据权利要求18所述的显示面板，其中，所述阵列基板还包括衬底、位于所述衬底上的缓冲层、以及位于所述第二有源层和所述第二栅极之间的栅极绝缘层；
    其中，所述第二有源层位于所述缓冲层上且与所述第二栅极对应设置，且所述第一源极位于所述栅极绝缘层上。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3838355A1 (de) * 1988-11-11 1990-05-17 Fraunhofer Ges Forschung Vertikaltransistoranordnung
CN1073806A (zh) * 1991-12-27 1993-06-30 三星电子株式会社 用于半导体存储器件的薄膜晶体管及其制造方法
US6846709B1 (en) * 2003-10-06 2005-01-25 Atmel Corporation Vertical gate CMOS with lithography-independent gate length
US20170256649A1 (en) * 2014-11-28 2017-09-07 Sharp Kabushiki Kaisha Semiconductor device
CN112968061A (zh) * 2021-02-03 2021-06-15 京东方科技集团股份有限公司 薄膜晶体管、显示基板及其制备方法和显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109300915B (zh) * 2018-09-30 2020-09-04 厦门天马微电子有限公司 一种阵列基板、显示面板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3838355A1 (de) * 1988-11-11 1990-05-17 Fraunhofer Ges Forschung Vertikaltransistoranordnung
CN1073806A (zh) * 1991-12-27 1993-06-30 三星电子株式会社 用于半导体存储器件的薄膜晶体管及其制造方法
US6846709B1 (en) * 2003-10-06 2005-01-25 Atmel Corporation Vertical gate CMOS with lithography-independent gate length
US20170256649A1 (en) * 2014-11-28 2017-09-07 Sharp Kabushiki Kaisha Semiconductor device
CN112968061A (zh) * 2021-02-03 2021-06-15 京东方科技集团股份有限公司 薄膜晶体管、显示基板及其制备方法和显示装置

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