CN108649036A - 一种阵列基板及其制作方法 - Google Patents
一种阵列基板及其制作方法 Download PDFInfo
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- CN108649036A CN108649036A CN201810404403.0A CN201810404403A CN108649036A CN 108649036 A CN108649036 A CN 108649036A CN 201810404403 A CN201810404403 A CN 201810404403A CN 108649036 A CN108649036 A CN 108649036A
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- 239000000758 substrate Substances 0.000 title claims abstract description 71
- 238000002360 preparation method Methods 0.000 title abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 63
- 229910052751 metal Inorganic materials 0.000 claims abstract description 63
- 238000002161 passivation Methods 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- 229920005591 polysilicon Polymers 0.000 claims abstract description 35
- 238000009413 insulation Methods 0.000 claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
本发明提供了一种阵列基板及其制作方法,包括:提供一基板,并在所述基板上方制备层叠设置的遮光层、第一缓冲层、多晶硅层、栅绝缘层、经图案化的第一金属、间绝缘层、第二缓冲层、经图案化的第二金属、第三缓冲层、经图案化的第一透明电极和钝化层;采用一道光罩工艺形成贯穿钝化层、第三缓冲层、第二缓冲层、栅绝缘层与多晶硅层接触的过孔;在钝化层表面制备图案化的第二透明电极,第二透明电极覆盖过孔表面,并与第二金属连接。本发明将栅绝缘层、第二缓冲层、第三缓冲层和钝化层通过一道过孔工艺实现各层的有效连接,进而将所需的四道光罩工艺节约为一道光罩工艺,极大的简化了阵列基板工艺流程和生产成本。
Description
技术领域
本发明涉及显示技术领域,具体涉及一种阵列基板及其制作方法。
背景技术
低温多晶硅(Low temperature poly-silicon,简称LTPS)技术具有电子迁移率高的优点,能够有效的减小薄膜晶体管(thin film transistor,简称TFT)器件的面积,从而提升像素的开口率,在增大面板显示亮度的同时可以降低整体的功耗,进而大幅度降低面板的制造成本,因此,LTPS工艺目前已成为液晶显示领域炙手可热的技术。
但是,现有的LTPS工艺复杂,阵列基板膜层的数目较多,一般需要至少10层的膜层结构,这样就需要较多的光罩工艺来进行层膜结构的制备,同时延长了产品制作时间,增加了产品的关照成本、物料成本和运营成本。
如何能够有效的降低阵列基板制作周期,提升产品的良率,提升产品的生产能力,降低产品的生产成本,是目前面板设计行业所关注的重点,也是增加公司市场竞争力的有效途径。因此目前亟须一种能够节省光罩工艺的ITPS阵列基板及其制作方法。
发明内容
本发明提供了一种阵列基板及其制作方法,以解决现有阵列基板制作工艺中,所需光罩工艺较多,导致产品生产工艺复杂,阵列基板制备成本较高的问题。
为实现上述目的,本发明提供的技术方案如下:
根据本发明的一个方面,提供了一种阵列基板的制作方法,所述阵列基板的制作方法包括如下步骤:
步骤S10、提供一基板,并在所述基板上方依次制备层叠设置的遮光层、第一缓冲层和多晶硅层;
步骤S20、在所述多晶硅层表面依次制备栅绝缘层、经图案化的第一金属,并对所述多晶硅层完成离子注入以形成两端的源漏极掺杂区和中间的沟道区;
步骤S30、在所述间绝缘层的上方依次制备层叠设置的第二缓冲层、经图案化的第二金属、第三缓冲层、经图案化的第一透明电极和钝化层;
步骤S40、采用一道光罩工艺形成过孔,所述过孔贯穿所述钝化层、所述第三缓冲层、所述第二缓冲层、所述栅绝缘层与所述多晶硅层接触;
步骤S50、在钝化层表面制备图案化的第二透明电极,所述第二透明电极覆盖所述过孔表面,并与所述第二金属连接。
根据本发明一优选实施例,所述钝化层、所述第三缓冲层、所述第二缓冲层、所述栅绝缘层的制备材料均为氮化硅和氧化硅中的至少一者。
根据本发明一优选实施例,所述第一金属为栅极金属,所述第二金属为源漏极金属。
根据本发明一优选实施例,所述第一透明电极为公共电极,所述第二透明电极为像素电极。
根据本发明一优选实施例,所述像素电极通过过孔将所述钝化层、所述第三绝缘层、所述第二金属、所述第二缓冲层、所述间绝缘层、所述多晶硅层电性互连。
根据本发明的另一个方面,提供了一种阵列基板,包括:
基板;
遮光层,设置在所述基板上方;
第一缓冲层,设置在所述基板的上方,并覆盖所述遮光层;
多晶硅层,设置在所述第一缓冲层的上方;
栅绝缘层,设置在所述多晶硅层的上方;
第一金属,设置在所述栅绝缘层的上方,并对应于所述多晶硅层位置;
第二缓冲层,设置在所述栅绝缘层的上方,并覆盖所述第一金属;
第二金属,设置在所述第二缓冲层的上方;
第三缓冲层,设置在所述第二缓冲层的上方,并覆盖所述第二金属;
第一透明电极,设置在所述第三缓冲层的上方;
钝化层,设置在所述第三缓冲层的上方,并覆盖所述第一电极;
第二透明电极,设置在所述钝化层的上方;
过孔,所述过孔贯穿所述钝化层、所述第三缓冲层、所述第二缓冲层、所述栅绝缘层与所述多晶硅层接触;
其中,所述第二透明电极覆盖所述过孔表面,并与所述第二金属连接。
根据本发明一优选实施例,所述钝化层、所述第三缓冲层、所述第二缓冲层、所述栅绝缘层的制备材料均为氮化硅和氧化硅中的至少一者。
根据本发明一优选实施例,所述第一金属为栅极金属,所述第二金属为源漏极金属。
根据本发明一优选实施例,所述第一透明电极为公共电极,所述第二透明电极为像素电极。
根据本发明一优选实施例,所述像素电极通过过孔将所述钝化层、所述第三绝缘层、所述第二金属、所述第二缓冲层、所述间绝缘层、所述多晶硅层电性互连。
本发明的优点是,提供了一种阵列基板及其制作方法,将栅绝缘层、第二缓冲层、第三缓冲层和钝化层通过一道过孔工艺实现各层的有效连接,进而将所需的四道光罩工艺节约为一道光罩工艺,极大的简化了阵列基板工艺流程和生产成本。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单介绍,显而易见地,下面描述中的附图仅仅是发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例中阵列基板的制作方法的流程示意图;
图2a-2e为本发明实施例中阵列基板的制作方法的结构示意图;
图3为本发明实施例中阵列基板结构示意图。
具体实施方式
以下各实施例的说明是参考附加的图示,用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语,例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。在图中,结构相似的单元是用以相同标号表示。
本发明针对现有阵列基板制作工艺中,所需光罩工艺较多,导致产品生产工艺复杂,阵列基板制备成本较高的问题,提出了一种阵列基板及其制作方法,本实施例能够改善该缺陷。
下面结合附图和具体实施例对本发明做进一步的说明:
图1为本发明实施例中LTPS阵列基板的制作方法的流程示意图;图2a-2e为本发明实施例中阵列基板的制作方法的结构示意图。
如图1所示,本发明提供了一种阵列基板的制作方法,所述阵列基板的制作方法包括如下步骤:
如图2a所示,步骤S10、提供一基板11,并在所述基板11上方依次制备层叠设置的遮光层12、第一缓冲层13和多晶硅层14a。
进一步的,所述基板11为玻璃基板,一般作为阵列基板刚性衬底使用,在玻璃基板上进行LTPS工艺前,需要将玻璃基板清洗干净。
遮光层12由不透明材料制备,既可以为金属材料也可以为无机物材料,在有的情况下,遮光层12也可以省略;缓冲层13制备在基板11的上方,并覆盖所述遮光层12,所述缓冲层13的制备材料为氮化硅和氧化硅中的至少一者,缓冲层13既可以阻挡外界微粒污染LTPS器件,也可以起到缓冲的作用。
通常的,在步骤S10中需要采用2道光罩工艺,第一道光罩工艺用于制备遮光层12,第二道光罩工艺用于制备多晶层14a。
如图2b所示,步骤S20、在所述多晶硅层14a表面依次制备栅绝缘层15、经图案化的第一金属16,并对所述多晶硅层14a完成离子注入以形成两端的源漏极掺杂区(包括源漏极轻掺杂区142和源漏极重掺杂区141)和中间的沟道区143。
具体的,在所述栅绝缘层15制备第一金属层,对所述多晶硅层14a和所述第一金属层进行第一次蚀刻以形成源漏极重掺杂区141和初始图案的第一金属,随后对所述多晶硅层14a和所述初始图案的第一金属进行第二次蚀刻以形成源漏极轻掺杂区142和第一金属16,所述第一次蚀刻、所述第二次蚀刻均在第三道光罩工艺中制备。
具体的,所述第一金属16为栅极金属,所述栅绝缘层15设置在所述第一缓冲层15的上方并覆盖所述多晶硅层14,所述栅绝缘层15的制备材料为氧化硅和氮化硅中的至少一者。
如图2c所示,步骤S30、在所述间绝缘层15的上方依次制备层叠设置的第二缓冲层17、经图案化的第二金属18、第三缓冲层19、经图案化的第一透明电极20和钝化层21;
具体的,在步骤S30中,在所述间绝缘层5的上方制备第二缓冲层17,在所述第二缓冲层17的上方涂布第二金属层,采用第四道光罩工艺图案化所述第二金属层以形成第二金属18。
优选的,所述第二金属18为源漏极金属。
所述第二缓冲层17、所述第三缓冲层19和所述钝化层21的制备材料相似,均为氧化硅和氮化硅中的至少一者,值得理解的是,所述第二缓冲层17、所述第三缓冲层19和所述钝化层21的制备材料也可以为其他相似的无机材料。
其中,在步骤S30中,采用第五道光罩工艺制备第一透明电极20。
如图2d所示,步骤S40、采用一道光罩工艺形成过孔23,所述过孔23贯穿所述钝化层21、所述第三缓冲层19、所述第二缓冲层17、所述栅绝缘层15与所述多晶硅层14接触。
具体的,所述过孔23与所述多晶硅层14的重掺杂区141相连。
形成过孔23所用的光罩工艺为本发明中所使用的第六道光罩工艺,也是本发明的主要发明点,本发明通过将原本需要四道光罩工艺制备的钝化层过孔、第三缓冲层过孔、第二缓冲层过孔和间绝缘层过孔整合为本发明中的一道过孔23,在利用所述钝化层21、所述第三缓冲层19、所述第二缓冲层17、所述栅绝缘层15所使用材料相同或化学性质相似,从而实现了一道光罩工艺蚀刻完所有的过孔(即本发明中整合的过孔23),本发明采用一道光罩工艺代替四道工艺的,极大的简化了阵列基板制作工序。
如图2e所示,步骤S50、在钝化层21表面制备图案化的第二透明电极22,所述第二透明电极22覆盖所述过孔23表面,并与所述第二金属18连接。
具体的,在步骤S50中,在所述钝化层21表面形成第二透明电极层,采用第七道光罩工艺图案化所述第二透明电极层以形成第二透明电极22。
所述第二透明电极22覆盖所述过孔23表面,所述第二透明电极22通过过孔23实现了所述钝化层21、所述第三绝缘层19、所述第二金属18、所述第二缓冲层17、所述间绝缘层15、所述多晶硅层14电性互连。
优选的,所述第一透明电极20为公共电极,所述第二透明电极22为像素电极。
如图3所示,根据本发明的另一个方面,还提供了一种阵列基板,所述阵列基板包括:
基板31;
遮光层32,所述遮光层32设置在所述基板31上方;
第一缓冲层33,所述第一缓冲层33设置在所述基板31的上方,并覆盖所述遮光层32;
多晶硅层34,所述多晶硅层34设置在所述第一缓冲层33的上方;
栅绝缘层35,所述栅绝缘层35设置在所述多晶硅层34的上方;
第一金属36,所述第一金属36设置在所述栅绝缘层35的上方,并对应于所述多晶硅层34位置;
第二缓冲层37,所述第二缓冲层37设置在所述栅绝缘层35的上方,并覆盖所述第一金属36;
第二金属38,所述第二金属38设置在所述第二缓冲层37的上方;
第三缓冲层39,所述第三缓冲层39设置在所述第二缓冲层38的上方,并覆盖所述第二金属38;
第一透明电极40,所述第一透明电极40设置在所述第三缓冲层39的上方;
钝化层41,所述钝化层41设置在所述第三缓冲层39的上方,并覆盖所述第一电极40;
第二透明电极42,所述第二透明电极42设置在所述钝化层41的上方;
过孔23,所述过孔23贯穿所述钝化层41、所述第三缓冲层39、所述第二缓冲层37、所述栅绝缘层35与所述多晶硅层34接触;
其中,所述第二透明电极22覆盖所述过孔表面,并与所述第二金属38连接。
优选的,所述钝化层41、所述第三缓冲层39、所述第二缓冲层37、所述栅绝缘层35的制备材料均为氮化硅和氧化硅中的至少一者。
优选的,所述第一金属36为栅极金属,所述第二金属38为源漏极金属。
优选的,所述第一透明电极40为公共电极,所述第二透明电极42为像素电极。
优选的,所述像素电极42通过过孔43将所述钝化层41、所述第三绝缘层39、所述第二金属38、所述第二缓冲层37、所述间绝缘层35、所述多晶硅层34电性互连。
在本实施例中,通过将第二金属38设置在第二缓冲层37的上方,使得过孔43可以依次贯穿所述钝化层41、所述第三绝缘层39、所述第二缓冲层37、所述间绝缘层35,一个过孔能够实现多层之间的电性互连,为所述阵列基板的制作方法中节省光罩制程提供了结构基础。
由于本发明中所述阵列基板原理与所述阵列基板的制作方法的工作原理相同,所述阵列基板原理具体请参考所述阵列基板的制作方法的工作原理,在此不做赘述。
本发明的优点是,提供了一种阵列基板及其制作方法,将栅绝缘层、第二缓冲层、第三缓冲层和钝化层通过一道过孔工艺实现各层的有效连接,进而将所需的四道光罩工艺节约为一道光罩工艺,极大的简化了阵列基板工艺流程和生产成本。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。
Claims (10)
1.一种阵列基板的制作方法,其特征在于,所述阵列基板的制作方法包括如下步骤:
步骤S10、提供一基板,并在所述基板上方依次制备层叠设置的遮光层、第一缓冲层和多晶硅层;
步骤S20、在所述多晶硅层表面依次制备栅绝缘层、经图案化的第一金属,并对所述多晶硅层完成离子注入以形成两端的源漏极掺杂区和中间的沟道区;
步骤S30、在所述间绝缘层的上方依次制备层叠设置的第二缓冲层、经图案化的第二金属、第三缓冲层、经图案化的第一透明电极和钝化层;
步骤S40、采用一道光罩工艺形成过孔,所述过孔贯穿所述钝化层、所述第三缓冲层、所述第二缓冲层、所述栅绝缘层与所述多晶硅层接触;
步骤S50、在钝化层表面制备图案化的第二透明电极,所述第二透明电极覆盖所述过孔表面,并与所述第二金属连接。
2.根据权利要求1所述的阵列基板的制作方法,其特征在于,所述钝化层、所述第三缓冲层、所述第二缓冲层、所述栅绝缘层的制备材料均为氮化硅和氧化硅中的至少一者。
3.根据权利要求1所述的阵列基板的制作方法,其特征在于,所述第一金属为栅极金属,所述第二金属为源漏极金属。
4.根据权利要求1所述的阵列基板的制作方法,其特征在于,所述第一透明电极为公共电极,所述第二透明电极为像素电极。
5.根据权利要求4所述的阵列基板的制作方法,其特征在于,所述像素电极通过过孔将所述钝化层、所述第三绝缘层、所述第二金属、所述第二缓冲层、所述间绝缘层、所述多晶硅层电性互连。
6.一种阵列基板,其特征在于,所述阵列基板包括:
基板;
第一缓冲层,设置在所述基板的上方,并覆盖所述基板;
多晶硅层,设置在所述第一缓冲层的上方;
栅绝缘层,设置在所述多晶硅层的上方;
第一金属,设置在所述栅绝缘层的上方,并对应于所述多晶硅层位置;
第二缓冲层,设置在所述栅绝缘层的上方,并覆盖所述第一金属;
第二金属,设置在所述第二缓冲层的上方;
第三缓冲层,设置在所述第二缓冲层的上方,并覆盖所述第二金属;
第一透明电极,设置在所述第三缓冲层的上方;
钝化层,设置在所述第三缓冲层的上方,并覆盖所述第一电极;
第二透明电极,设置在所述钝化层的上方;
过孔,所述过孔贯穿所述钝化层、所述第三缓冲层、所述第二缓冲层、所述栅绝缘层与所述多晶硅层接触;
其中,所述第二透明电极覆盖所述过孔表面,并与所述第二金属连接。
7.根据权利要求6所述的阵列基板,其特征在于,所述钝化层、所述第三缓冲层、所述第二缓冲层、所述栅绝缘层的制备材料均为氮化硅和氧化硅中的至少一者。
8.根据权利要求6所述的阵列基板,其特征在于,所述第一金属为栅极金属,所述第二金属为源漏极金属。
9.根据权利要求6所述的阵列基板,其特征在于,所述第一透明电极为公共电极,所述第二透明电极为像素电极。
10.根据权利要求9所述的阵列基板,其特征在于,所述像素电极通过过孔将所述钝化层、所述第三绝缘层、所述第二金属、所述第二缓冲层、所述间绝缘层、所述多晶硅层电性互连。
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CN110634804A (zh) * | 2019-08-09 | 2019-12-31 | 武汉华星光电技术有限公司 | 一种阵列基板及其制备方法、触控显示面板 |
CN110854139A (zh) * | 2019-11-26 | 2020-02-28 | 武汉华星光电技术有限公司 | 一种tft阵列基板、其制备方法及其显示面板 |
CN111613578A (zh) * | 2020-06-08 | 2020-09-01 | 武汉华星光电技术有限公司 | 低温多晶硅阵列基板的制备方法、阵列基板、显示面板 |
CN114156288A (zh) * | 2021-11-30 | 2022-03-08 | 武汉华星光电技术有限公司 | 阵列基板及显示面板 |
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