CN105137645A - 一种彩膜阵列基板及其制造方法、显示装置 - Google Patents

一种彩膜阵列基板及其制造方法、显示装置 Download PDF

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CN105137645A
CN105137645A CN201510622182.0A CN201510622182A CN105137645A CN 105137645 A CN105137645 A CN 105137645A CN 201510622182 A CN201510622182 A CN 201510622182A CN 105137645 A CN105137645 A CN 105137645A
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pattern
black matrix
passivation layer
hole
array substrate
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CN105137645B (zh
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付如海
林永伦
张君恺
邱杰
叶成亮
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to PCT/CN2015/091196 priority patent/WO2017049663A1/zh
Priority to US14/787,064 priority patent/US9933652B2/en
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    • GPHYSICS
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    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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Abstract

本发明公开了一种彩膜阵列基板及其制造方法、显示装置,其通过在彩膜阵列基板的基板上形成多个阵列式排布的像素单元,且每个像素单元包括透光区域及位于透光区域外围的非透光区域,像素单元进一步包括彩色滤光图案和黑矩阵图案,其中彩色滤光图案覆盖透光区域,黑矩阵图案在下方不设置彩色滤光图案的情况下直接覆盖非透光区域。与现有技术相比,本发明能够在像素单元的非透光区域形成较厚的黑矩阵图案,以避免漏光问题,进而改善后续显示品质。

Description

一种彩膜阵列基板及其制造方法、显示装置
技术领域
本发明涉及显示技术领域,尤其涉及一种彩膜阵列基板及其制造方法、显示装置。
背景技术
随着人们对液晶显示产品高、精、细品质的要求越来越高,产线对液晶显示屏的阵列基板和彩膜基板的对位压盒精度要求也越来越高。传统的对盒工艺已经无法满足高精度要求,而通过在阵列基板上制作彩色滤光膜来提高对位精度和提升开口率的彩膜阵列基板技术逐渐开展起来。
彩膜阵列基板技术直接在阵列基板上制备彩色滤光膜和黑矩阵,使其与像素电极的对位精度要求大幅度减少,从而使得像素单元的开口率大幅度提高,实现增大光透过率和对比度的目的。现有技术中彩膜阵列基板的彩色滤光膜铺满整个像素单元即铺满像素单元的透光区域和非透光区域(或布线区域),在与薄膜晶体管、扫描线、数据线等对应的位置再铺设黑矩阵以防止非透光区域的漏光,但是薄膜晶体管的漏极需要与黑矩阵和彩色滤光膜上的像素电极实现电连接,通常是将黑矩阵和彩色滤光膜对应漏极连接的位置进行挖孔形成通孔,通过该通孔与像素电极电连接,但是由于黑矩阵材料的光密度较小,需要涂布很厚的黑矩阵材料才能有效避免漏光的问题,而且黑矩阵材料具有一定的流动性,常常会有一部分流入通孔中,或其他地势较低的区域,如从彩膜阵列基板的带有彩色滤光膜的显示区域流到不含有彩色滤光膜的位于彩膜阵列基板边沿的非显示区域,进而使得非透光区域的彩色滤光膜上的黑矩阵变薄,进而引起漏光问题,以最终影响显示品质。
综上,现有技术在像素单元的非透光区域存在黑矩阵变薄而引起漏光的问题,对后续显示品质有不良影响。
发明内容
本发明主要解决的技术问题是提供一种彩膜阵列基板及其制造方法、显示装置,能够在像素单元的非透光区域形成较厚的黑矩阵图案,以避免漏光问题。
为解决上述技术问题,本发明采用的一个技术方案是:提供一种彩膜阵列基板,该彩膜阵列基板包括基板、形成在基板上的多个阵列式排布的像素单元,像素单元包括透光区域及位于透光区域外围的非透光区域,像素单元进一步包括彩色滤光图案和黑矩阵图案,其中彩色滤光图案覆盖透光区域,黑矩阵图案在下方不设置彩色滤光图案的情况下直接覆盖非透光区域。
其中,黑矩阵图案是有机光阻材料。
其中,像素单元进一步包括薄膜晶体管、扫描线图案、数据线图案、第一钝化层和像素电极图案,薄膜晶体管的栅极图案和源极图案分别与扫描线图案和数据线图案连接,像素电极图案位于第一钝化层上部,第一钝化层上设有第一通孔,薄膜晶体管的漏极图案通过第一通孔与像素电极图案连接,黑矩阵图案与薄膜晶体管、扫描线图案和数据线图案对应设置,且直接接触第一钝化层。
其中,黑矩阵图案设置在第一钝化层上。
可选的,黑矩阵图案设置在第一钝化层与基板之间。
其中,黑矩阵图案在第一通孔的位置也设有第二通孔,用于薄膜晶体管的漏极图案通过第一通孔、第二通孔与像素电极图案连接。
其中,像素单元进一步包括第二钝化层,第二钝化层位于黑矩阵图案和像素电极图案之间,第二钝化层上设有第三通孔,用于薄膜晶体管的漏极图案通过第一通孔、第二通孔和第三通孔与像素电极图案连接。
可选的,黑矩阵图案设置在第一钝化层与基板之间。
为解决上述技术问题,本发明采用的另一个技术方案是:提供一种显示装置,该显示装置包括上述的彩膜阵列基板。
为解决上述技术问题,本发明采用的又一个技术方案是:提供一种彩膜阵列基板的制造方法,该方法包括以下步骤:提供一基板;在基板上依次形成薄膜晶体管的栅极图案和扫描线图案、栅极绝缘层、半导体层图案、薄膜晶体管的源极图案和漏极图案及数据线图案;
在薄膜晶体管的源极图案和漏极图案及数据线图案上形成第一钝化层;
在第一钝化层上形成彩色滤光图案,使得彩色滤光图案覆盖彩膜阵列基板的透光区域;
在第一钝化层上形成与彩色滤光图案间隔设置的黑矩阵图案,使得黑矩阵图案覆盖彩膜阵列基板的非透光区域。
其中,该制造方法进一步包括:在彩色滤光图案和黑矩阵图案上形成第二钝化层;
在第二钝化层、黑矩阵图案和第一钝化层的对应漏极图案的位置形成通孔;
在第二钝化层上形成像素电极图案,使得像素电极图案通过通孔与漏极图案电连接。
本发明的有益效果是:本发明通过在彩膜阵列基板的基板上形成多个阵列式排布的像素单元,且每个像素单元包括透光区域及位于透光区域外围的非透光区域,像素单元进一步包括彩色滤光图案和黑矩阵图案,其中彩色滤光图案覆盖透光区域,黑矩阵图案在下方不设置彩色滤光图案的情况下直接覆盖非透光区域。与现有技术相比,本发明能够在像素单元的非透光区域形成较厚的黑矩阵图案,以避免漏光问题,进而改善后续显示品质。
附图说明
图1是本发明提供的一种彩膜阵列基板一实施方式的俯视示意图;
图2是图1中沿A-A的截面示意图;
图3是图1中沿B-B的截面示意图;
图4是本发明提供的一种显示装置一实施方式的结构示意图;
图5是本发明提供的一种彩膜阵列基板的制造方法一实施方式的流程示意图;
图6是图5中每个步骤对应的制程示意图。
具体实施方式
请参阅图1和图2,图1是本发明提供的一种彩膜阵列基板一实施方式的俯视示意图。图2是图1中沿A-A的截面示意图。结合图1和图2所示,该彩膜阵列基板10包括基板11,形成在基板11上的多个阵列式排布的像素单元12,像素单元12包括透光区域I及位于透光区域I外围的非透光区域II,像素单元12进一步包括彩色滤光图案121和黑矩阵图案122,其中彩色滤光图案121覆盖透光区域I,黑矩阵图案122在下方不设置彩色滤光图案121的情况下直接覆盖非透光区域II。
其中,透光区域I为像素单元12的像素开口区域,用于显示彩色图像,非透光区域II为设置驱动透光区域I的电子元器件的区域。
其中,图1中彩膜阵列基板10在虚线内的区域为其显示区域,设有多个阵列式排布的像素单元12,在显示区域外围的区域为非显示区域,用于设置彩膜阵列基板10的驱动电路或与外接驱动电路的布线结构。
其中,在彩膜阵列基板10中黑矩阵图案122使用的是有机光阻材料。
请继续参阅图1和图2所示,像素单元12进一步包括薄膜晶体管、扫描线图案123(图2中未示出)、数据线图案124(图2中未示出)、第一钝化层125(图1中未示出)和像素电极图案126(图1中未示出),薄膜晶体管包括依次设置在基板11上的栅极图案127,栅极绝缘层128、半导体图案129,源极图案130和漏极图案131,具体的,第一钝化层125设于源极图案130和漏极图案131上,栅极图案127和源极图案130分别与扫描线图案123和数据线图案124连接,像素电极图案126位于第一钝化层125上部,第一钝化层125上设有第一通孔132,薄膜晶体管的漏极图案131通过第一通孔132与像素电极图案126连接,黑矩阵图案122与薄膜晶体管、扫描线123和数据线124对应设置,且直接接触第一钝化层125。
其中,黑矩阵图案122与薄膜晶体管、扫描线图案123和数据线图案124对应设置是指黑矩阵图案122能够铺满非透光区域II,而薄膜晶体管、扫描线图案123和数据线图案124设于非透光区域II中,黑矩阵图案122能够遮盖该区域使之不能透光。
可以理解的是,虽然图2中示例为黑矩阵图案122设置在第一钝化层125上,可选的,黑矩阵图案22也可设置在第一钝化层125与基板11之间。如图2所示,进一步的,像素电极图案126位于黑矩阵图案122之上,黑矩阵图案122在第一通孔132的位置也设有第二通孔133,用于薄膜晶体管的漏极图案131通过第一通孔131、第二通孔132与像素电极图案126连接。同样可以理解的是,图1中扫描线图案123和数据线图案124可选位于黑矩阵图案122的上方或下方,但其尺寸小于或等于黑矩阵图案122。在其他实施方式中,像素单元12可选还包括公共电极图案133,该公共电极图案133与扫描线图案123和数据线图案124绝缘设置,用于形成像素单元12中的存储电容(图1和图2中未示出)。
请继续参阅图2,像素单元12进一步包括第二钝化层134,第二钝化层134位于黑矩阵图案122和像素电极图案126之间,第二钝化层134上设有第三通孔135,用于薄膜晶体管的漏极图案131通过第一通孔131、所第二通孔132和第三通孔135与像素电极图案126连接。
其中,第一钝化层125、栅极绝缘层128和第二钝化层134为整面结构,不需要通过光罩工序进行图案化。
其中,为了连接像素电极图案126的需要,可选第一通孔131、第二通孔132和第三通孔135区域没有覆盖黑矩阵材料。即黑矩阵图案122在第一通孔131、第二通孔132和第三通孔135区域无黑矩阵材料。
请参阅图3,图3是图1中沿B-B的截面示意图。结合图3和图1、图2所示,彩色滤光图案121在显示区域I的第一钝化层125上,可以理解的是,第一钝化层125的下方依次是栅极绝缘层128和基板11,第一钝化层125的上方也设有像素电极图案126,进一步的,在像素电极图案126下方与彩色滤光图案和黑矩阵图案122之间还设有第二钝化层134,彩色滤光图案121与黑矩阵图案122间隔设置(彩色滤光图案121与黑矩阵图案122以互补或近似互补的形状设置)。在像素单元12的非显示区域II内,不设置与显示区域I内连续的彩色滤光图案121,黑矩阵图案122直接覆盖整个非显示区域II,在第一通孔131、第二通孔132和第三通孔135区域(图3中未示出该三个通孔区域下方的漏极图案131等相关元件,请参阅图2所示)等通孔位置处可选不设置黑矩阵材料,由于在非显示区域II内并未设置彩色滤光图案121,使得该区域的黑矩阵图案122较现有技术能够形成较厚的黑矩阵图案,能够有效防止该区域的漏光,同时不影响显示区域I内的透光效果,进而降低了后续显示时的暗态亮度,提高对比度,以改善显示品质。
请参阅图4,图4是本发明提供的一种显示装置一实施方式的结构示意图。如图4所示,该显示装置40包括上述实施方式中的彩膜阵列基板10、彩膜基板41和位于彩膜阵列基板10与彩膜基板41之间的液晶层42。由于显示装置40包括图1、图2和图3中所示的彩膜阵列基板10,而彩膜阵列基板10包括了彩色滤光图案121和黑矩阵图案122,因此彩膜基板41上无需设置彩色滤光图案和黑矩阵图案,且彩膜阵列基板10中黑矩阵图案122在下方不设置彩色滤光图案121的情况下直接覆盖像素单元12的非显示区域II,使得该区域的黑矩阵图案122较现有技术能够形成较厚的黑矩阵图案,能够有效防止该区域的漏光,同时不影响显示区域I内的透光效果。
请参阅图5和图6,其中图5是本发明提供的一种彩膜阵列基板的制造方法一实施方式的流程示意图;图6是图5中每个步骤对应的制程示意图。其中本发明提供的一种彩膜阵列基板的制造方式是制造上述图1、图2和图3中所示的彩膜阵列基板10,本说明书使用相同的标识来标记同样的结构元件。如图5和图6所示,并结合图1、图2和图3所示,该制造方法包括以下步骤:
S1:提供一基板11。
其中,基板11可选为玻璃基板或塑料基板。进一步的,在提供基板11的同时,将基板11通过清洗或和磨砂等操作去除基板11表面的杂质,可选再通过烘干工序将基板11烘干,以提供一干净的基板11。
S2:在基板11上依次形成薄膜晶体管的栅极图案127和扫描线图案123(图6中未示出,可参阅图1)、栅极绝缘层128、半导体图案129、薄膜晶体管的源极图案130和漏极图案131及数据线图案124(图6中未示出,可参阅图1)。
其中,栅极图案127、源极图案130和漏极图案131是金属材料,扫描线图案123、数据线图案124可选是金属材料或透明导电材料,栅极绝缘层128可选是氧化硅或/和氮化硅材料,半导体图案129可选是非晶硅材料,在其他实施方式中也可选是多晶硅材料。该步骤S2与现有技术相同,通常采用光罩工序对连续的整面层材料进行图案化以获得需要的各层或各结构元件的图案,此处不再赘述。
进一步的,在形成栅极图案127时,步骤S2可选进一步形成图1所示的公共电极图案133。
S3:在薄膜晶体管的源极图案130和漏极图案121及数据线图案124上形成第一钝化层125。
其中,第一钝化层125可选采用沉积或涂布的方式形成,如采用物理气相沉积(PVD)、化学气相沉积(CVD)设备或涂布机将第一钝化层125的材料沉积或涂布形成一薄层。第一钝化层125可选是氮化硅材料。
S4:在第一钝化层125上形成彩色滤光图案121,使得彩色滤光图案121覆盖彩膜阵列基板10的透光区域I。
其中,该步骤S4的具体实现方式是:在第一钝化层125上形成彩色滤光层,通过光罩工序将该彩色滤光层进行图案化以形成彩色滤光图案121,结合图1和图3所示,使得彩色滤光图案121覆盖彩膜阵列基板10的透光区域I,具体是彩色滤光图案121位于第一钝化层125之上且铺满整个透过区域I。
其中彩色滤光层可选是红色色阻材料、绿色色阻材料或/和蓝色色阻材料。
S5:在第一钝化层125上形成与彩色滤光图案121间隔设置的黑矩阵图案122,使得黑矩阵图案122覆盖彩膜阵列基板10的非透光区域II。
可以理解的是,该步骤S5的具体实施方式是:在第一钝化层125和彩色滤光图案121上形成黑矩阵材料层,通过光罩工序将该黑矩阵材料层进行图案化以形成黑矩阵图案122,使得黑矩阵图案122覆盖彩膜阵列基板10的非透光区域II。
其中,黑矩阵图案122使用的是有机光阻材料。
其中,该制造方法进一步包括:
S6:在彩色滤光图案121和黑矩阵图案122上形成第二钝化层134。
其中,第二钝化层134可选与第一钝化层125的形成方式相同,进一步的,第二钝化层134可选是氮化硅材料。其中第二钝化层134具有增强后续像素电极图案126附着力的作用,使得像素电极图案126能够稳定、牢固地与漏极图案131连接。
S7:在第二钝化层134、黑矩阵图案122和第一钝化层125的对应漏极图案131的位置形成通孔。
其中,本步骤S7中具体是采用光罩工序在对应漏极图案131的位置形成通孔,结合图2和图6所示,该通孔在第一钝化层125为第一通孔132,在黑矩阵图案122中为第二通孔132,在第二钝化层134中为第三通孔135。
其中,为了与后续像素电极图案126进行连接,可选第一通孔131、第二通孔132和第三通孔135区域没有覆盖黑矩阵材料。
S8:在第二钝化层134上形成像素电极图案126,使得像素电极图案126通过通孔具体是第一通孔131、第二通孔132和第三通孔135与漏极图案131电连接。
其中,像素电极图案126可选是透明导电材料。
可以理解的是,像素电极图案126设置在在透光区域I和非透光区域II,在非透光区域II中用于与漏极图案131连接,在透光区域I中铺满整个透光区域,以对图4中液晶层43进行施加合适的显示灰阶电压。
区别于现有技术,本发明通过在彩膜阵列基板的基板上形成多个阵列式排布的像素单元,且每个像素单元包括透光区域及位于透光区域外围的非透光区域,像素单元进一步包括彩色滤光图案和黑矩阵图案,其中彩色滤光图案覆盖透光区域,黑矩阵图案在下方不设置彩色滤光图案的情况下直接覆盖非透光区域。与现有技术相比,本发明能够在像素单元的非透光区域形成较厚的黑矩阵图案,避免该区域的漏光,进而降低了后续显示时的暗态亮度,提高对比度,以改善显示品质。
以上所述仅为本发明的实施例,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。

Claims (10)

1.一种彩膜阵列基板,其特征在于,所述彩膜阵列基板包括基板、形成在所述基板上的多个阵列式排布的像素单元,所述像素单元包括透光区域及位于所述透光区域外围的非透光区域,所述像素单元进一步包括彩色滤光图案和黑矩阵图案,其中所述彩色滤光图案覆盖所述透光区域,所述黑矩阵图案在下方不设置所述彩色滤光图案的情况下直接覆盖所述非透光区域。
2.根据权利要求1所述的彩膜阵列基板,其特征在于,所述黑矩阵图案是有机光阻材料。
3.根据权利要求1所述的彩膜阵列基板,其特征在于,所述像素单元进一步包括薄膜晶体管、扫描线图案、数据线图案、第一钝化层和像素电极图案,所述薄膜晶体管的栅极图案和源极图案分别与所述扫描线图案和所述数据线图案连接,所述像素电极图案位于所述第一钝化层上部,所述第一钝化层上设有第一通孔,所述薄膜晶体管的漏极图案通过所述第一通孔与所述像素电极图案连接,所述黑矩阵图案与所述薄膜晶体管、所述扫描线图案和所述数据线图案对应设置,且直接接触所述第一钝化层。
4.根据权利要求3所述的彩膜阵列基板,其特征在于,所述黑矩阵图案设置在所述第一钝化层上。
5.根据权利要求4所述的彩膜阵列基板,其特征在于,所述黑矩阵图案在所述第一通孔的位置也设有第二通孔,用于所述薄膜晶体管的漏极图案通过所述第一通孔、所述第二通孔与所述像素电极图案连接。
6.根据权利要求5所述的彩膜阵列基板,其特征在于,所述像素单元进一步包括第二钝化层,所述第二钝化层位于所述黑矩阵图案和所述像素电极图案之间,所述第二钝化层上设有第三通孔,用于所述薄膜晶体管的漏极图案通过所述第一通孔、所述第二通孔和所述第三通孔与所述像素电极图案连接。
7.根据权利要求3所述的彩膜阵列基板,其特征在于,所述黑矩阵图案设置在所述第一钝化层与所述基板之间。
8.一种显示装置,其特征在于,所述显示装置包括权利1至7任意一项所述的彩膜阵列基板。
9.一种彩膜阵列基板的制造方法,其特征在于,所述制造方法包括以下步骤:
提供一基板;
在所述基板上依次形成薄膜晶体管的栅极图案和扫描线图案、栅极绝缘层、半导体层图案、所述薄膜晶体管的源极图案和漏极图案及数据线图案;
在所述薄膜晶体管的源极图案和漏极图案及所述数据线图案上形成第一钝化层;
在所述第一钝化层上形成彩色滤光图案,使得所述彩色滤光图案覆盖所述彩膜阵列基板的透光区域;
在所述第一钝化层上形成与所述彩色滤光图案间隔设置的黑矩阵图案,使得所述黑矩阵图案覆盖所述彩膜阵列基板的非透光区域。
10.据权利要求9所述的制造方法,其特征在于,所述制造方法进一步包括以下步骤:
在所述彩色滤光图案和所述黑矩阵图案上形成第二钝化层;
在所述第二钝化层、所述黑矩阵图案和所述第一钝化层的对应所述漏极图案的位置形成通孔;
在所述第二钝化层上形成像素电极图案,使得所述像素电极图案通过所述通孔与所述漏极图案电连接。
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