CN110854139A - 一种tft阵列基板、其制备方法及其显示面板 - Google Patents

一种tft阵列基板、其制备方法及其显示面板 Download PDF

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CN110854139A
CN110854139A CN201911172589.2A CN201911172589A CN110854139A CN 110854139 A CN110854139 A CN 110854139A CN 201911172589 A CN201911172589 A CN 201911172589A CN 110854139 A CN110854139 A CN 110854139A
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layer
array substrate
insulating layer
tft array
inorganic insulating
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艾飞
宋德伟
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Wuhan China Star Optoelectronics Technology Co Ltd
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Abstract

本发明提供了一种TFT阵列基板、其制备方法及其显示面板。其中所述TFT阵列基板，其包括基板。所述基板上依次设置有缓冲层和TFT功能层。其中所述TFT功能层包括依次设置在所述缓冲层上的有源层(Active)、栅极绝缘层(GI)、栅极层(GE)、层间绝缘层(ILD)和源漏极层(SD)。其中所述源漏极层上设置有无机绝缘层，所述无机绝缘层上还依次设置有BITO层、钝化层(PV)和TITO层。本发明提供了一种TFT阵列基板，其采用新型的功能层结构设计，能够有效的降低了所述TFT阵列(Array)基板的生产成本和周期。

Description

一种TFT阵列基板、其制备方法及其显示面板
技术领域
本发明涉及用于平面显示面板技术领域，尤其是，其中涉及的一种阵列基板、其制备方法及其显示面板。
背景技术
已知，随着显示技术的不断发展，平面显示技术已取代了CRT(Cathode Ray Tube)显示技术成为主流显示技术。
其中液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
特别是，其中的LTPS(Low Temperature Poly-silicon)低温多晶硅显示技术，由于其较的高载流子迁移率可以使晶体管获得更高的开关电流比，在满足要求的充电电流条件下，每个像素晶体管可以更加小尺寸化，增加每个像素透光区，提高面板开口率，改善面板亮点和高分辨率，降低面板功耗，从而获得更好的视觉体验。
然而，由于液晶显示器是一种靠电场来调节液晶分子的排列状态，从而实现光通量调制的被动型显示器件，需要精细的有源驱动矩阵(Array)配合各像素区液晶的偏转状况。
鉴于LTPS低温多晶硅有源矩阵朝着不断缩小特征尺寸方向发展，随之而来的光刻技术进步导致了设备成本以指数增长。因此，确有必要来开发一种新型的TFT阵列基板，来克服现有技术中的缺陷。
发明内容
本发明的一个方面是提供一种TFT阵列基板，其采用新型的功能层结构设计，能够有效的降低了所述TFT阵列(Array)基板的生产成本和周期。
本发明采用的技术方案如下：
一种TFT阵列基板，其包括基板。所述基板上依次设置有缓冲层和TFT功能层。其中所述TFT功能层包括依次设置在所述缓冲层上的有源层(Active)、栅极绝缘层(GI)、栅极层(GE)、层间绝缘层(ILD)和源漏极层(SD)。其中所述源漏极层上设置有无机绝缘层(IL，Insulating layer)，所述无机绝缘层上还依次设置有BITO(Back side Indium TinOxides)层、钝化层(PV)和TITO(Top-Indium Tin Oxides)层。
进一步的，在不同实施方式中，其中所述源漏极层上方设置的所述BITO层中设置有第一贯穿开槽，所述钝化层会向下填充所述第一贯穿开槽并与所述无机绝缘层表面相接。
进一步的，在不同实施方式中，其中所述第一贯穿开槽的宽度小于或是等于设置在其下方的所述源漏极层的宽度。
进一步的，在不同实施方式中，其中所述无机绝缘层采用的材料包括SiN和/或SiO，具体可随需要而定，并无限定。
进一步的，在不同实施方式中，其中所述阵列基板为LTPS型阵列基板。
进一步的，在不同实施方式中，其中所述缓冲层内设置有遮光层。
进一步的，在不同实施方式中，其中所述有源层采用的材质为低温多晶硅材质(Poly-Si)。
进一步的，本发明的又一方面是提供一种制备本发明涉及的所述阵列基板的制备方法，其包括以下步骤：
步骤S1：在提供的基板上制备遮光层；
步骤S2：在所述基板上制备缓冲层和有源层；
步骤S3：在所述缓冲层上制备栅极绝缘层和栅极层；
步骤S4：在所述栅极绝缘层上形成层间绝缘层；
步骤S5：在所述层间绝缘层上形成源漏极层；
步骤S6：在所述层间绝缘层上形成无机绝缘层，在所述无机绝缘层上形成BITO层；
步骤S7：在所述无机绝缘层上形成钝化层；以及
步骤S8：在所述钝化层上形成TITO层。
进一步的，在不同实施方式中，其中在所述步骤S6中，在形成所述BITO层后，还会对位于所述源漏极层上方的BITO层进行贯穿开槽处理以形成一第一贯穿开槽，而在所述步骤S7中，形成的所述钝化层会向下填充所述第一贯穿开槽并与所述无机绝缘层表面相接。
进一步的，本发明的又一方面是提供一种显示面板，其包括本发明涉及的所述阵列基板。
进一步的，在不同实施方式中，其中所述显示面板为LCD显示面板。
进一步的，在不同实施方式中，其中所述阵列基板中的源漏极(SD)层用作Data走线，而其上方设置的所述BITO层用作Com电极。其中所述BITO层通过采用设置第一贯穿开槽的结构方式，能够有效地降低其与下方对应设置的所述源漏极层间的耦合电容数值，从而能够避免所述显示面板可能出现的Crosstalk、重载画异等光学问题，进而优化了产品设计，提升了所述显示面板的光学性能。
进一步的，在不同实施方式中，其中设置在所述源漏极层上方的所述BITO层中的第一贯穿开槽，其位于设置在所述显示面板内相邻两条Gate走线之间。
相对于现有技术，本发明的有益效果是：本发明涉及的一种TFT阵列基板，其采用新型的功能层结构设计，其用于隔开所述源漏极层和BITO层的结构，不在是设置业界一般常用的平坦层(PLN)，而是采用无机绝缘层的结构，从而使其整个制备工艺制程中减少了其中的平坦层光罩(Mask)工艺，因此，相应的简化了其制程工艺，从而降低了本发明涉及的所述TFT阵列(array)基板的生产成本和周期。
进一步的，本发明涉及的所述TFT阵列基板，其位于所述源漏极(SD)层上方的对应的BITO层采用了新型结构设计，即通过对所述BITO层进行内部开槽的结构设计，来有效的降低分别作为Data走线的所述源漏极层与作为Com电极的所述BITO层之间的耦合(Couple)电容数值，从而避免了其所在显示面板可能出现的Crosstalk、重载画异等光学问题，进而优化了产品设计，提升了其所在显示面板的光学性能。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术的TFT阵列基板的结构示意图；
图2为本发明涉及的一种TFT阵列基板的制备方法，其步骤S1完成后的结构示意图；
图3为图1所述的制备方法，其步骤S2完成后的结构示意图；
图4为图1所述的制备方法，其步骤S3完成后的结构示意图；
图5为图1所述的制备方法，其步骤S4完成后的结构示意图；
图6为图1所述的制备方法，其步骤S5完成后的结构示意图；
图7为图1所述的制备方法，其步骤S6完成后的结构示意图；
图8为图1所述的制备方法，其步骤S7完成后的结构示意图；
图9为图1所述的制备方法，其步骤S8完成后的结构示意图；以及
图10为本发明涉及的一种显示面板，其局部结构的平面透视示意图。
具体实施方式
以下将结合附图和实施例，对本发明涉及的一种TFT阵列基板、其制备方法及其显示面板的技术方案作进一步的详细描述。
由于本发明同时涉及所述TFT阵列基板的结构及其制备方法，因此，为避免不必要的赘述，以下将结以本发明涉及的所述TFT阵列基板的制备方法来对本发明涉及的所述TFT阵列基板的结构进行说明。
本发明的一个实施方式提供了一种本发明涉及的TFT阵列基板的制备方法，其包括以下步骤。
步骤S1：在提供的基板(Glass)100上沉积遮光(Light Shielding，LS)层101，然后刻蚀出所述遮光层101图案，完成后的结构图示请参阅图2所示。
步骤S2：在所述基板100上沉积形成缓冲(BL)层102后，沉积有源层103，其采用的材料为a-Si，对其进行激光镭射退火，然后在经过PHO/Dry/STR工艺后，形成所述有源层103的Poly-Si图案，完成后的结构图示请参阅图3所示。
步骤S3：在所述缓冲层102上沉积栅极绝缘层(GI)104以及其上设置的栅极层(GE)105，采用业界常用的Re-etch工艺技术，对所述栅极层105进行图形化，以及所述有源层103的源漏重掺杂和LDD的形成，完成后的结构图示请参阅图4所示。
步骤S4：在所述栅极绝缘层上沉积层间介质层(ILD)106，并通过业界常用的PHO/Dry/STR工艺对其进行图形化处理从而形成其中的过孔图案，完成后的结构图示请参阅图5所示。
步骤S5：在所述层间介质层上沉积源漏极(SD)层107，并通过业界常用的PHO/Dry/STR在所述源漏极上形成SD孔图案，完成后的结构图示请参阅图6所示。
步骤S6：在所述层间绝缘层106上沉积无机绝缘(IL)层108以及后进行ITO材料的沉积，其中对所述ITO材质层经过业界常规的PHO/Dry/STR图形化处理后，使其成为BITO层110，也就是通常上的公共电极(Com ITO)同时在所述源漏极层上方的BITO层110形成有第一贯穿开槽112和第二贯穿开槽114，完成后的结构图示请参阅图7所示。
步骤S7：在所述无机绝缘层上沉积钝化(PV)层109，然后经过业界常规的PHO/Dry/STR工艺对其的图形化处理，完成其中的分别直达所述源漏极层107和BITO层110的相应开孔，其中一个对应所述源漏极层的开孔会贯穿所述第二贯穿开槽114，而所述第一贯穿开槽112处则由所述钝化层109向下填充，完成后的结构图示请参阅图8所示。
步骤S8：在所述钝化层109上继续沉积ITO材料，通过对其进行业界常规的PHO/Dry/STR工艺图形化处理后，使其成为TITO层120，也就是通常上的像素电极(Pixel ITO)。至此，本发明涉及的所述TFT阵列基板的整个制程完成，而本发明涉及的所述TFT阵列基板的整体结构图示也请参阅图9所示。
其中由于本发明涉及的所述TFT阵列基板，其采用了使用无机绝缘层来代替常规的由有机光阻材料构成的平坦层(PLN)的结构设计(参阅图1的现有技术结构)，因此，使得其整个制程相对于现有的9光罩(Mask)工艺制程，缩减为8光罩(Mask)工艺制程，也就是本发明涉及的所述制备方法中的8个步骤。如此，即简化了本发明涉及的所述TFT阵列基板的整个制备工艺制程，同时又降低了本发明涉及的所述阵列基板的生产成本和周期。
进一步的，本发明的又一实施方式提供了一种显示面板，其采用本发明涉及的所述TFT阵列基板。
其中所述阵列基板中的源漏极(SD)层107用作所述显示面板中的Data走线，而其上方设置的所述BITO层110用作所述显示面板的Com电极。其中由于所述BITO层110中设置有第一贯穿开槽112，从而能够有效地降低其与下方对应设置的所述源漏极层107间的耦合电容数值，进而能够避免所述显示面板可能出现的Crosstalk、重载画异等光学问题，如此既优化了产品设计，又提升了所述显示面板的光学性能。
进一步的，其中设置在所述源漏极层107上方的所述BITO层110的所述第一贯穿开槽112，其位于设置在所述显示面板内相邻两条Gate走线130之间，也就是说，所述第一贯穿开槽112的长度小于相邻两条Gate走线间的距离，具体结构图示请参阅图10所示。
其中如图9中所示，所述BITO层110为整层结构设置，为便于显示其与第一贯穿开槽112的下方设置的源漏极层107间的位置关系，进而显露出其下方对应设置的源漏极层107，第一贯穿开槽112其位于设置在所述显示面板内相邻两条Gate走线130之间对其进行了透视展示。进一步的，图9中也图示了上述第二贯穿开槽114的位置，其位于对应其上方的TITO层的位置处，以便所述TITO层130向下形成触控电极的连接。
本发明的技术范围不仅仅局限于上述说明中的内容，本领域技术人员可以在不脱离本发明技术思想的前提下，对上述实施例进行多种变形和修改，而这些变形和修改均应当属于本发明的范围内。

Claims (10)

1.一种TFT阵列基板，其包括基板；所述基板上依次设置有缓冲层和TFT功能层，其中所述TFT功能层包括依次设置在所述缓冲层上的有源层、栅极绝缘层、栅极层、层间绝缘层和源漏极层；其特征在于，其中所述源漏极层上设置有无机绝缘层，所述无机绝缘层上还依次设置有BITO层、钝化层和TITO层；
其中，所述源漏极层上方设置的所述BITO层中设置有第一贯穿开槽，所述钝化层会向下填充所述第一贯穿开槽并与所述无机绝缘层表面相接。
2.根据权利要求1所述的TFT阵列基板；其特征在于，其中所述第一贯穿开槽的宽度小于或是等于设置在其下方的所述源漏极层的宽度。
3.根据权利要求1所述的TFT阵列基板；其特征在于，其中所述无机绝缘层采用的材料包括SiN和/或SiO。
4.根据权利要求1所述的TFT阵列基板；其特征在于，其中所述钝化层中设置有第二贯穿开槽，所述第二贯穿开槽贯穿所述钝化层以及部分所述无机绝缘层直至所述源漏极层的表面，所述TITO层通过所述第二贯穿开槽连接所述源漏极层。
5.根据权利要求1所述的TFT阵列基板；其特征在于，其中所述TFT阵列基板为LTPS型TFT阵列基板。
6.一种制备根据权利要求1所述的TFT阵列基板的制备方法；其特征在于，其包括以下步骤：
步骤S1：在提供的基板上制备遮光层；
步骤S2：在所述基板上制备缓冲层和有源层；
步骤S3：在所述缓冲层上制备栅极绝缘层和栅极层；
步骤S4：在所述栅极绝缘层上形成层间绝缘层；
步骤S5：在所述层间绝缘层上形成源漏极层；
步骤S6：在所述层间绝缘层上形成无机绝缘层，在所述无机绝缘层上形成BITO层；
步骤S7：在所述无机绝缘层上形成钝化层；以及
步骤S8：在所述钝化层上形成TITO层。
7.根据权利要求5所述的制备方法；其特征在于，其中在所述步骤S6中，在形成所述BITO层后，还会对位于所述源漏极层上方的BITO层进行贯穿开槽处理以形成一第一贯穿开槽；而在所述步骤S7中，形成的所述钝化层会向下填充所述第一贯穿开槽并与所述无机绝缘层表面相接。
8.一种显示面板；其特征在于，包括根据权利要求1所述的TFT阵列基板。
9.根据权利要求7所述的显示面板；其特征在于，其中所述TFT阵列基板上设置的所述源漏极层上方设置的所述BITO层中设置有第一贯穿开槽，所述钝化层会向下填充所述第一贯穿开槽并与所述无机绝缘层表面相接；
其中所述阵列基板中的所述源漏极层用作Data走线，而其上方设置的所述BITO层用作Com电极。
10.根据权利要求8所述的显示面板；其特征在于，其中所述第一贯穿开槽是位于设置在所述显示面板内相邻两条Gate走线之间。
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