WO2021103157A1 - 一种 tft 阵列基板、其制备方法及其显示面板 - Google Patents

一种 tft 阵列基板、其制备方法及其显示面板 Download PDF

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Publication number
WO2021103157A1
WO2021103157A1 PCT/CN2019/124855 CN2019124855W WO2021103157A1 WO 2021103157 A1 WO2021103157 A1 WO 2021103157A1 CN 2019124855 W CN2019124855 W CN 2019124855W WO 2021103157 A1 WO2021103157 A1 WO 2021103157A1
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Prior art keywords
layer
insulating layer
array substrate
tft array
source
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PCT/CN2019/124855
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English (en)
French (fr)
Inventor
艾飞
宋德伟
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武汉华星光电技术有限公司
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Priority to US16/757,175 priority Critical patent/US20210408080A1/en
Publication of WO2021103157A1 publication Critical patent/WO2021103157A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
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    • G02F2202/104—Materials and properties semiconductor poly-Si

Definitions

  • This application relates to the technical field of display panels, and relates to an array substrate, a preparation method thereof, and a display panel thereof.
  • CRT Cathode Ray Tube
  • liquid crystal displays Liquid Crystal Display, LCD
  • LCD liquid crystal display
  • other flat display devices are widely used in mobile phones, TVs, personal digital assistants, digital cameras,
  • Various consumer electronic products such as notebook computers and desktop computers have become the mainstream of display devices.
  • the LTPS Low Temperature Poly-silicon
  • the transistor Due to its relatively high carrier mobility, the transistor can obtain a higher switching current ratio. Under the condition of meeting the required charging current, each pixel transistor can be smaller in size and increase The light-transmitting area of each pixel increases the aperture ratio of the panel, improves the bright spots and high resolution of the panel, reduces the power consumption of the panel, and obtains a better visual experience.
  • liquid crystal display is a passive display device that relies on an electric field to adjust the arrangement of liquid crystal molecules to achieve light flux modulation
  • a fine active drive matrix (Array) is required to match the deflection of the liquid crystal in each pixel area.
  • One aspect of the present invention is to provide a TFT array substrate, which adopts a novel functional layer structure design, which can effectively reduce the production cost and cycle of the TFT array (Array) substrate.
  • a TFT array substrate includes a substrate.
  • a buffer layer and a TFT functional layer are sequentially arranged on the substrate.
  • the TFT functional layer includes an active layer (Active), a gate insulating layer (GI), a gate layer (GE), an interlayer insulating layer (ILD) and a source and drain layer which are sequentially arranged on the buffer layer (SD).
  • the source drain layer is provided with an inorganic insulating layer (IL, Insulating layer)
  • the inorganic insulating layer is further provided with a BITO (Back side Indium Tin Oxides) layer, a passivation layer (PV) and a TITO (Top-Indium Tin Oxides) layer in sequence. Oxides) layer.
  • the passivation layer will fill the first through slot downward and be in contact with The surface of the inorganic insulating layer is in contact with each other.
  • the width of the first through slot is less than or equal to the width of the source and drain layer disposed thereunder.
  • the material used for the inorganic insulating layer includes SiN and/or SiO, which can be specifically determined as required and is not limited.
  • the array substrate is an LTPS type array substrate.
  • a light-shielding layer is provided in the buffer layer.
  • the material used for the active layer is a low-temperature polysilicon material (Poly-Si).
  • another aspect of the present invention is to provide a method for preparing the array substrate related to the present invention, which includes the following steps: Step S1: preparing a light-shielding layer on the provided substrate; Step S2: on the substrate Step S3: Prepare a gate insulating layer and a gate layer on the buffer layer; Step S4: Form an interlayer insulating layer on the gate insulating layer; Step S5: Prepare a gate insulating layer on the gate insulating layer; Forming a source and drain layer on the interlayer insulating layer; step S6: forming an inorganic insulating layer on the interlayer insulating layer, and forming a BITO layer on the inorganic insulating layer; step S7: forming on the inorganic insulating layer A passivation layer; and step S8: forming a TITO layer on the passivation layer.
  • the BITO layer located above the source and drain layer is further subjected to a through-grooving process to form a first through-hole Grooving, and in the step S7, the passivation layer formed will fill the first penetrating groove downwards and be in contact with the surface of the inorganic insulating layer.
  • Another aspect of the present invention is to provide a display panel, which includes the array substrate related to the present invention.
  • the display panel is an LCD display panel.
  • the source/drain (SD) layer in the array substrate is used as a Data trace
  • the BITO layer provided above it is used as a Com electrode.
  • the BITO layer can effectively reduce the value of the coupling capacitance between the BITO layer and the source and drain layers provided below by adopting the structure of the first through slot, so as to avoid the possible crosstalk of the display panel. , Heavy-duty painting and other optical problems, thereby optimizing the product design, and improving the optical performance of the display panel.
  • the first through slot in the BITO layer provided above the source and drain layer is located between two adjacent gate traces provided in the display panel .
  • a TFT array substrate related to the present invention adopts a new functional layer structure design, which is used to separate the structure of the source drain layer and the BITO layer.
  • the flat layer (PLN) commonly used in the industry is provided, but the structure of an inorganic insulating layer is adopted, so that the flat layer mask (Mask) process is reduced in the entire manufacturing process, and therefore, the manufacturing process is simplified accordingly Process, thereby reducing the production cost and cycle of the TFT array substrate involved in the present invention.
  • the corresponding BITO layer above the source and drain (SD) layer adopts a new structure design, that is, the structure design of the BITO layer is internally slotted.
  • the beneficial effects of this application are: dequantize the image compressed data based on integer dequantization factors to obtain dequantized data, and then perform DCT inverse transformation on the dequantized data based on shift operations and addition operations to obtain image data, so that the image can be dequantized.
  • DCT inverse transformation on the dequantized data based on shift operations and addition operations to obtain image data, so that the image can be dequantized.
  • There are no floating-point operations and multiplication operations in the compression process which effectively improves the processing efficiency of decompression and ensures real-time processing of decompression.
  • FIG. 1 is a schematic diagram of the structure of a TFT array substrate in the prior art
  • FIG. 2 is a schematic diagram of a method for preparing a TFT array substrate according to the present invention, after step S1 is completed;
  • Fig. 3 is a schematic diagram of the structure of the preparation method described in Fig. 1 after step S2 is completed;
  • step S3 is completed;
  • FIG. 5 is a schematic diagram of the structure of the preparation method described in FIG. 1 after step S4 is completed;
  • Fig. 6 is a schematic diagram of the structure of the preparation method described in Fig. 1 after step S5 is completed;
  • FIG. 7 is a schematic diagram of the structure of the preparation method described in FIG. 1 after step S6 is completed;
  • Fig. 8 is a schematic diagram of the structure of the preparation method described in Fig. 1 after step S7 is completed;
  • Fig. 9 is a schematic structural diagram of the preparation method described in Fig. 1 after step S8 is completed.
  • FIG. 10 is a perspective schematic diagram of a partial structure of a display panel according to the present invention.
  • connection should be understood in a broad sense, for example, it can be a support connection or a detachable connection. Connected or integrally connected; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication between two components.
  • connection should be understood in a broad sense, for example, it can be a support connection or a detachable connection. Connected or integrally connected; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication between two components.
  • An embodiment of the present invention provides a method for preparing the TFT array substrate of the present invention, which includes the following steps.
  • Step S1 Deposit a light shielding (LS) layer 101 on the provided substrate (Glass) 100, and then etch the pattern of the light shielding layer 101. Please refer to FIG. 2 for the completed structure diagram.
  • LS light shielding
  • Step S2 After the buffer (BL) layer 102 is deposited on the substrate 100, the active layer 103 is deposited, the material used is a-Si, laser laser annealing is performed, and then the active layer 103 is subjected to a PHO/Dry/STR process After that, the Poly-Si pattern of the active layer 103 is formed. Please refer to FIG. 3 for the completed structure diagram.
  • Step S3 Depositing a gate insulating layer (GI) 104 and a gate layer (GE) 105 disposed on the buffer layer 102, and using a Re-etch process technology commonly used in the industry to process the gate layer 105
  • GI gate insulating layer
  • GE gate layer
  • Step S4 Depositing an interlayer dielectric layer (ILD) 106 on the gate insulating layer, and patterning it through a PHO/Dry/STR process commonly used in the industry to form a via pattern therein, and the completed structure Please refer to Figure 5 for an illustration.
  • ILD interlayer dielectric layer
  • Step S5 Deposit a source and drain (SD) layer 107 on the interlayer dielectric layer, and form SD hole patterns on the source and drain through PHO/Dry/STR commonly used in the industry. Please refer to the completed structure diagram Refer to Figure 6.
  • SD source and drain
  • Step S6 Depositing an inorganic insulating (IL) layer 108 on the interlayer insulating layer 106 and then depositing an ITO material, wherein the ITO material layer is subjected to a conventional PHO/Dry/STR patterning process in the industry to make It becomes the BITO layer 110, that is, the common electrode (Com ITO) in general.
  • the BITO layer 110 above the source and drain layer is formed with a first through slot 112 and a second through slot 114, the completed structure Please refer to Figure 7 for an illustration.
  • Step S7 Depositing a passivation (PV) layer 109 on the inorganic insulating layer, and then patterning it through a conventional PHO/Dry/STR process in the industry to complete the process directly to the source and drain layers 107 and The corresponding openings of the BITO layer 110, one of the openings corresponding to the source and drain layers penetrates the second through slot 114, and the first through slot 112 is directed by the passivation layer 109 Underfill, please refer to Figure 8 for the completed structure diagram.
  • PV passivation
  • Step S8 Continue to deposit ITO material on the passivation layer 109, and make it into the TITO layer 120, which is the usual pixel electrode (Pixel ITO). So far, the entire manufacturing process of the TFT array substrate related to the present invention is completed, and the overall structure diagram of the TFT array substrate related to the present invention is also shown in FIG. 9.
  • the TFT array substrate involved in the present invention uses an inorganic insulating layer instead of a conventional planar layer (PLN) composed of organic photoresist materials (refer to the prior art structure in FIG. 1), .
  • PPN planar layer
  • the entire manufacturing process is reduced to an 8-mask (Mask) process, that is, 8 steps in the manufacturing method involved in the present invention.
  • the entire manufacturing process of the TFT array substrate related to the present invention is simplified, and at the same time, the production cost and cycle of the array substrate related to the present invention are reduced.
  • another embodiment of the present invention provides a display panel, which adopts the TFT array substrate related to the present invention.
  • the source and drain (SD) layer 107 in the array substrate is used as the Data trace in the display panel, and the BITO layer 110 provided above it is used as the Com electrode of the display panel.
  • the BITO layer 110 is provided with the first penetrating slot 112, it can effectively reduce the value of the coupling capacitance between it and the source and drain layer 107 provided below, thereby avoiding the possibility of the display panel.
  • Optical problems such as crosstalk, heavy-duty painting, etc., which not only optimize the product design, but also improve the optical performance of the display panel.
  • first through slot 112 of the BITO layer 110 disposed above the source and drain layer 107 is located between two adjacent gate traces 130 disposed in the display panel, In other words, the length of the first through slot 112 is less than the distance between two adjacent gate wires. Please refer to FIG. 10 for the specific structure diagram.
  • the BITO layer 110 is arranged in a whole layer structure, in order to facilitate the display of the positional relationship between it and the source and drain layer 107 arranged under the first through slot 112, thereby revealing the corresponding underneath.
  • the source and drain layers 107 are provided, and the first penetrating slot 112 is located between two adjacent Gate wires 130 provided in the display panel, which is a perspective display.
  • FIG. 9 also illustrates the position of the second through slot 114 described above, which is located at a position corresponding to the TITO layer above it, so that the TITO layer 130 forms a touch electrode connection downward.

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Abstract

一种TFT阵列基板、其制备方法及其显示面板。其中所述TFT阵列基板，其包括基板(100)。所述基板(100)上依次设置有缓冲层(102)和TFT功能层。其中所述TFT功能层包括依次设置在所述缓冲层上的有源层(Active) (103)、栅极绝缘层(GI) (104)、栅极层(GE) (105)、层间绝缘层(ILD) (106)和源漏极层(SD) (107)。其中所述源漏极层(107)上设置有无机绝缘层(108)，所述无机绝缘层(108)上还依次设置有BITO层(110)、钝化层(PV) (109)和TITO(120)层。由此提供了一种TFT阵列基板，其采用新型的功能层结构设计，能够有效的降低了所述TFT阵列(Array)基板的生产成本和周期。

Description

一种TFT阵列基板、其制备方法及其显示面板
本申请要求于2019年11月26日提交中国专利局、申请号为201911172589.2、发明名称为“一种TFT阵列基板、其制备方法及其显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示面板技术领域，其中涉及的一种阵列基板、其制备方法及其显示面板。
 背景技术
已知，随着显示技术的不断发展，平面显示技术已取代了CRT（Cathode Ray Tube）显示技术成为主流显示技术。
其中液晶显示器（Liquid Crystal Display，LCD）等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
特别是，其中的LTPS（Low Temperature Poly-silicon）低温多晶硅显示技术，由于其较的高载流子迁移率可以使晶体管获得更高的开关电流比，在满足要求的充电电流条件下，每个像素晶体管可以更加小尺寸化，增加每个像素透光区，提高面板开口率，改善面板亮点和高分辨率，降低面板功耗，从而获得更好的视觉体验。
然而，由于液晶显示器是一种靠电场来调节液晶分子的排列状态，从而实现光通量调制的被动型显示器件，需要精细的有源驱动矩阵（Array）配合各像素区液晶的偏转状况。
鉴于LTPS低温多晶硅有源矩阵朝着不断缩小特征尺寸方向发展，随之而来的光刻技术进步导致了设备成本以指数增长。因此，确有必要来开发一种新型的TFT阵列基板，来克服现有技术中的缺陷。
 技术问题
本发明的一个方面是提供一种TFT阵列基板，其采用新型的功能层结构设计，能够有效的降低了所述TFT阵列（Array）基板的生产成本和周期。
 技术解决方案
本发明采用的技术方案如下：
一种TFT阵列基板，其包括基板。所述基板上依次设置有缓冲层和TFT功能层。其中所述TFT功能层包括依次设置在所述缓冲层上的有源层（Active）、栅极绝缘层（GI）、栅极层（GE）、层间绝缘层（ILD）和源漏极层（SD）。其中所述源漏极层上设置有无机绝缘层（IL，Insulating layer），所述无机绝缘层上还依次设置有BITO（Back side Indium Tin Oxides）层、钝化层（PV）和TITO（Top-Indium Tin Oxides）层。
进一步的，在不同实施方式中，其中所述源漏极层上方设置的所述BITO层中设置有第一贯穿开槽，所述钝化层会向下填充所述第一贯穿开槽并与所述无机绝缘层表面相接。
进一步的，在不同实施方式中，其中所述第一贯穿开槽的宽度小于或是等于设置在其下方的所述源漏极层的宽度。
进一步的，在不同实施方式中，其中所述无机绝缘层采用的材料包括SiN和/或SiO，具体可随需要而定，并无限定。
进一步的，在不同实施方式中，其中所述阵列基板为LTPS型阵列基板。
进一步的，在不同实施方式中，其中所述缓冲层内设置有遮光层。
进一步的，在不同实施方式中，其中所述有源层采用的材质为低温多晶硅材质（Poly-Si）。
进一步的，本发明的又一方面是提供一种制备本发明涉及的所述阵列基板的制备方法，其包括以下步骤：步骤S1：在提供的基板上制备遮光层；步骤S2：在所述基板上制备缓冲层和有源层；步骤S3：在所述缓冲层上制备栅极绝缘层和栅极层；步骤S4：在所述栅极绝缘层上形成层间绝缘层；步骤S5：在所述层间绝缘层上形成源漏极层；步骤S6：在所述层间绝缘层上形成无机绝缘层，在所述无机绝缘层上形成BITO层；步骤S7：在所述无机绝缘层上形成钝化层；以及步骤S8：在所述钝化层上形成TITO层。
进一步的，在不同实施方式中，其中在所述步骤S6中，在形成所述BITO层后，还会对位于所述源漏极层上方的BITO层进行贯穿开槽处理以形成一第一贯穿开槽，而在所述步骤S7中，形成的所述钝化层会向下填充所述第一贯穿开槽并与所述无机绝缘层表面相接。
进一步的，本发明的又一方面是提供一种显示面板，其包括本发明涉及的所述阵列基板。
进一步的，在不同实施方式中，其中所述显示面板为LCD显示面板。
进一步的，在不同实施方式中，其中所述阵列基板中的源漏极（SD）层用作Data走线，而其上方设置的所述BITO层用作Com电极。其中所述BITO层通过采用设置第一贯穿开槽的结构方式，能够有效地降低其与下方对应设置的所述源漏极层间的耦合电容数值，从而能够避免所述显示面板可能出现的Crosstalk、重载画异等光学问题，进而优化了产品设计，提升了所述显示面板的光学性能。
进一步的，在不同实施方式中，其中设置在所述源漏极层上方的所述BITO层中的第一贯穿开槽，其位于设置在所述显示面板内相邻两条Gate走线之间。
相对于现有技术，本发明的有益效果是：本发明涉及的一种TFT阵列基板，其采用新型的功能层结构设计，其用于隔开所述源漏极层和BITO层的结构，不在是设置业界一般常用的平坦层（PLN），而是采用无机绝缘层的结构，从而使其整个制备工艺制程中减少了其中的平坦层光罩（Mask）工艺，因此，相应的简化了其制程工艺，从而降低了本发明涉及的所述TFT阵列（array）基板的生产成本和周期。
进一步的，本发明涉及的所述TFT阵列基板，其位于所述源漏极（SD）层上方的对应的BITO层采用了新型结构设计，即通过对所述BITO层进行内部开槽的结构设计，来有效的降低分别作为Data走线的所述源漏极层与作为Com电极的所述BITO层之间的耦合（Couple）电容数值，从而避免了其所在显示面板可能出现的Crosstalk、重载画异等光学问题，进而优化了产品设计，提升了其所在显示面板的光学性能。
 有益效果
本申请的有益效果为：基于整数的反量化因素对图像压缩数据进行反量化，获得反量化数据，进而基于移位运算和加法运算对反量化数据进行DCT反变换，获得图像数据，使得图像解压缩过程中无浮点运算和乘法运算，有效提高解压缩的处理效率，保证解压缩的实时处理。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有技术的TFT阵列基板的结构示意图；
图2为本发明涉及的一种TFT阵列基板的制备方法，其步骤S1完成后的结构示意图；
图3为图1所述的制备方法，其步骤S2完成后的结构示意图；
图4为图1所述的制备方法，其步骤S3完成后的结构示意图；
图5为图1所述的制备方法，其步骤S4完成后的结构示意图；
图6为图1所述的制备方法，其步骤S5完成后的结构示意图；
图7为图1所述的制备方法，其步骤S6完成后的结构示意图；
图8为图1所述的制备方法，其步骤S7完成后的结构示意图；
图9为图1所述的制备方法，其步骤S8完成后的结构示意图；以及
图10为本发明涉及的一种显示面板，其局部结构的平面透视示意图。
 本发明的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是支撑连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
本发明的一个实施方式提供了一种本发明涉及的TFT阵列基板的制备方法，其包括以下步骤。
步骤S1：在提供的基板（Glass）100上沉积遮光（Light Shielding，LS）层101，然后刻蚀出所述遮光层101图案，完成后的结构图示请参阅图2所示。
步骤S2：在所述基板100上沉积形成缓冲（BL）层102后，沉积有源层103，其采用的材料为a-Si，对其进行激光镭射退火，然后在经过PHO/Dry/STR工艺后，形成所述有源层103的Poly-Si图案，完成后的结构图示请参阅图3所示。
步骤S3：在所述缓冲层102上沉积栅极绝缘层（GI）104以及其上设置的栅极层（GE）105，采用业界常用的Re-etch工艺技术，对所述栅极层105进行图形化，以及所述有源层103的源漏重掺杂和LDD的形成，完成后的结构图示请参阅图4所示。
步骤S4：在所述栅极绝缘层上沉积层间介质层（ILD）106，并通过业界常用的PHO/Dry/STR工艺对其进行图形化处理从而形成其中的过孔图案，完成后的结构图示请参阅图5所示。
步骤S5：在所述层间介质层上沉积源漏极（SD）层107，并通过业界常用的PHO/Dry/STR在所述源漏极上形成SD孔图案，完成后的结构图示请参阅图6所示。
步骤S6：在所述层间绝缘层106上沉积无机绝缘（IL）层108以及后进行ITO材料的沉积，其中对所述ITO材质层经过业界常规的PHO/Dry/STR图形化处理后，使其成为BITO层110，也就是通常上的公共电极（Com ITO）同时在所述源漏极层上方的BITO层110形成有第一贯穿开槽112和第二贯穿开槽114，完成后的结构图示请参阅图7所示。
步骤S7：在所述无机绝缘层上沉积钝化（PV）层109，然后经过业界常规的PHO/Dry/STR工艺对其的图形化处理，完成其中的分别直达所述源漏极层107和BITO层110的相应开孔，其中一个对应所述源漏极层的开孔会贯穿所述第二贯穿开槽114，而所述第一贯穿开槽112处则由所述钝化层109向下填充，完成后的结构图示请参阅图8所示。
步骤S8：在所述钝化层109上继续沉积ITO材料，通过对其进行业界常规的PHO/Dry/STR工艺图形化处理后，使其成为TITO层120，也就是通常上的像素电极（Pixel ITO）。至此，本发明涉及的所述TFT阵列基板的整个制程完成，而本发明涉及的所述TFT阵列基板的整体结构图示也请参阅图9所示。
其中由于本发明涉及的所述TFT阵列基板，其采用了使用无机绝缘层来代替常规的由有机光阻材料构成的平坦层（PLN）的结构设计（参阅图1的现有技术结构），因此，使得其整个制程相对于现有的9光罩（Mask）工艺制程，缩减为8光罩（Mask）工艺制程，也就是本发明涉及的所述制备方法中的8个步骤。如此，即简化了本发明涉及的所述TFT阵列基板的整个制备工艺制程，同时又降低了本发明涉及的所述阵列基板的生产成本和周期。
进一步的，本发明的又一实施方式提供了一种显示面板，其采用本发明涉及的所述TFT阵列基板。
其中所述阵列基板中的源漏极（SD）层107用作所述显示面板中的Data走线，而其上方设置的所述BITO层110用作所述显示面板的Com电极。其中由于所述BITO层110中设置有第一贯穿开槽112，从而能够有效地降低其与下方对应设置的所述源漏极层107间的耦合电容数值，进而能够避免所述显示面板可能出现的Crosstalk、重载画异等光学问题，如此 既优化了产品设计，又提升了所述显示面板的光学性能。
进一步的，其中设置在所述源漏极层107上方的所述BITO层110的所述第一贯穿开槽112，其位于设置在所述显示面板内相邻两条Gate走线130之间，也就是说，所述第一贯穿开槽112的长度小于相邻两条Gate走线间的距离，具体结构图示请参阅图10所示。
其中如图9中所示，所述BITO层110为整层结构设置，为便于显示其与第一贯穿开槽112的下方设置的源漏极层107间的位置关系，进而显露出其下方对应设置的源漏极层107 ，第一贯穿开槽112其位于设置在所述显示面板内相邻两条Gate走线130之间对其进行了透视展示。进一步的，图9中也图示了上述第二贯穿开槽114的位置，其位于对应其上方的TITO层的位置处，以便所述TITO层130向下形成触控电极的连接。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (10)

  1. 一种TFT阵列基板，其包括基板；所述基板上依次设置有缓冲层和TFT功能层，其中所述TFT功能层包括依次设置在所述缓冲层上的有源层、栅极绝缘层、栅极层、层间绝缘层和源漏极层；其特征在于，其中所述源漏极层上设置有无机绝缘层，所述无机绝缘层上还依次设置有BITO层、钝化层和TITO层；
    其中，所述源漏极层上方设置的所述BITO层中设置有第一贯穿开槽，所述钝化层会向下填充所述第一贯穿开槽并与所述无机绝缘层表面相接。
  2. 根据权利要求1所述的TFT阵列基板；其中所述第一贯穿开槽的宽度小于或是等于设置在其下方的所述源漏极层的宽度。
  3. 根据权利要求1所述的TFT阵列基板；其中所述无机绝缘层采用的材料包括SiN和/或SiO。
  4. 根据权利要求1所述的TFT阵列基板；其中所述钝化层中设置有第二贯穿开槽，所述第二贯穿开槽贯穿所述钝化层以及部分所述无机绝缘层直至所述源漏极层的表面，所述TITO层通过所述第二贯穿开槽连接所述源漏极层。
  5. 根据权利要求1所述的TFT阵列基板；其中所述TFT阵列基板为LTPS型TFT阵列基板。
  6. 一种制备根据权利要求1所述的TFT阵列基板的制备方法；其包括以下步骤：
    步骤S1：在提供的基板上制备遮光层；
    步骤S2：在所述基板上制备缓冲层和有源层；
    步骤S3：在所述缓冲层上制备栅极绝缘层和栅极层；
    步骤S4：在所述栅极绝缘层上形成层间绝缘层；
    步骤S5：在所述层间绝缘层上形成源漏极层；
    步骤S6：在所述层间绝缘层上形成无机绝缘层，在所述无机绝缘层上形成BITO层；
    步骤S7：在所述无机绝缘层上形成钝化层；以及
    步骤S8：在所述钝化层上形成TITO层。
  7. 根据权利要求5所述的制备方法；其中在所述步骤S6中，在形成所述BITO层后，还会对位于所述源漏极层上方的BITO层进行贯穿开槽处理以形成一第一贯穿开槽；而在所述步骤S7中，形成的所述钝化层会向下填充所述第一贯穿开槽并与所述无机绝缘层表面相接。
  8. 一种显示面板；，括根据权利要求1所述的TFT阵列基板。
  9. 根据权利要求7所述的显示面板；其中所述TFT阵列基板上设置的所述源漏极层上方设置的所述BITO层中设置有第一贯穿开槽，所述钝化层会向下填充所述第一贯穿开槽并与所述无机绝缘层表面相接；
    其中所述阵列基板中的所述源漏极层用作Data走线，而其上方设置的所述BITO层用作Com电极。
  10. 根据权利要求8所述的显示面板；其中所述第一贯穿开槽是位于设置在所述显示面板内相邻两条Gate走线之间。
PCT/CN2019/124855 2019-11-26 2019-12-12 一种 tft 阵列基板、其制备方法及其显示面板 WO2021103157A1 (zh)

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