CN104882414B - Tft基板的制作方法及其结构 - Google Patents

Tft基板的制作方法及其结构 Download PDF

Info

Publication number
CN104882414B
CN104882414B CN201510227679.2A CN201510227679A CN104882414B CN 104882414 B CN104882414 B CN 104882414B CN 201510227679 A CN201510227679 A CN 201510227679A CN 104882414 B CN104882414 B CN 104882414B
Authority
CN
China
Prior art keywords
semiconductor
tft
connection
layer
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510227679.2A
Other languages
English (en)
Other versions
CN104882414A (zh
Inventor
石龙强
韩佰祥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201510227679.2A priority Critical patent/CN104882414B/zh
Priority to US14/759,198 priority patent/US9673227B1/en
Priority to PCT/CN2015/079662 priority patent/WO2016176880A1/zh
Publication of CN104882414A publication Critical patent/CN104882414A/zh
Application granted granted Critical
Publication of CN104882414B publication Critical patent/CN104882414B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02565Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02631Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/04Structural and physical details of display devices
    • G09G2300/0421Structural details of the set of electrodes
    • G09G2300/043Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/04Structural and physical details of display devices
    • G09G2300/0439Pixel structures
    • G09G2300/0465Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Abstract

本发明提供一种TFT基板的制作方法及其结构。该TFT基板的制作方法采用设置于半导体层且经过N型重掺杂的连接半导体(42)连接第一半导体(41)与第二半导体(43),从而将第一TFT与第二TFT串联起来,该经过N型重掺杂的连接半导体(42)代替了现有技术中设置于第二金属层上的连接电极,避免了将连接电极与数据线、供电压线等讯号线共同设置于第二金属层所导致的连接电极与第二金属层的设计规则变小的问题,有利于提高显示面板的开口率、及分辨率。本发明还提供一种TFT基板结构,其结构简单,具有高开口率及高分辨率。

Description

TFT基板的制作方法及其结构
技术领域
本发明涉及显示技术领域,尤其涉及一种TFT基板的制作方法及其结构。
背景技术
在显示技术领域,液晶显示器(Liquid Crystal Display,LCD)与有机发光二极管显示器(Organic Light Emitting Diode,OLED)等平板显示技术已经逐步取代CRT显示器。其中,OLED具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽,可实现柔性显示与大面积全色显示等诸多优点,被业界公认为是最有发展潜力的显示装置。
OLED按照驱动类型可分为无源OLED(PMOLED)和有源OLED(AMOLED);其中,AMOLED器件为电流驱动,其对薄膜晶体管(Thin Film Transistor,TFT)电流的要求非常严格。所以,AMOLED产品必须采用像素补偿电路来减少整个驱动过程中由于TFT不稳定导致的电流变化。
现有的AMOLED像素补偿电路通常涉及到多个TFT串联,如图1所示的一种像素补偿电路,在数据线Vdata与供电压线Vdd这两条讯号线之间串联了两个TFT:TFT1与TFT2;图2为对应图1所示的像素补偿电路的TFT基板结构,图3为图2所示的TFT基板结构中TFT组件与数据线、及供电压线的分布及连接示意图。
如图2和图3所示,所述TFT基板结构包括从下到上依次设置的基板100、第一金属层、栅极绝缘层300、半导体层、刻蚀阻挡层500、及第二金属层;所述第一金属层包括间隔设置的第一栅极210、及第二栅极230;所述半导体层包括间隔设置的第一半导体420、及第二半导体440;所述第二金属层包括间隔设置的第一源极610、连接电极620、及第二漏极630。
所述刻蚀阻挡层500上设有第一通孔510、第二通孔520、第三通孔530、及第四通孔540;所述第一源极610通过第一通孔510与所述第一半导体420的一端相接触;所述连接电极620通过第二通孔520与所述第一半导体420的另外一端相接触,同时通过第三通孔530与所述第二半导体440的一端相接触;所述第二漏极630通过第四通孔540与所述第二半导体440的另外一端相接触。
所述第一栅极210、第一半导体420、第一源极610、及连接电极620构成第一TFT;所述第二栅极230、第二半导体440、连接电极620、及第二漏极630构成第二TFT。
从图2和图3中可见,所述连接电极620同时充当第一TFT的第一漏极、以及第二TFT的第二源极,从而将第一TFT与第二TFT串联起来,然而,由于该连接电极620所在的第二金属层还分布有数据线Vdata、供电压线Vdd等讯号线,使得该连接电极620的设计规则(designrule)很小,而两TFT之间再通过连接电极620桥接会导致该第二金属层的设计规则变得更小,不利于高开口率、及高分辨率的显示面板的制作。
发明内容
本发明的目的在于提供一种TFT基板的制作方法,通过采用设置于半导体层且经过N型重掺杂的连接半导体代替现有技术中设置于第二金属层上的连接电极,避免了现有设计中将连接电极与数据线、供电压线等讯号线共同设置于第二金属层所导致的连接电极与第二金属层的设计规则变小的问题,有利于高开口率、及高分辨率的显示面板的制作。
本发明的目的还在于提供一种TFT基板结构,其结构简单,具有高开口率及高分辨率。
为实现上述目的,本发明首先提供一种TFT基板的制作方法,包括如下步骤:
步骤1、提供一基板,在所述基板上沉积第一金属层,并通过一道光刻制程图案化该第一金属层,形成间隔设置的第一栅极、及第二栅极;
步骤2、在所述第一栅极、第二栅极、及基板上沉积栅极绝缘层;
步骤3、在所述栅极绝缘层上沉积一半导体层,并通过一道光刻制程对该半导体层进行图案化,形成依次排列且相互连接的第一半导体、连接半导体、及第二半导体;
所述第一半导体对应位于所述第一栅极的上方,所述第二半导体对应位于所述第二栅极的上方、所述连接半导体位于所述第一半导体与第二半导体之间;
步骤4、在所述半导体层上沉积一刻蚀阻挡层,并通过一道光刻制程在该刻蚀阻挡层上形成间隔设置的第一通孔、第二通孔、及第三通孔;
所述第一通孔、第二通孔、及第三通孔分别暴露出第一半导体相对远离连接半导体的一端、连接半导体、及第二半导体相对远离连接半导体的一端;
步骤5、以所述刻蚀阻挡层为遮挡层,分别经由所述第一通孔、第二通孔、及第三通孔对所述第一半导体相对远离连接半导体的一端、连接半导体、及第二半导体相对远离连接半导体的一端进行N型重掺杂,从而在所述第一半导体上形成第一源极接触区与第一沟道区,在所述第二半导体上形成第二沟道区与第二漏极接触区,所述连接半导体的两端分别连接第一沟道区与第二沟道区;
其中,所述第一源极接触区、连接半导体、及第二漏极接触区均为N型重掺杂区域;
步骤6、在所述刻蚀阻挡层上沉积第二金属层,并通过一道光刻制程图案化该第二金属层,形成间隔设置的第一源极、及第二漏极;
所述第一源极通过第一通孔与第一源极接触区相接触;所述第二漏极通过第三通孔与第二漏极接触区相接触;
所述第一栅极、第一半导体、第一源极、及经过N型重掺杂的连接半导体构成第一TFT;所述第二栅极、第二半导体、经过N型重掺杂的连接半导体、及第二漏极构成第二TFT;所述第一TFT与第二TFT由经过N型重掺杂的连接半导体串联起来。
所述步骤1采用物理气相沉积法沉积所述第一金属层,所述第一金属层的材料为铜、铝、或钼,所述步骤1中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程;所述步骤2采用等离子增强化学气相沉积法沉积所述栅极绝缘层,所述栅极绝缘层的材料为氧化硅或氮化硅。
所述步骤3采用物理气相沉积法沉积所述半导体层,所述半导体层的材料为金属氧化物,所述步骤3中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
所述步骤4采用化学气相沉积法沉积所述刻蚀阻挡层,所述刻蚀阻挡层的材料为氧化硅或氮化硅,所述步骤4中的光刻制程包括涂光阻、曝光、显影、干蚀刻、及去光阻制程;所述步骤5采用氢气等离子处理工艺对所述第一半导体相对远离连接半导体的一端、连接半导体、及第二半导体相对远离连接半导体的一端进行N型重掺杂。
所述步骤6采用通过物理气相沉积法沉积所述第二金属层,所述第二金属层的材料为铜、铝、或钼,所述步骤6中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
本发明还提供一种TFT基板结构,包括从下到上依次设置的:基板、第一金属层、栅极绝缘层、半导体层、刻蚀阻挡层、及第二金属层;所述第一金属层包括间隔设置的第一栅极、及第二栅极;所述半导体层包括依次排列且相互连接的第一半导体、连接半导体、及第二半导体;所述第二金属层包括间隔设置的第一源极、及第二漏极;
所述第一半导体对应位于所述第一栅极的上方,所述第二半导体对应位于所述第二栅极的上方、所述连接半导体位于所述第一半导体与第二半导体之间;所述第一半导体包括第一源极接触区、及第一沟道区;所述第二半导体包括第二沟道区、及第二漏极接触区;所述连接半导体的两端分别连接第一沟道区与第二沟道区;所述第一源极接触区、连接半导体、及第二漏极接触区均为N型重掺杂区域;
所述刻蚀阻挡层上形成有间隔设置的第一通孔、第二通孔、及第三通孔;所述第一源极通过第一通孔与第一源极接触区相接触;所述第二漏极通过第三通孔与第二漏极接触区相接触;所述第二通孔暴露出所述连接半导体;
所述第一栅极、第一半导体、第一源极、及经过N型重掺杂的连接半导体构成第一TFT;所述第二栅极、第二半导体、经过N型重掺杂的连接半导体、及第二漏极构成第二TFT;所述第一TFT与第二TFT由经过N型重掺杂的连接半导体串联起来。
所述基板为玻璃基板;所述第一金属层的材料为铜、铝、或钼。
所述栅极绝缘层的材料为氧化硅或氮化硅。
所述半导体层的材料为金属氧化物。
所述刻蚀阻挡层的材料为氧化硅或氮化硅;所述第二金属层的材料为铜、铝、或钼。
本发明的有益效果:本发明提供的一种TFT基板的制作方法,采用设置于半导体层且经过N型重掺杂的连接半导体连接第一半导体与第二半导体,从而将第一TFT与第二TFT串联起来,该经过N型重掺杂的连接半导体代替了现有技术中设置于第二金属层上的连接电极,避免了将连接电极与数据线、供电压线等讯号线共同设置于第二金属层所导致的连接电极与第二金属层的设计规则变小的问题,有利于提高显示面板的开口率、及分辨率。本发明提供的一种TFT基板结构,其结构简单,具有高开口率及高分辨率。
为了能更进一步了解本发明的特征以及技术内容,请参阅以下有关本发明的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本发明加以限制。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其它有益效果显而易见。
附图中,
图1为现有的一种像素补偿电路的电路图;
图2为对应图1所示的像素补偿电路的TFT基板结构的示意图;
图3为图2所示的TFT基板结构中TFT组件与数据线、及供电压线的分布及连接示意图;
图4为本发明的TFT基板的制作方法步骤1的示意图;
图5为本发明的TFT基板的制作方法步骤2的示意图;
图6为本发明的TFT基板的制作方法步骤3的示意图;
图7为本发明的TFT基板的制作方法步骤4的示意图;
图8为本发明的TFT基板的制作方法步骤5的示意图;
图9为本发明的TFT基板的制作方法步骤6的示意图暨本发明的TFT基板结构的剖面示意图;
图10为图9所示的TFT基板结构中TFT组件与数据线、及供电压线的分布及连接示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图4至图9,本发明首先提供一种TFT基板的制作方法,包括如下步骤:
步骤1、如图4所示,提供一基板1,在所述基板1上沉积第一金属层,并通过一道光刻制程图案化该第一金属层,形成间隔设置的第一栅极21、及第二栅极23。
优选的,所述基板1为玻璃基板。
具体地,该步骤1采用物理气相沉积法(Physical Vapor Deposition,PVD)沉积沉积所述第一金属层。优选的,所述第一金属层的材料为铜、铝、或钼。
所述光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
步骤2、如图5所示,在所述第一栅极21、第二栅极23、及基板1上沉积栅极绝缘层3。
具体地,该步骤2采用等离子增强化学气相沉积法(Plasma Enhanced ChemicalVapor Deposition,PECVD)沉积所述栅极绝缘层3。优选的,所述栅极绝缘层3的材料为氧化硅或氮化硅。
步骤3、如图6所示,在所述栅极绝缘层3上沉积一半导体层,并通过一道光刻制程对该半导体层进行图案化,形成依次排列且相互连接的第一半导体41、连接半导体42、及第二半导体43。
所述第一半导体41对应位于所述第一栅极21的上方,所述第二半导体43对应位于所述第二栅极23的上方、所述连接半导体42位于所述第一半导体41与第二半导体43之间。
具体地,该步骤3采用物理气相沉积法沉积所述半导体层。进一步地,所述半导体层的材料为金属氧化物,优选的,所述金属氧化物为铟镓锌氧化物(Indium Gallium ZincOxide,IGZO)。
所述光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
步骤4、如图7所示,在所述半导体层上沉积一刻蚀阻挡层5,并通过一道光刻制程在刻蚀阻挡层5上形成间隔设置的第一通孔51、第二通孔52、及第三通孔53。
所述第一通孔51、第二通孔52、及第三通孔53分别暴露出第一半导体41相对远离连接半导体42的一端、连接半导体42、及第二半导体43相对远离连接半导体42的一端。
具体地,该步骤4采用化学气相沉积法(Chemical Vapor Deposition,CVD)沉积所述刻蚀阻挡层5。优选的,所述刻蚀阻挡层5的材料为氧化硅或氮化硅。
所述光刻制程包括涂光阻、曝光、显影、干蚀刻、及去光阻制程。
步骤5、如图8所示,以所述刻蚀阻挡层5为遮挡层,分别经由所述第一通孔51、第二通孔52、及第三通孔53对所述第一半导体41相对远离连接半导体42的一端、连接半导体42、及第二半导体43相对远离连接半导体42的一端进行N型重掺杂,提高所述第一半导体41相对远离连接半导体42的一端、连接半导体42、及第二半导体43相对远离连接半导体42的一端的导电能力,从而在所述第一半导体41上形成第一源极接触区412与第一沟道区414,在所述第二半导体43上形成第二沟道区432与第二漏极接触区434,所述连接半导体42的两端分别连接第一沟道区414与第二沟道区432。
其中,所述第一源极接触区412、连接半导体42、及第二漏极接触区434均为N型重掺杂区域。
优选的,该步骤5采用氢气等离子(Plasma)处理工艺对所述第一半导体41相对远离连接半导体42的一端、连接半导体42、及第二半导体43相对远离连接半导体42的一端进行N型重掺杂。
步骤6、如图9所示,在所述刻蚀阻挡层5上沉积第二金属层,并通过一道光刻制程图案化该第二金属层,形成间隔设置的第一源极61、及第二漏极62;
所述第一源极61通过第一通孔51与第一源极接触区412相接触;所述第二漏极62通过第三通孔53与第二漏极接触区434相接触。
所述第一栅极21、第一半导体41、第一源极61、及经过N型重掺杂的连接半导体42构成第一TFT;所述第二栅极23、第二半导体43、经过N型重掺杂的连接半导体42、及第二漏极62构成第二TFT;所述第一TFT与第二TFT由经过N型重掺杂的连接半导体42串联起来。
具体地,该步骤6采用物理气相沉积法沉积所述第二金属层。优选的,所述第二金属层的材料为铜、铝、或钼。
所述光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
上述TFT基板的制作方法将经过N型重掺杂的连接半导体42设置于半导体层,并由所述经过N型重掺杂的连接半导体42来连接第一半导体41与第二半导体43,从而将第一TFT与第二TFT连接起来,代替了现有技术中设置于第二金属层上的连接电极,避免了将连接电极与数据线、供电压线等讯号线共同设置于第二金属层所导致的连接电极与第二金属层的设计规则变小的问题,有利于提高显示面板的开口率、及分辨率。
请参阅图9、图10,本发明还提供一种由上述制作方法制备的TFT基板结构,其包括从下到上依次设置的:基板1、第一金属层、栅极绝缘层3、半导体层、刻蚀阻挡层5、及第二金属层;所述第一金属层包括间隔设置的第一栅极21、及第二栅极23;所述半导体层包括依次排列且相互连接的第一半导体41、连接半导体42、及第二半导体43;所述第二金属层包括间隔设置的第一源极61、及第二漏极62。
所述第一半导体41对应位于所述第一栅极21的上方,所述第二半导体43对应位于所述第二栅极23的上方、所述连接半导体42位于所述第一半导体41与第二半导体43之间;所述第一半导体41包括第一源极接触区412、及第一沟道区414;所述第二半导体43包括第二沟道区432、及第二漏极接触区434;所述连接半导体42的两端分别连接第一沟道区414与第二沟道区432;所述第一源极接触区412、连接半导体42、及第二漏极接触区434均为N型重掺杂区域。
所述刻蚀阻挡层5上形成有间隔设置的第一通孔51、第二通孔52、及第三通孔53;所述第一源极61通过第一通孔51与第一源极接触区412相接触;所述第二漏极62通过第三通孔53与第二漏极接触区434相接触;所述第二通孔52暴露出所述连接半导体42。
所述第一栅极21、第一半导体41、第一源极61、及经过N型重掺杂的连接半导体42构成第一TFT;所述第二栅极23、第二半导体43、经过N型重掺杂的连接半导体42、及第二漏极62构成第二TFT;所述第一TFT与第二TFT由经过N型重掺杂的连接半导体42串联起来。
优选的,所述基板1为玻璃基板;
优选的,所述第一金属层的材料为铜、铝、或钼;
优选的,所述栅极绝缘层3的材料为氧化硅或氮化硅;
优选的,所述半导体层的材料为金属氧化物,如铟镓锌氧化物;
优选的,所述刻蚀阻挡层5的材料为氧化硅或氮化硅;
优选的,所述第二金属层的材料为铜、铝、或钼。
综上所述,本发明的TFT基板的制作方法,采用设置于半导体层且经过N型重掺杂的连接半导体连接第一半导体与第二半导体,从而将第一TFT与第二TFT串联起来,该经过N型重掺杂的连接半导体代替了现有技术中设置于第二金属层上的连接电极,避免了将连接电极与数据线、供电压线等讯号线共同设置于第二金属层所导致的连接电极与第二金属层的设计规则变小的问题,有利于提高显示面板的开口率、及分辨率。本发明的TFT基板结构,其结构简单,具有高开口率及高分辨率。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

1.一种TFT基板的制作方法,其特征在于,包括如下步骤:
步骤1、提供一基板(1),在所述基板(1)上沉积第一金属层,并通过一道光刻制程图案化该第一金属层,形成间隔设置的第一栅极(21)、及第二栅极(23);
步骤2、在所述第一栅极(21)、第二栅极(23)、及基板(1)上沉积栅极绝缘层(3);
步骤3、在所述栅极绝缘层(3)上沉积一半导体层,并通过一道光刻制程对该半导体层进行图案化,形成依次排列且相互连接的第一半导体(41)、连接半导体(42)、及第二半导体(43);
所述第一半导体(41)对应位于所述第一栅极(21)的上方,所述第二半导体(43)对应位于所述第二栅极(23)的上方、所述连接半导体(42)位于所述第一半导体(41)与第二半导体(43)之间;
步骤4、在所述半导体层上沉积一刻蚀阻挡层(5),并通过一道光刻制程在该刻蚀阻挡层(5)上形成间隔设置的第一通孔(51)、第二通孔(52)、及第三通孔(53);
所述第一通孔(51)、第二通孔(52)、及第三通孔(53)分别暴露出第一半导体(41)相对远离连接半导体(42)的一端、连接半导体(42)、及第二半导体(43)相对远离连接半导体(42)的一端;
步骤5、以所述刻蚀阻挡层(5)为遮挡层,分别经由所述第一通孔(51)、第二通孔(52)、及第三通孔(53)对所述第一半导体(41)相对远离连接半导体(42)的一端、连接半导体(42)、及第二半导体(43)相对远离连接半导体(42)的一端进行N型重掺杂,从而在所述第一半导体(41)上形成第一源极接触区(412)与第一沟道区(414),在所述第二半导体(43)上形成第二沟道区(432)与第二漏极接触区(434),所述连接半导体(42)的两端分别连接第一沟道区(414)与第二沟道区(432);
其中,所述第一源极接触区(412)、连接半导体(42)、及第二漏极接触区(434)均为N型重掺杂区域;
步骤6、在所述刻蚀阻挡层(5)上沉积第二金属层,并通过一道光刻制程图案化该第二金属层,形成间隔设置的第一源极(61)、及第二漏极(62);
所述第一源极(61)通过第一通孔(51)与第一源极接触区(412)相接触;所述第二漏极(62)通过第三通孔(53)与第二漏极接触区(434)相接触;
所述第一栅极(21)、第一半导体(41)、第一源极(61)、及经过N型重掺杂的连接半导体(42)构成第一TFT;所述第二栅极(23)、第二半导体(43)、经过N型重掺杂的连接半导体(42)、及第二漏极(62)构成第二TFT;所述第一TFT与第二TFT由经过N型重掺杂的连接半导体(42)串联起来;
所述第一TFT与第二TFT设于数据线和供电压线之间用于构成像素补偿电路。
2.如权利要求1所述的TFT基板的制作方法,其特征在于,所述步骤1采用物理气相沉积法沉积所述第一金属层,所述第一金属层的材料为铜、铝、或钼,所述步骤1中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程;所述步骤2采用等离子增强化学气相沉积法沉积所述该栅极绝缘层(3),所述栅极绝缘层(3)的材料为氧化硅或氮化硅。
3.如权利要求1所述的TFT基板的制作方法,其特征在于,所述步骤3采用物理气相沉积法沉积所述半导体层,所述半导体层的材料为金属氧化物,所述步骤3中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
4.如权利要求1所述的TFT基板的制作方法,其特征在于,所述步骤4采用化学气相沉积法沉积所述刻蚀阻挡层(5),所述刻蚀阻挡层(5)的材料为氧化硅或氮化硅,所述步骤4中的光刻制程包括涂光阻、曝光、显影、干蚀刻、及去光阻制程;所述步骤5采用氢气等离子处理工艺对所述第一半导体(41)相对远离连接半导体(42)的一端、连接半导体(42)、及第二半导体(43)相对远离连接半导体(42)的一端进行N型重掺杂。
5.如权利要求1所述的TFT基板的制作方法,其特征在于,所述步骤6采用物理气相沉积法沉积所述第二金属层,所述第二金属层的材料为铜、铝、或钼,所述步骤6中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
6.一种TFT基板结构,其特征在于,包括从下到上依次设置的:基板(1)、第一金属层、栅极绝缘层(3)、半导体层、刻蚀阻挡层(5)、及第二金属层;所述第一金属层包括间隔设置的第一栅极(21)、及第二栅极(23);所述半导体层包括依次排列且相互连接的第一半导体(41)、连接半导体(42)、及第二半导体(43);所述第二金属层包括间隔设置的第一源极(61)、及第二漏极(62);
所述第一半导体(41)对应位于所述第一栅极(21)的上方,所述第二半导体(43)对应位于所述第二栅极(23)的上方、所述连接半导体(42)位于所述第一半导体(41)与第二半导体(43)之间;所述第一半导体(41)包括第一源极接触区(412)、及第一沟道区(414);所述第二半导体(43)包括第二沟道区(432)、及第二漏极接触区(434);所述连接半导体(42)的两端分别连接第一沟道区(414)与第二沟道区(432);所述第一源极接触区(412)、连接半导体(42)、及第二漏极接触区(434)均为N型重掺杂区域;
所述刻蚀阻挡层(5)上形成有间隔设置的第一通孔(51)、第二通孔(52)、及第三通孔(53);所述第一源极(61)通过第一通孔(51)与第一源极接触区(412)相接触;所述第二漏极(62)通过第三通孔(53)与第二漏极接触区(434)相接触;所述第二通孔(52)暴露出所述连接半导体(42);
所述第一栅极(21)、第一半导体(41)、第一源极(61)、及经过N型重掺杂的连接半导体(42)构成第一TFT;所述第二栅极(23)、第二半导体(43)、经过N型重掺杂的连接半导体(42)、及第二漏极(62)构成第二TFT;所述第一TFT与第二TFT由经过N型重掺杂的连接半导体(42)串联起来;
所述第一TFT与第二TFT设于数据线和供电压线之间用于构成像素补偿电路。
7.如权利要求6所述的TFT基板结构,其特征在于,所述基板(1)为玻璃基板;所述第一金属层的材料为铜、铝、或钼。
8.如权利要求6所述的TFT基板结构,其特征在于,所述栅极绝缘层(3)的材料为氧化硅或氮化硅。
9.如权利要求6所述的TFT基板结构,其特征在于,所述半导体层的材料为金属氧化物。
10.如权利要求6所述的TFT基板结构,其特征在于,所述刻蚀阻挡层(5)的材料为氧化硅或氮化硅;所述第二金属层的材料为铜、铝、或钼。
CN201510227679.2A 2015-05-06 2015-05-06 Tft基板的制作方法及其结构 Active CN104882414B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201510227679.2A CN104882414B (zh) 2015-05-06 2015-05-06 Tft基板的制作方法及其结构
US14/759,198 US9673227B1 (en) 2015-05-06 2015-05-25 Method of manufacturing TFTs in series and connection semiconductor formed thereby
PCT/CN2015/079662 WO2016176880A1 (zh) 2015-05-06 2015-05-25 Tft基板的制作方法及其结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510227679.2A CN104882414B (zh) 2015-05-06 2015-05-06 Tft基板的制作方法及其结构

Publications (2)

Publication Number Publication Date
CN104882414A CN104882414A (zh) 2015-09-02
CN104882414B true CN104882414B (zh) 2018-07-10

Family

ID=53949854

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510227679.2A Active CN104882414B (zh) 2015-05-06 2015-05-06 Tft基板的制作方法及其结构

Country Status (3)

Country Link
US (1) US9673227B1 (zh)
CN (1) CN104882414B (zh)
WO (1) WO2016176880A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105633101A (zh) * 2016-04-01 2016-06-01 京东方科技集团股份有限公司 Tft阵列基板及其制造方法、显示装置
KR20200089794A (ko) * 2019-01-17 2020-07-28 삼성디스플레이 주식회사 표시 장치와 그의 제조 방법
CN110047849A (zh) * 2019-04-02 2019-07-23 福建华佳彩有限公司 一种Demux电路的TFT结构

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1825565A (zh) * 1999-06-04 2006-08-30 株式会社半导体能源研究所 制造发光器件的方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198379A (en) * 1990-04-27 1993-03-30 Sharp Kabushiki Kaisha Method of making a MOS thin film transistor with self-aligned asymmetrical structure
KR100292767B1 (ko) * 1992-09-25 2001-09-17 이데이 노부유끼 액정표시장치
JP3274081B2 (ja) * 1997-04-08 2002-04-15 松下電器産業株式会社 薄膜トランジスタの製造方法および液晶表示装置の製造方法
JP4076648B2 (ja) * 1998-12-18 2008-04-16 株式会社半導体エネルギー研究所 半導体装置
JP2000214800A (ja) * 1999-01-20 2000-08-04 Sanyo Electric Co Ltd エレクトロルミネッセンス表示装置
US6281552B1 (en) * 1999-03-23 2001-08-28 Semiconductor Energy Laboratory Co., Ltd. Thin film transistors having ldd regions
JP4718677B2 (ja) * 2000-12-06 2011-07-06 株式会社半導体エネルギー研究所 半導体装置及びその作製方法
KR100514181B1 (ko) * 2003-09-03 2005-09-13 삼성에스디아이 주식회사 시리즈 박막트랜지스터, 그를 이용한 능동 매트릭스유기전계발광소자 및 상기 능동 매트릭스유기전계발광소자의 제조방법
JP4246123B2 (ja) * 2004-08-02 2009-04-02 株式会社半導体エネルギー研究所 半導体集積回路の作製方法
JP4349375B2 (ja) * 2005-04-11 2009-10-21 セイコーエプソン株式会社 電気光学装置及び電子機器
US7687327B2 (en) * 2005-07-08 2010-03-30 Kovio, Inc, Methods for manufacturing RFID tags and structures formed therefrom
KR101183437B1 (ko) * 2006-06-14 2012-09-14 엘지디스플레이 주식회사 박막 트랜지스터 및 이를 이용한 유기전계발광표시장치
KR100867926B1 (ko) * 2007-06-21 2008-11-10 삼성에스디아이 주식회사 유기전계발광표시장치 및 그의 제조 방법
CN100464241C (zh) * 2007-07-03 2009-02-25 友达光电股份有限公司 液晶显示器的像素结构及其制造方法
CN101123224A (zh) * 2007-09-18 2008-02-13 友达光电股份有限公司 像素结构的制作方法
CN101308844B (zh) * 2008-07-15 2010-06-02 友达光电股份有限公司 半导体结构及其制造方法
KR102081283B1 (ko) * 2013-02-14 2020-04-16 삼성디스플레이 주식회사 박막 반도체 장치, 유기 발광 표시 장치, 및 이의 제조 방법
KR102049444B1 (ko) * 2013-05-10 2019-11-28 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 유기 발광 표시 장치 제조용 포토 마스크
CN204391121U (zh) * 2014-12-22 2015-06-10 京东方科技集团股份有限公司 一种显示装置、阵列基板及薄膜晶体管

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1825565A (zh) * 1999-06-04 2006-08-30 株式会社半导体能源研究所 制造发光器件的方法

Also Published As

Publication number Publication date
US9673227B1 (en) 2017-06-06
WO2016176880A1 (zh) 2016-11-10
US20170141127A1 (en) 2017-05-18
CN104882414A (zh) 2015-09-02

Similar Documents

Publication Publication Date Title
CN104966696B (zh) Tft基板的制作方法及其结构
US10013124B2 (en) Array substrate, touch screen, touch display device, and fabrication method thereof
CN103314431B (zh) 制造氧化物薄膜晶体管的方法和包含该晶体管的装置
CN104064688B (zh) 具有存储电容的tft基板的制作方法及该tft基板
CN104538429B (zh) Amoled背板的制作方法及其结构
CN104810382A (zh) Amoled背板的制作方法及其结构
US9685461B2 (en) Display device, array substrate and method for manufacturing the same
CN104659285A (zh) 适用于amoled的tft背板制作方法及结构
CN104977764A (zh) 一种阵列基板及其制作方法、液晶显示器
CN104952880A (zh) 双栅极tft基板的制作方法及其结构
CN106229297B (zh) Amoled像素驱动电路的制作方法
CN104966718A (zh) Amoled背板的制作方法及其结构
CN106129086B (zh) Tft基板及其制作方法
CN103887245B (zh) 一种阵列基板的制造方法
CN103839973A (zh) 有源矩阵有机发光二极管阵列基板及制作方法和显示装置
CN105470196A (zh) 薄膜晶体管、阵列基板及其制造方法、和显示装置
CN104882414B (zh) Tft基板的制作方法及其结构
CN104157608B (zh) Tft基板的制作方法及其结构
CN104022079A (zh) 薄膜晶体管基板的制造方法
CN110233156A (zh) 薄膜晶体管基板的制作方法及薄膜晶体管基板
CN106298815A (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
TW202103237A (zh) 半導體基板
CN104934444A (zh) 共平面型氧化物半导体tft基板结构及其制作方法
KR20160044168A (ko) 표시 기판 및 이의 제조 방법
CN101740604B (zh) 有源矩阵有机发光二极管像素结构及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
EXSB Decision made by sipo to initiate substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant