WO2016176880A1 - Tft基板的制作方法及其结构 - Google Patents

Tft基板的制作方法及其结构 Download PDF

Info

Publication number
WO2016176880A1
WO2016176880A1 PCT/CN2015/079662 CN2015079662W WO2016176880A1 WO 2016176880 A1 WO2016176880 A1 WO 2016176880A1 CN 2015079662 W CN2015079662 W CN 2015079662W WO 2016176880 A1 WO2016176880 A1 WO 2016176880A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
layer
gate
tft
metal layer
Prior art date
Application number
PCT/CN2015/079662
Other languages
English (en)
French (fr)
Inventor
石龙强
韩佰祥
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/759,198 priority Critical patent/US9673227B1/en
Publication of WO2016176880A1 publication Critical patent/WO2016176880A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate and a structure thereof.
  • OLED organic light emitting diodes
  • OLEDs can be classified into passive OLEDs (PMOLEDs) and active OLEDs (AMOLEDs) according to the type of driving; among them, AMOLED devices are current driven, and their requirements for thin film transistor (TFT) current are very strict. Therefore, AMOLED products must use pixel compensation circuits to reduce current variations due to TFT instability during the entire drive process.
  • PMOLEDs passive OLEDs
  • AMOLEDs active OLEDs
  • TFT thin film transistor
  • the existing AMOLED pixel compensation circuit generally involves a plurality of TFTs connected in series. As shown in FIG. 1 , a pixel compensation circuit has two TFTs connected in series between the data lines V data and the voltage supply lines V dd . : TFT1 and TFT2; FIG. 2 is a TFT substrate structure corresponding to the pixel compensation circuit shown in FIG. 1, and FIG. 3 is a schematic diagram showing the distribution and connection of the TFT component, the data line, and the voltage supply line in the TFT substrate structure shown in FIG. 2.
  • the TFT substrate structure includes a substrate 100, a first metal layer, a gate insulating layer 300, a semiconductor layer, an etch stop layer 500, and a second metal layer disposed in order from bottom to top.
  • the first metal layer includes a first gate 210 and a second gate 230 which are spaced apart;
  • the semiconductor layer includes a first semiconductor 420 and a second semiconductor 440 which are spaced apart;
  • the second metal layer includes The first source 610, the connection electrode 620, and the second drain 630 are disposed at intervals.
  • the etch barrier layer 500 is provided with a first through hole 510, a second through hole 520, a third through hole 530, and a fourth through hole 540; the first source 610 passes through the first through hole 510 and the One end of the first semiconductor 420 is in contact; the connection electrode 620 is in contact with the other end of the first semiconductor 420 through the second via 520 while passing through the third via 530 and one end of the second semiconductor 440 The second drain 630 is in contact with the other end of the second semiconductor 440 through the fourth via 540.
  • the first gate 210, the first semiconductor 420, the first source 610, and the connection electrode 620 constitute a first TFT; the second gate 230, the second semiconductor 440, the connection electrode 620, and the second drain 630 constitutes a second TFT.
  • connection electrode 620 serves as both the first drain of the first TFT and the second source of the second TFT, thereby connecting the first TFT and the second TFT in series, however,
  • the second metal layer where the connection electrode 620 is located is further distributed with signal lines V data and voltage lines V dd , so that the design rule of the connection electrode 620 is small, and the two TFTs are connected again. Bridging the electrode 620 results in a smaller design rule for the second metal layer, which is detrimental to the fabrication of a high aperture ratio, high resolution display panel.
  • An object of the present invention is to provide a method for fabricating a TFT substrate, which avoids the existing connection electrode disposed on the second metal layer in the prior art by using a N-type heavily doped connection semiconductor disposed on the semiconductor layer.
  • the connection electrode and the data line, the voltage line and the like are disposed together on the second metal layer, and the design rule of the connection electrode and the second metal layer is reduced, which is advantageous for high aperture ratio and high resolution. The production of the display panel.
  • Another object of the present invention is to provide a TFT substrate structure which has a simple structure, a high aperture ratio and a high resolution.
  • the present invention first provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer by a photolithography process to form a first gate and a second gate disposed at intervals;
  • Step 2 depositing a gate insulating layer on the first gate, the second gate, and the substrate;
  • Step 3 depositing a semiconductor layer on the gate insulating layer, and patterning the semiconductor layer by a photolithography process to form a first semiconductor, a connection semiconductor, and a second semiconductor which are sequentially arranged and connected to each other;
  • the first semiconductor is correspondingly located above the first gate
  • the second semiconductor is correspondingly located above the second gate
  • the connecting semiconductor is located between the first semiconductor and the second semiconductor
  • Step 4 depositing an etch stop layer on the semiconductor layer, and forming a first through hole, a second through hole, and a third through hole formed on the etch stop layer by a photolithography process;
  • the first through hole, the second through hole, and the third through hole respectively expose an end of the first semiconductor relatively away from the connection semiconductor, a connection semiconductor, and an end of the second semiconductor relatively far from the connection semiconductor;
  • Step 5 using the etch barrier layer as a shielding layer, respectively, connecting the first semiconductor to an end of the semiconductor connected to the semiconductor via the first via hole, the second via hole, and the third via hole, and connecting the semiconductor, and
  • the second semiconductor is N-type heavily doped away from an end connected to the semiconductor, thereby forming a first source contact region and a first channel region on the first semiconductor, and forming a second channel on the second semiconductor a second drain contact region, the two ends of the connection semiconductor are respectively connected to the first channel region and the second channel region;
  • the first source contact region, the connection semiconductor, and the second drain contact region are all N-type heavily doped regions;
  • Step 6 depositing a second metal layer on the etch barrier layer, and patterning the second metal layer by a photolithography process to form a first source and a second drain;
  • the first source is in contact with the first source contact region through the first via hole;
  • the second drain is in contact with the second drain contact region through the third via hole;
  • the first gate, the first semiconductor, the first source, and the N-type heavily doped connection semiconductor constitute a first TFT; the second gate, the second semiconductor, and an N-type heavily doped connection
  • the semiconductor and the second drain constitute a second TFT; the first TFT and the second TFT are connected in series by an N-type heavily doped connection semiconductor.
  • the first metal layer is deposited by physical vapor deposition, and the material of the first metal layer is copper, aluminum, or molybdenum.
  • the photolithography process in the step 1 includes photoresist, exposure, development, and wetness. Etching, and photoresist removal process; the step 2 deposits the gate insulating layer by plasma enhanced chemical vapor deposition, and the material of the gate insulating layer is silicon oxide or silicon nitride.
  • the step 3 is to deposit the semiconductor layer by physical vapor deposition, the material of the semiconductor layer is a metal oxide, and the photolithography process in the step 3 includes photoresisting, exposure, development, wet etching, and photoresist removal process. .
  • the step 4 is to deposit the etch barrier layer by chemical vapor deposition, the etch barrier layer is made of silicon oxide or silicon nitride, and the lithography process in the step 4 includes photoresist, exposure, development, and drying. Etching, and photoresist removal process; the step 5 is performed by a hydrogen plasma treatment process to N-type heavily doped the end of the first semiconductor relatively far from the connection semiconductor, the connection semiconductor, and the end of the second semiconductor relatively far from the connection semiconductor.
  • the step 6 is to deposit the second metal layer by physical vapor deposition, the material of the second metal layer is copper, aluminum, or molybdenum.
  • the photolithography process in the step 6 includes photoresist, exposure, development, Wet etching, and photoresist removal process.
  • the present invention also provides a TFT substrate structure comprising: a substrate, a first metal layer, a gate insulating layer, a semiconductor layer, an etch barrier layer, and a second metal layer disposed in order from bottom to top; the first metal The layer includes a first gate and a second gate which are spaced apart; the semiconductor layer includes a first semiconductor, a connection semiconductor, and a second semiconductor that are sequentially arranged and connected to each other; the second metal layer includes a first source and a second drain that are spaced apart;
  • the first semiconductor is correspondingly located above the first gate, the second semiconductor is correspondingly located above the second gate, and the connecting semiconductor is located between the first semiconductor and the second semiconductor;
  • the first semiconductor includes a first source contact region and a first channel region;
  • the second semiconductor includes a second channel region and a second drain contact region; and two ends of the connection semiconductor are respectively connected to the first a channel region and a second channel region;
  • the first source contact region, the connection semiconductor, and the second drain contact region are both N-type heavily doped regions;
  • a first via hole, a second via hole, and a third via hole are formed on the etch barrier layer; the first source is in contact with the first source contact region through the first via hole; The second drain contacts the second drain contact region through the third via hole; the second via hole exposes the connection semiconductor;
  • the first gate, the first semiconductor, the first source, and the N-type heavily doped connection semiconductor constitute a first TFT; the second gate, the second semiconductor, and an N-type heavily doped connection
  • the semiconductor and the second drain constitute a second TFT; the first TFT and the second TFT are connected in series by an N-type heavily doped connection semiconductor.
  • the substrate is a glass substrate; the material of the first metal layer is copper, aluminum, or molybdenum.
  • the material of the gate insulating layer is silicon oxide or silicon nitride.
  • the material of the semiconductor layer is a metal oxide.
  • the material of the etch barrier layer is silicon oxide or silicon nitride; the material of the second metal layer is copper, aluminum, or molybdenum.
  • the present invention also provides a TFT substrate structure comprising: a substrate, a first metal layer, a gate insulating layer, a semiconductor layer, an etch barrier layer, and a second metal layer disposed in order from bottom to top; the first metal The layer includes a first gate and a second gate which are spaced apart; the semiconductor layer includes a first semiconductor, a connection semiconductor, and a second semiconductor which are sequentially arranged and connected to each other; and the second metal layer includes an interval a source and a second drain;
  • the first semiconductor is correspondingly located above the first gate, the second semiconductor is correspondingly located above the second gate, and the connecting semiconductor is located between the first semiconductor and the second semiconductor;
  • the first semiconductor includes a first source contact region and a first channel region;
  • the second semiconductor includes a second channel region and a second drain contact region; and two ends of the connection semiconductor are respectively connected to the first a channel region and a second channel region;
  • the first source contact region, the connection semiconductor, and the second drain contact region are both N-type heavily doped regions;
  • a first via hole, a second via hole, and a third via hole are formed on the etch barrier layer; the first source is in contact with the first source contact region through the first via hole; Second drain Contacting the second drain contact region through the third via hole; the second via hole exposing the connection semiconductor;
  • the first gate, the first semiconductor, the first source, and the N-type heavily doped connection semiconductor constitute a first TFT; the second gate, the second semiconductor, and an N-type heavily doped connection
  • the semiconductor and the second drain form a second TFT; the first TFT and the second TFT are connected in series by an N-type heavily doped connection semiconductor;
  • the substrate is a glass substrate;
  • the material of the first metal layer is copper, aluminum, or molybdenum;
  • the material of the gate insulating layer is silicon oxide or silicon nitride
  • the material of the semiconductor layer is a metal oxide.
  • the present invention provides a TFT substrate manufacturing method in which a first semiconductor and a second semiconductor are connected by an N-type heavily doped connection semiconductor disposed on a semiconductor layer, thereby bonding the first TFT and the second TFT
  • the TFTs are connected in series, and the N-type heavily doped connection semiconductor replaces the connection electrode disposed on the second metal layer in the prior art, thereby avoiding the connection of the connection electrode with the data line, the voltage supply line, and the like.
  • the problem that the design rules of the connection electrode and the second metal layer become smaller due to the two metal layers is advantageous for improving the aperture ratio and resolution of the display panel.
  • the invention provides a TFT substrate structure which has a simple structure, a high aperture ratio and a high resolution.
  • 1 is a circuit diagram of a conventional pixel compensation circuit
  • FIG. 2 is a schematic view showing a structure of a TFT substrate corresponding to the pixel compensation circuit shown in FIG. 1;
  • FIG. 3 is a schematic view showing the distribution and connection of a TFT component, a data line, and a voltage supply line in the TFT substrate structure shown in FIG. 2;
  • FIG. 4 is a schematic view showing a step 1 of a method for fabricating a TFT substrate of the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating a TFT substrate of the present invention
  • FIG. 6 is a schematic diagram of step 3 of a method for fabricating a TFT substrate according to the present invention.
  • step 4 is a schematic diagram of step 4 of a method for fabricating a TFT substrate of the present invention.
  • step 5 of a method for fabricating a TFT substrate of the present invention is a schematic diagram of step 5 of a method for fabricating a TFT substrate of the present invention.
  • FIG. 9 is a schematic view showing a step 6 of a method for fabricating a TFT substrate of the present invention. and a schematic cross-sectional view showing a structure of a TFT substrate of the present invention;
  • FIG. 10 is a schematic view showing the distribution and connection of a TFT component, a data line, and a voltage supply line in the TFT substrate structure shown in FIG. 9.
  • FIG. 10 is a schematic view showing the distribution and connection of a TFT component, a data line, and a voltage supply line in the TFT substrate structure shown in FIG. 9.
  • the present invention first provides a method for fabricating a TFT substrate, including the following steps:
  • Step 1 as shown in FIG. 4, a substrate 1 is provided, a first metal layer is deposited on the substrate 1, and the first metal layer is patterned by a photolithography process to form a first gate 21 disposed at intervals. And a second gate 23.
  • the substrate 1 is a glass substrate.
  • the step 1 deposits the first metal layer by physical Vapor Deposition (PVD) deposition.
  • PVD physical Vapor Deposition
  • the material of the first metal layer is copper, aluminum, or molybdenum.
  • the lithography process includes photoresisting, exposure, development, wet etching, and photoresist removal processes.
  • Step 2 As shown in FIG. 5, a gate insulating layer 3 is deposited on the first gate 21, the second gate 23, and the substrate 1.
  • the gate insulating layer 3 is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD).
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the material of the gate insulating layer 3 is silicon oxide or silicon nitride.
  • Step 3 depositing a semiconductor layer on the gate insulating layer 3, and patterning the semiconductor layer by a photolithography process to form a first semiconductor 41 and a connection which are sequentially arranged and connected to each other The semiconductor 42 and the second semiconductor 43.
  • the first semiconductor 41 is located above the first gate 21
  • the second semiconductor 43 is located above the second gate 23
  • the connecting semiconductor 42 is located at the first semiconductor 41 and Between two semiconductors 43.
  • the step 3 deposits the semiconductor layer by physical vapor deposition.
  • the material of the semiconductor layer is a metal oxide.
  • the metal oxide is Indium Gallium Zinc Oxide (IGZO).
  • the lithography process includes photoresisting, exposure, development, wet etching, and photoresist removal processes.
  • Step 4 depositing an etch stop layer 5 on the semiconductor layer and passing A lithography process forms a first through hole 51, a second through hole 52, and a third through hole 53 which are spaced apart from each other on the etch barrier layer 5.
  • the first through hole 51 , the second through hole 52 , and the third through hole 53 respectively expose an end of the first semiconductor 41 relatively away from the connection semiconductor 42 , the connection semiconductor 42 , and the second semiconductor 43 relatively away from the connection semiconductor 42 .
  • the step 4 deposits the etch stop layer 5 by chemical vapor deposition (CVD).
  • the material of the etch barrier layer 5 is silicon oxide or silicon nitride.
  • the lithography process includes photoresisting, exposure, development, dry etching, and photoresist removal processes.
  • Step 5 as shown in FIG. 8, the etch stop layer 5 is used as a shielding layer, and the first semiconductor 41 is respectively connected via the first through hole 51, the second through hole 52, and the third through hole 53.
  • N-type heavily doping is performed relatively far from an end of the connection semiconductor 42 , the connection semiconductor 42 , and the second semiconductor 43 relatively away from the connection semiconductor 42 , and the first semiconductor 41 is relatively far from the end of the connection semiconductor 42 , and the semiconductor 42 is connected.
  • a second semiconductor 43 is relatively far away from the conductive capability of the one end of the connection semiconductor 42 to form a first source contact region 412 and a first channel region 414 on the first semiconductor 41 to form on the second semiconductor 43
  • the second channel region 432 and the second drain contact region 434 are connected to the first channel region 414 and the second channel region 432, respectively.
  • the first source contact region 412, the connection semiconductor 42 and the second drain contact region 434 are all N-type heavily doped regions.
  • a N-type re-doping is performed on the end of the first semiconductor 41 relatively far from the connection semiconductor 42 , the connection semiconductor 42 , and the second semiconductor 43 relatively far from the connection semiconductor 42 by a hydrogen plasma treatment process. miscellaneous.
  • Step 6 as shown in FIG. 9, depositing a second metal layer on the etch barrier layer 5, and patterning the second metal layer by a photolithography process to form a first source 61 and an interval Two drains 62;
  • the first source 61 is in contact with the first source contact region 412 through the first via 51; the second drain 62 is in contact with the second drain contact region 434 through the third via 53.
  • the first gate 21, the first semiconductor 41, the first source 61, and the N-type heavily doped connection semiconductor 42 constitute a first TFT; the second gate 23, the second semiconductor 43, and the N pass The heavily doped junction semiconductor 42 and the second drain 62 form a second TFT; the first TFT and the second TFT are connected in series by an N-type heavily doped connection semiconductor 42.
  • the step 6 deposits the second metal layer by physical vapor deposition.
  • the material of the second metal layer is copper, aluminum, or molybdenum.
  • the lithography process includes photoresisting, exposure, development, wet etching, and photoresist removal processes.
  • the N-type heavily doped connection semiconductor 42 is disposed on the semiconductor layer, and the first semiconductor 41 and the second semiconductor 43 are connected by the N-type heavily doped connection semiconductor 42.
  • the first TFT is connected to the second TFT instead of the connection electrode disposed on the second metal layer in the prior art, and the connection electrode and the data line and the voltage line are disposed together in the second metal layer.
  • the problem that the design rule of the connection electrode and the second metal layer becomes small is small, which is advantageous for improving the aperture ratio and resolution of the display panel.
  • the present invention further provides a TFT substrate structure prepared by the above manufacturing method, which comprises: a substrate 1, a first metal layer, a gate insulating layer 3, and a semiconductor layer arranged in order from bottom to top. And etching the barrier layer 5 and the second metal layer; the first metal layer includes a first gate electrode 21 and a second gate electrode 23; the semiconductor layer includes a first semiconductor sequentially arranged and connected to each other 41. The semiconductor 42 and the second semiconductor 43 are connected; the second metal layer includes a first source 61 and a second drain 62 which are spaced apart from each other.
  • the first semiconductor 41 is located above the first gate 21, the second semiconductor 43 is located above the second gate 23, and the connecting semiconductor 42 is located at the first semiconductor 41 and Between the two semiconductors 43; the first semiconductor 41 includes a first source contact region 412, and a first channel region 414; the second semiconductor 43 includes a second channel region 432, and a second drain contact region 434; the two ends of the connection semiconductor 42 are respectively connected to the first channel region 414 and the second channel region 432; the first source contact region 412, the connection semiconductor 42, and the second drain contact region 434 are N-type heavily doped region.
  • a first through hole 51, a second through hole 52, and a third through hole 53 are formed on the etch barrier layer 5; the first source 61 passes through the first through hole 51 and the first source The contact region 412 is in contact; the second drain 62 is in contact with the second drain contact region 434 through the third via 53; the second via 52 exposes the connection semiconductor 42.
  • the first gate 21, the first semiconductor 41, the first source 61, and the N-type heavily doped connection semiconductor 42 constitute a first TFT; the second gate 23, the second semiconductor 43, and the N pass The heavily doped junction semiconductor 42 and the second drain 62 form a second TFT; the first TFT and the second TFT are connected in series by an N-type heavily doped connection semiconductor 42.
  • the substrate 1 is a glass substrate
  • the material of the first metal layer is copper, aluminum, or molybdenum
  • the material of the gate insulating layer 3 is silicon oxide or silicon nitride
  • the material of the semiconductor layer is a metal oxide such as indium gallium zinc oxide
  • the material of the etch barrier layer 5 is silicon oxide or silicon nitride
  • the material of the second metal layer is copper, aluminum, or molybdenum.
  • the first semiconductor and the second semiconductor are connected by an N-type heavily doped connection semiconductor disposed in the semiconductor layer, thereby connecting the first TFT and the second TFT in series.
  • the N-type heavily doped connection semiconductor replaces the connection electrode disposed on the second metal layer in the prior art, and avoids connecting the connection electrode to the second metal layer together with the signal line and the voltage line.
  • the problem that the design rule of the connection electrode and the second metal layer becomes small is small, which is advantageous for improving the aperture ratio and resolution of the display panel.
  • the TFT substrate structure of the present invention has a simple structure and a high aperture ratio and high resolution.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种TFT基板的制作方法及其结构。该TFT基板的制作方法采用设置于半导体层且经过N型重掺杂的连接半导体(42)连接第一半导体(41)与第二半导体(43)，从而将第一TFT与第二TFT串联起来，该经过N型重掺杂的连接半导体(42)代替了现有技术中设置于第二金属层上的连接电极，避免了将连接电极与数据线、供电压线等讯号线共同设置于第二金属层所导致的连接电极与第二金属层的设计规则变小的问题，有利于提高显示面板的开口率、及分辨率。还提供一种TFT基板结构，其结构简单，具有高开口率及高分辨率。

Description

TFT基板的制作方法及其结构 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法及其结构。
背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)等平板显示技术已经逐步取代CRT显示器。其中，OLED具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
OLED按照驱动类型可分为无源OLED(PMOLED)和有源OLED(AMOLED)；其中，AMOLED器件为电流驱动，其对薄膜晶体管(Thin Film Transistor，TFT)电流的要求非常严格。所以，AMOLED产品必须采用像素补偿电路来减少整个驱动过程中由于TFT不稳定导致的电流变化。
现有的AMOLED像素补偿电路通常涉及到多个TFT串联，如图1所示的一种像素补偿电路，在数据线Vdata与供电压线Vdd这两条讯号线之间串联了两个TFT：TFT1与TFT2；图2为对应图1所示的像素补偿电路的TFT基板结构，图3为图2所示的TFT基板结构中TFT组件与数据线、及供电压线的分布及连接示意图。
如图2和图3所示，所述TFT基板结构包括从下到上依次设置的基板100、第一金属层、栅极绝缘层300、半导体层、刻蚀阻挡层500、及第二金属层；所述第一金属层包括间隔设置的第一栅极210、及第二栅极230；所述半导体层包括间隔设置的第一半导体420、及第二半导体440；所述第二金属层包括间隔设置的第一源极610、连接电极620、及第二漏极630。
所述刻蚀阻挡层500上设有第一通孔510、第二通孔520、第三通孔530、及第四通孔540；所述第一源极610通过第一通孔510与所述第一半导体420的一端相接触；所述连接电极620通过第二通孔520与所述第一半导体420的另外一端相接触，同时通过第三通孔530与所述第二半导体440的一端相接触；所述第二漏极630通过第四通孔540与所述第二半导体440的另外一端相接触。
所述第一栅极210、第一半导体420、第一源极610、及连接电极620构成第一TFT；所述第二栅极230、第二半导体440、连接电极620、及第二漏极630构成第二TFT。
从图2和图3中可见，所述连接电极620同时充当第一TFT的第一漏极、以及第二TFT的第二源极，从而将第一TFT与第二TFT串联起来，然而，由于该连接电极620所在的第二金属层还分布有数据线Vdata、供电压线Vdd等讯号线，使得该连接电极620的设计规则(design rule)很小，而两TFT之间再通过连接电极620桥接会导致该第二金属层的设计规则变得更小，不利于高开口率、及高分辨率的显示面板的制作。
发明内容
本发明的目的在于提供一种TFT基板的制作方法，通过采用设置于半导体层且经过N型重掺杂的连接半导体代替现有技术中设置于第二金属层上的连接电极，避免了现有设计中将连接电极与数据线、供电压线等讯号线共同设置于第二金属层所导致的连接电极与第二金属层的设计规则变小的问题，有利于高开口率、及高分辨率的显示面板的制作。
本发明的目的还在于提供一种TFT基板结构，其结构简单，具有高开口率及高分辨率。
为实现上述目的，本发明首先提供一种TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上沉积第一金属层，并通过一道光刻制程图案化该第一金属层，形成间隔设置的第一栅极、及第二栅极；
步骤2、在所述第一栅极、第二栅极、及基板上沉积栅极绝缘层；
步骤3、在所述栅极绝缘层上沉积一半导体层，并通过一道光刻制程对该半导体层进行图案化，形成依次排列且相互连接的第一半导体、连接半导体、及第二半导体；
所述第一半导体对应位于所述第一栅极的上方，所述第二半导体对应位于所述第二栅极的上方、所述连接半导体位于所述第一半导体与第二半导体之间；
步骤4、在所述半导体层上沉积一刻蚀阻挡层，并通过一道光刻制程在该刻蚀阻挡层上形成间隔设置的第一通孔、第二通孔、及第三通孔；
所述第一通孔、第二通孔、及第三通孔分别暴露出第一半导体相对远离连接半导体的一端、连接半导体、及第二半导体相对远离连接半导体的一端；
步骤5、以所述刻蚀阻挡层为遮挡层，分别经由所述第一通孔、第二通孔、及第三通孔对所述第一半导体相对远离连接半导体的一端、连接半导体、及第二半导体相对远离连接半导体的一端进行N型重掺杂，从而在所述第一半导体上形成第一源极接触区与第一沟道区，在所述第二半导体上形成第二沟道区与第二漏极接触区，所述连接半导体的两端分别连接第一沟道区与第二沟道区；
其中，所述第一源极接触区、连接半导体、及第二漏极接触区均为N型重掺杂区域；
步骤6、在所述刻蚀阻挡层上沉积第二金属层，并通过一道光刻制程图案化该第二金属层，形成间隔设置的第一源极、及第二漏极；
所述第一源极通过第一通孔与第一源极接触区相接触；所述第二漏极通过第三通孔与第二漏极接触区相接触；
所述第一栅极、第一半导体、第一源极、及经过N型重掺杂的连接半导体构成第一TFT；所述第二栅极、第二半导体、经过N型重掺杂的连接半导体、及第二漏极构成第二TFT；所述第一TFT与第二TFT由经过N型重掺杂的连接半导体串联起来。
所述步骤1采用物理气相沉积法沉积所述第一金属层，所述第一金属层的材料为铜、铝、或钼，所述步骤1中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程；所述步骤2采用等离子增强化学气相沉积法沉积所述栅极绝缘层，所述栅极绝缘层的材料为氧化硅或氮化硅。
所述步骤3采用物理气相沉积法沉积所述半导体层，所述半导体层的材料为金属氧化物，所述步骤3中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
所述步骤4采用化学气相沉积法沉积所述刻蚀阻挡层，所述刻蚀阻挡层的材料为氧化硅或氮化硅，所述步骤4中的光刻制程包括涂光阻、曝光、显影、干蚀刻、及去光阻制程；所述步骤5采用氢气等离子处理工艺对所述第一半导体相对远离连接半导体的一端、连接半导体、及第二半导体相对远离连接半导体的一端进行N型重掺杂。
所述步骤6采用通过物理气相沉积法沉积所述第二金属层，所述第二金属层的材料为铜、铝、或钼，所述步骤6中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
本发明还提供一种TFT基板结构，包括从下到上依次设置的：基板、第一金属层、栅极绝缘层、半导体层、刻蚀阻挡层、及第二金属层；所述第一金属层包括间隔设置的第一栅极、及第二栅极；所述半导体层包括依 次排列且相互连接的第一半导体、连接半导体、及第二半导体；所述第二金属层包括间隔设置的第一源极、及第二漏极；
所述第一半导体对应位于所述第一栅极的上方，所述第二半导体对应位于所述第二栅极的上方、所述连接半导体位于所述第一半导体与第二半导体之间；所述第一半导体包括第一源极接触区、及第一沟道区；所述第二半导体包括第二沟道区、及第二漏极接触区；所述连接半导体的两端分别连接第一沟道区与第二沟道区；所述第一源极接触区、连接半导体、及第二漏极接触区均为N型重掺杂区域；
所述刻蚀阻挡层上形成有间隔设置的第一通孔、第二通孔、及第三通孔；所述第一源极通过第一通孔与第一源极接触区相接触；所述第二漏极通过第三通孔与第二漏极接触区相接触；所述第二通孔暴露出所述连接半导体；
所述第一栅极、第一半导体、第一源极、及经过N型重掺杂的连接半导体构成第一TFT；所述第二栅极、第二半导体、经过N型重掺杂的连接半导体、及第二漏极构成第二TFT；所述第一TFT与第二TFT由经过N型重掺杂的连接半导体串联起来。
所述基板为玻璃基板；所述第一金属层的材料为铜、铝、或钼。
所述栅极绝缘层的材料为氧化硅或氮化硅。
所述半导体层的材料为金属氧化物。
所述刻蚀阻挡层的材料为氧化硅或氮化硅；所述第二金属层的材料为铜、铝、或钼。
本发明还提供一种TFT基板结构，包括从下到上依次设置的：基板、第一金属层、栅极绝缘层、半导体层、刻蚀阻挡层、及第二金属层；所述第一金属层包括间隔设置的第一栅极、及第二栅极；所述半导体层包括依次排列且相互连接的第一半导体、连接半导体、及第二半导体；所述第二金属层包括间隔设置的第一源极、及第二漏极；
所述第一半导体对应位于所述第一栅极的上方，所述第二半导体对应位于所述第二栅极的上方、所述连接半导体位于所述第一半导体与第二半导体之间；所述第一半导体包括第一源极接触区、及第一沟道区；所述第二半导体包括第二沟道区、及第二漏极接触区；所述连接半导体的两端分别连接第一沟道区与第二沟道区；所述第一源极接触区、连接半导体、及第二漏极接触区均为N型重掺杂区域；
所述刻蚀阻挡层上形成有间隔设置的第一通孔、第二通孔、及第三通孔；所述第一源极通过第一通孔与第一源极接触区相接触；所述第二漏极 通过第三通孔与第二漏极接触区相接触；所述第二通孔暴露出所述连接半导体；
所述第一栅极、第一半导体、第一源极、及经过N型重掺杂的连接半导体构成第一TFT；所述第二栅极、第二半导体、经过N型重掺杂的连接半导体、及第二漏极构成第二TFT；所述第一TFT与第二TFT由经过N型重掺杂的连接半导体串联起来；
其中，所述基板为玻璃基板；所述第一金属层的材料为铜、铝、或钼；
其中，所述栅极绝缘层的材料为氧化硅或氮化硅；
其中，所述半导体层的材料为金属氧化物。
本发明的有益效果：本发明提供的一种TFT基板的制作方法，采用设置于半导体层且经过N型重掺杂的连接半导体连接第一半导体与第二半导体，从而将第一TFT与第二TFT串联起来，该经过N型重掺杂的连接半导体代替了现有技术中设置于第二金属层上的连接电极，避免了将连接电极与数据线、供电压线等讯号线共同设置于第二金属层所导致的连接电极与第二金属层的设计规则变小的问题，有利于提高显示面板的开口率、及分辨率。本发明提供的一种TFT基板结构，其结构简单，具有高开口率及高分辨率。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有的一种像素补偿电路的电路图；
图2为对应图1所示的像素补偿电路的TFT基板结构的示意图；
图3为图2所示的TFT基板结构中TFT组件与数据线、及供电压线的分布及连接示意图；
图4为本发明的TFT基板的制作方法步骤1的示意图；
图5为本发明的TFT基板的制作方法步骤2的示意图；
图6为本发明的TFT基板的制作方法步骤3的示意图；
图7为本发明的TFT基板的制作方法步骤4的示意图；
图8为本发明的TFT基板的制作方法步骤5的示意图；
图9为本发明的TFT基板的制作方法步骤6的示意图暨本发明的TFT基板结构的剖面示意图；
图10为图9所示的TFT基板结构中TFT组件与数据线、及供电压线的分布及连接示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图4至图9，本发明首先提供一种TFT基板的制作方法，包括如下步骤：
步骤1、如图4所示，提供一基板1，在所述基板1上沉积第一金属层，并通过一道光刻制程图案化该第一金属层，形成间隔设置的第一栅极21、及第二栅极23。
优选的，所述基板1为玻璃基板。
具体地，该步骤1采用物理气相沉积法(Physical Vapor Deposition，PVD)沉积沉积所述第一金属层。优选的，所述第一金属层的材料为铜、铝、或钼。
所述光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
步骤2、如图5所示，在所述第一栅极21、第二栅极23、及基板1上沉积栅极绝缘层3。
具体地，该步骤2采用等离子增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)沉积所述栅极绝缘层3。优选的，所述栅极绝缘层3的材料为氧化硅或氮化硅。
步骤3、如图6所示，在所述栅极绝缘层3上沉积一半导体层，并通过一道光刻制程对该半导体层进行图案化，形成依次排列且相互连接的第一半导体41、连接半导体42、及第二半导体43。
所述第一半导体41对应位于所述第一栅极21的上方，所述第二半导体43对应位于所述第二栅极23的上方、所述连接半导体42位于所述第一半导体41与第二半导体43之间。
具体地，该步骤3采用物理气相沉积法沉积所述半导体层。进一步地，所述半导体层的材料为金属氧化物，优选的，所述金属氧化物为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)。
所述光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
步骤4、如图7所示，在所述半导体层上沉积一刻蚀阻挡层5，并通过 一道光刻制程在刻蚀阻挡层5上形成间隔设置的第一通孔51、第二通孔52、及第三通孔53。
所述第一通孔51、第二通孔52、及第三通孔53分别暴露出第一半导体41相对远离连接半导体42的一端、连接半导体42、及第二半导体43相对远离连接半导体42的一端。
具体地，该步骤4采用化学气相沉积法(Chemical Vapor Deposition，CVD)沉积所述刻蚀阻挡层5。优选的，所述刻蚀阻挡层5的材料为氧化硅或氮化硅。
所述光刻制程包括涂光阻、曝光、显影、干蚀刻、及去光阻制程。
步骤5、如图8所示，以所述刻蚀阻挡层5为遮挡层，分别经由所述第一通孔51、第二通孔52、及第三通孔53对所述第一半导体41相对远离连接半导体42的一端、连接半导体42、及第二半导体43相对远离连接半导体42的一端进行N型重掺杂，提高所述第一半导体41相对远离连接半导体42的一端、连接半导体42、及第二半导体43相对远离连接半导体42的一端的导电能力，从而在所述第一半导体41上形成第一源极接触区412与第一沟道区414，在所述第二半导体43上形成第二沟道区432与第二漏极接触区434，所述连接半导体42的两端分别连接第一沟道区414与第二沟道区432。
其中，所述第一源极接触区412、连接半导体42、及第二漏极接触区434均为N型重掺杂区域。
优选的，该步骤5采用氢气等离子(Plasma)处理工艺对所述第一半导体41相对远离连接半导体42的一端、连接半导体42、及第二半导体43相对远离连接半导体42的一端进行N型重掺杂。
步骤6、如图9所示，在所述刻蚀阻挡层5上沉积第二金属层，并通过一道光刻制程图案化该第二金属层，形成间隔设置的第一源极61、及第二漏极62；
所述第一源极61通过第一通孔51与第一源极接触区412相接触；所述第二漏极62通过第三通孔53与第二漏极接触区434相接触。
所述第一栅极21、第一半导体41、第一源极61、及经过N型重掺杂的连接半导体42构成第一TFT；所述第二栅极23、第二半导体43、经过N型重掺杂的连接半导体42、及第二漏极62构成第二TFT；所述第一TFT与第二TFT由经过N型重掺杂的连接半导体42串联起来。
具体地，该步骤6采用物理气相沉积法沉积所述第二金属层。优选的，所述第二金属层的材料为铜、铝、或钼。
所述光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
上述TFT基板的制作方法将经过N型重掺杂的连接半导体42设置于半导体层，并由所述经过N型重掺杂的连接半导体42来连接第一半导体41与第二半导体43，从而将第一TFT与第二TFT连接起来，代替了现有技术中设置于第二金属层上的连接电极，避免了将连接电极与数据线、供电压线等讯号线共同设置于第二金属层所导致的连接电极与第二金属层的设计规则变小的问题，有利于提高显示面板的开口率、及分辨率。
请参阅图9、图10，本发明还提供一种由上述制作方法制备的TFT基板结构，其包括从下到上依次设置的：基板1、第一金属层、栅极绝缘层3、半导体层、刻蚀阻挡层5、及第二金属层；所述第一金属层包括间隔设置的第一栅极21、及第二栅极23；所述半导体层包括依次排列且相互连接的第一半导体41、连接半导体42、及第二半导体43；所述第二金属层包括间隔设置的第一源极61、及第二漏极62。
所述第一半导体41对应位于所述第一栅极21的上方，所述第二半导体43对应位于所述第二栅极23的上方、所述连接半导体42位于所述第一半导体41与第二半导体43之间；所述第一半导体41包括第一源极接触区412、及第一沟道区414；所述第二半导体43包括第二沟道区432、及第二漏极接触区434；所述连接半导体42的两端分别连接第一沟道区414与第二沟道区432；所述第一源极接触区412、连接半导体42、及第二漏极接触区434均为N型重掺杂区域。
所述刻蚀阻挡层5上形成有间隔设置的第一通孔51、第二通孔52、及第三通孔53；所述第一源极61通过第一通孔51与第一源极接触区412相接触；所述第二漏极62通过第三通孔53与第二漏极接触区434相接触；所述第二通孔52暴露出所述连接半导体42。
所述第一栅极21、第一半导体41、第一源极61、及经过N型重掺杂的连接半导体42构成第一TFT；所述第二栅极23、第二半导体43、经过N型重掺杂的连接半导体42、及第二漏极62构成第二TFT；所述第一TFT与第二TFT由经过N型重掺杂的连接半导体42串联起来。
优选的，所述基板1为玻璃基板；
优选的，所述第一金属层的材料为铜、铝、或钼；
优选的，所述栅极绝缘层3的材料为氧化硅或氮化硅；
优选的，所述半导体层的材料为金属氧化物，如铟镓锌氧化物；
优选的，所述刻蚀阻挡层5的材料为氧化硅或氮化硅；
优选的，所述第二金属层的材料为铜、铝、或钼。
综上所述，本发明的TFT基板的制作方法，采用设置于半导体层且经过N型重掺杂的连接半导体连接第一半导体与第二半导体，从而将第一TFT与第二TFT串联起来，该经过N型重掺杂的连接半导体代替了现有技术中设置于第二金属层上的连接电极，避免了将连接电极与数据线、供电压线等讯号线共同设置于第二金属层所导致的连接电极与第二金属层的设计规则变小的问题，有利于提高显示面板的开口率、及分辨率。本发明的TFT基板结构，其结构简单，具有高开口率及高分辨率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (12)

  1. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上沉积第一金属层，并通过一道光刻制程图案化该第一金属层，形成间隔设置的第一栅极、及第二栅极；
    步骤2、在所述第一栅极、第二栅极、及基板上沉积栅极绝缘层；
    步骤3、在所述栅极绝缘层上沉积一半导体层，并通过一道光刻制程对该半导体层进行图案化，形成依次排列且相互连接的第一半导体、连接半导体、及第二半导体；
    所述第一半导体对应位于所述第一栅极的上方，所述第二半导体对应位于所述第二栅极的上方、所述连接半导体位于所述第一半导体与第二半导体之间；
    步骤4、在所述半导体层上沉积一刻蚀阻挡层，并通过一道光刻制程在该刻蚀阻挡层上形成间隔设置的第一通孔、第二通孔、及第三通孔；
    所述第一通孔、第二通孔、及第三通孔分别暴露出第一半导体相对远离连接半导体的一端、连接半导体、及第二半导体相对远离连接半导体的一端；
    步骤5、以所述刻蚀阻挡层为遮挡层，分别经由所述第一通孔、第二通孔、及第三通孔对所述第一半导体相对远离连接半导体的一端、连接半导体、及第二半导体相对远离连接半导体的一端进行N型重掺杂，从而在所述第一半导体上形成第一源极接触区与第一沟道区，在所述第二半导体上形成第二沟道区与第二漏极接触区，所述连接半导体的两端分别连接第一沟道区与第二沟道区；
    其中，所述第一源极接触区、连接半导体、及第二漏极接触区均为N型重掺杂区域；
    步骤6、在所述刻蚀阻挡层上沉积第二金属层，并通过一道光刻制程图案化该第二金属层，形成间隔设置的第一源极、及第二漏极；
    所述第一源极通过第一通孔与第一源极接触区相接触；所述第二漏极通过第三通孔与第二漏极接触区相接触；
    所述第一栅极、第一半导体、第一源极、及经过N型重掺杂的连接半导体构成第一TFT；所述第二栅极、第二半导体、经过N型重掺杂的连接半导体、及第二漏极构成第二TFT；所述第一TFT与第二TFT由经过N型重掺杂的连接半导体串联起来。
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤1采用物理气相沉积法沉积所述第一金属层，所述第一金属层的材料为铜、铝、或钼，所述步骤1中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程；所述步骤2采用等离子增强化学气相沉积法沉积所述该栅极绝缘层，所述栅极绝缘层的材料为氧化硅或氮化硅。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤3采用物理气相沉积法沉积所述半导体层，所述半导体层的材料为金属氧化物，所述步骤3中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
  4. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤4采用化学气相沉积法沉积所述刻蚀阻挡层，所述刻蚀阻挡层的材料为氧化硅或氮化硅，所述步骤4中的光刻制程包括涂光阻、曝光、显影、干蚀刻、及去光阻制程；所述步骤5采用氢气等离子处理工艺对所述第一半导体相对远离连接半导体的一端、连接半导体、及第二半导体相对远离连接半导体的一端进行N型重掺杂。
  5. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤6采用物理气相沉积法沉积所述第二金属层，所述第二金属层的材料为铜、铝、或钼，所述步骤6中的光刻制程包括涂光阻、曝光、显影、湿蚀刻、及去光阻制程。
  6. 一种TFT基板结构，包括从下到上依次设置的：基板、第一金属层、栅极绝缘层、半导体层、刻蚀阻挡层、及第二金属层；所述第一金属层包括间隔设置的第一栅极、及第二栅极；所述半导体层包括依次排列且相互连接的第一半导体、连接半导体、及第二半导体；所述第二金属层包括间隔设置的第一源极、及第二漏极；
    所述第一半导体对应位于所述第一栅极的上方，所述第二半导体对应位于所述第二栅极的上方、所述连接半导体位于所述第一半导体与第二半导体之间；所述第一半导体包括第一源极接触区、及第一沟道区；所述第二半导体包括第二沟道区、及第二漏极接触区；所述连接半导体的两端分别连接第一沟道区与第二沟道区；所述第一源极接触区、连接半导体、及第二漏极接触区均为N型重掺杂区域；
    所述刻蚀阻挡层上形成有间隔设置的第一通孔、第二通孔、及第三通孔；所述第一源极通过第一通孔与第一源极接触区相接触；所述第二漏极通过第三通孔与第二漏极接触区相接触；所述第二通孔暴露出所述连接半导体；
    所述第一栅极、第一半导体、第一源极、及经过N型重掺杂的连接半导体构成第一TFT；所述第二栅极、第二半导体、经过N型重掺杂的连接半导体、及第二漏极构成第二TFT；所述第一TFT与第二TFT由经过N型重掺杂的连接半导体串联起来。
  7. 如权利要求6所述的TFT基板结构，其中，所述基板为玻璃基板；所述第一金属层的材料为铜、铝、或钼。
  8. 如权利要求6所述的TFT基板结构，其中，所述栅极绝缘层的材料为氧化硅或氮化硅。
  9. 如权利要求6所述的TFT基板结构，其中，所述半导体层的材料为金属氧化物。
  10. 如权利要求6所述的TFT基板结构，其中，所述刻蚀阻挡层的材料为氧化硅或氮化硅；所述第二金属层的材料为铜、铝、或钼。
  11. 一种TFT基板结构，包括从下到上依次设置的：基板、第一金属层、栅极绝缘层、半导体层、刻蚀阻挡层、及第二金属层；所述第一金属层包括间隔设置的第一栅极、及第二栅极；所述半导体层包括依次排列且相互连接的第一半导体、连接半导体、及第二半导体；所述第二金属层包括间隔设置的第一源极、及第二漏极；
    所述第一半导体对应位于所述第一栅极的上方，所述第二半导体对应位于所述第二栅极的上方、所述连接半导体位于所述第一半导体与第二半导体之间；所述第一半导体包括第一源极接触区、及第一沟道区；所述第二半导体包括第二沟道区、及第二漏极接触区；所述连接半导体的两端分别连接第一沟道区与第二沟道区；所述第一源极接触区、连接半导体、及第二漏极接触区均为N型重掺杂区域；
    所述刻蚀阻挡层上形成有间隔设置的第一通孔、第二通孔、及第三通孔；所述第一源极通过第一通孔与第一源极接触区相接触；所述第二漏极通过第三通孔与第二漏极接触区相接触；所述第二通孔暴露出所述连接半导体；
    所述第一栅极、第一半导体、第一源极、及经过N型重掺杂的连接半导体构成第一TFT；所述第二栅极、第二半导体、经过N型重掺杂的连接半导体、及第二漏极构成第二TFT；所述第一TFT与第二TFT由经过N型重掺杂的连接半导体串联起来；
    其中，所述基板为玻璃基板；所述第一金属层的材料为铜、铝、或钼；
    其中，所述栅极绝缘层的材料为氧化硅或氮化硅；
    其中，所述半导体层的材料为金属氧化物。
  12. 如权利要求11所述的TFT基板结构，其中，所述刻蚀阻挡层的材料为氧化硅或氮化硅；所述第二金属层的材料为铜、铝、或钼。
PCT/CN2015/079662 2015-05-06 2015-05-25 Tft基板的制作方法及其结构 WO2016176880A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/759,198 US9673227B1 (en) 2015-05-06 2015-05-25 Method of manufacturing TFTs in series and connection semiconductor formed thereby

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510227679.2A CN104882414B (zh) 2015-05-06 2015-05-06 Tft基板的制作方法及其结构
CN201510227679.2 2015-05-06

Publications (1)

Publication Number Publication Date
WO2016176880A1 true WO2016176880A1 (zh) 2016-11-10

Family

ID=53949854

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/079662 WO2016176880A1 (zh) 2015-05-06 2015-05-25 Tft基板的制作方法及其结构

Country Status (3)

Country Link
US (1) US9673227B1 (zh)
CN (1) CN104882414B (zh)
WO (1) WO2016176880A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105633101A (zh) 2016-04-01 2016-06-01 京东方科技集团股份有限公司 Tft阵列基板及其制造方法、显示装置
KR20200089794A (ko) * 2019-01-17 2020-07-28 삼성디스플레이 주식회사 표시 장치와 그의 제조 방법
CN110047849A (zh) * 2019-04-02 2019-07-23 福建华佳彩有限公司 一种Demux电路的TFT结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1359139A (zh) * 2000-12-06 2002-07-17 株式会社半导体能源研究所 半导体器件及其制造方法
CN101067705A (zh) * 2007-07-03 2007-11-07 友达光电股份有限公司 液晶显示器的像素结构及其制造方法
CN101123224A (zh) * 2007-09-18 2008-02-13 友达光电股份有限公司 像素结构的制作方法
CN101308844A (zh) * 2008-07-15 2008-11-19 友达光电股份有限公司 半导体结构及其制造方法
CN104538458A (zh) * 2014-12-22 2015-04-22 京东方科技集团股份有限公司 一种显示装置、阵列基板、薄膜晶体管及其制作方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198379A (en) * 1990-04-27 1993-03-30 Sharp Kabushiki Kaisha Method of making a MOS thin film transistor with self-aligned asymmetrical structure
KR100292767B1 (ko) * 1992-09-25 2001-09-17 이데이 노부유끼 액정표시장치
JP3274081B2 (ja) * 1997-04-08 2002-04-15 松下電器産業株式会社 薄膜トランジスタの製造方法および液晶表示装置の製造方法
JP4076648B2 (ja) * 1998-12-18 2008-04-16 株式会社半導体エネルギー研究所 半導体装置
JP2000214800A (ja) * 1999-01-20 2000-08-04 Sanyo Electric Co Ltd エレクトロルミネッセンス表示装置
US6281552B1 (en) * 1999-03-23 2001-08-28 Semiconductor Energy Laboratory Co., Ltd. Thin film transistors having ldd regions
US7288420B1 (en) * 1999-06-04 2007-10-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing an electro-optical device
KR100514181B1 (ko) * 2003-09-03 2005-09-13 삼성에스디아이 주식회사 시리즈 박막트랜지스터, 그를 이용한 능동 매트릭스유기전계발광소자 및 상기 능동 매트릭스유기전계발광소자의 제조방법
JP4246123B2 (ja) * 2004-08-02 2009-04-02 株式会社半導体エネルギー研究所 半導体集積回路の作製方法
JP4349375B2 (ja) * 2005-04-11 2009-10-21 セイコーエプソン株式会社 電気光学装置及び電子機器
US7687327B2 (en) * 2005-07-08 2010-03-30 Kovio, Inc, Methods for manufacturing RFID tags and structures formed therefrom
KR101183437B1 (ko) * 2006-06-14 2012-09-14 엘지디스플레이 주식회사 박막 트랜지스터 및 이를 이용한 유기전계발광표시장치
KR100867926B1 (ko) * 2007-06-21 2008-11-10 삼성에스디아이 주식회사 유기전계발광표시장치 및 그의 제조 방법
KR102081283B1 (ko) * 2013-02-14 2020-04-16 삼성디스플레이 주식회사 박막 반도체 장치, 유기 발광 표시 장치, 및 이의 제조 방법
KR102049444B1 (ko) * 2013-05-10 2019-11-28 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 유기 발광 표시 장치 제조용 포토 마스크

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1359139A (zh) * 2000-12-06 2002-07-17 株式会社半导体能源研究所 半导体器件及其制造方法
CN101067705A (zh) * 2007-07-03 2007-11-07 友达光电股份有限公司 液晶显示器的像素结构及其制造方法
CN101123224A (zh) * 2007-09-18 2008-02-13 友达光电股份有限公司 像素结构的制作方法
CN101308844A (zh) * 2008-07-15 2008-11-19 友达光电股份有限公司 半导体结构及其制造方法
CN104538458A (zh) * 2014-12-22 2015-04-22 京东方科技集团股份有限公司 一种显示装置、阵列基板、薄膜晶体管及其制作方法

Also Published As

Publication number Publication date
CN104882414A (zh) 2015-09-02
US20170141127A1 (en) 2017-05-18
US9673227B1 (en) 2017-06-06
CN104882414B (zh) 2018-07-10

Similar Documents

Publication Publication Date Title
WO2016176884A1 (zh) Tft基板的制作方法及其结构
US9768323B2 (en) Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof
US9666653B2 (en) Method for manufacturing TFT substrate and structure thereof
US9716119B2 (en) Manufacturing method of dual gate TFT substrate and structure thereof
CN108091674B (zh) Oled背板结构及oled背板制作方法
CN108493195B (zh) 柔性tft背板的制作方法及柔性tft背板
US20150325630A1 (en) Array substrate, manufacturing method thereof and display device
US9214476B1 (en) Pixel structure
WO2018176784A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
US20150357356A1 (en) Thin film transistor array substrate and method of manufacturing the same
WO2016176879A1 (zh) Amoled背板的制作方法及其结构
WO2015123915A1 (zh) 有源矩阵有机发光二极管阵列基板及制作方法和显示装置
US11374027B2 (en) Manufacturing method of thin film transistor substrate and thin film transistor substrate
WO2015161523A1 (zh) 薄膜晶体管及有机发光二极管显示器制备方法
WO2016176880A1 (zh) Tft基板的制作方法及其结构
WO2018023955A1 (zh) Oled显示装置的阵列基板及其制造方法
WO2016026176A1 (zh) Tft基板的制作方法及其结构
WO2020037850A1 (zh) 阵列基板及其制造方法、显示面板
WO2016179877A1 (zh) 共平面型氧化物半导体tft基板结构及其制作方法
KR101094296B1 (ko) 표시장치 및 그 제조 방법
US9691836B2 (en) Pixel unit, array substrate, display device and method for manufacturing the same including MoW/Cu/MoW conductive line
WO2018161372A1 (zh) 薄膜晶体管阵列基板及其制备方法、显示装置
US20210013329A1 (en) Array substrate and method for manufacturing the same
WO2022160410A1 (zh) 显示面板及其制备方法
TW201607000A (zh) 有機發光顯示器及其製造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14759198

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15891132

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15891132

Country of ref document: EP

Kind code of ref document: A1