WO2014153810A1 - 悬浮栅晶体管及其制作方法、应用方法、显示器驱动电路 - Google Patents

悬浮栅晶体管及其制作方法、应用方法、显示器驱动电路 Download PDF

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Publication number
WO2014153810A1
WO2014153810A1 PCT/CN2013/075310 CN2013075310W WO2014153810A1 WO 2014153810 A1 WO2014153810 A1 WO 2014153810A1 CN 2013075310 W CN2013075310 W CN 2013075310W WO 2014153810 A1 WO2014153810 A1 WO 2014153810A1
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Prior art keywords
layer
insulating film
floating gate
film
photoresist
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PCT/CN2013/075310
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English (en)
French (fr)
Inventor
陈宁
郭炜
王路
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/368,145 priority Critical patent/US9620532B2/en
Publication of WO2014153810A1 publication Critical patent/WO2014153810A1/zh

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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • Embodiments of the present invention relate to a floating gate transistor based on a thin film transistor (TFT) fabrication process, a fabrication method thereof, an application method, and a display driving circuit.
  • TFT thin film transistor
  • the term "suspended gate” is derived from a special MOS transistor.
  • the transistor has a source 104, a drain 105, and two gates.
  • One of the gates has an electrical connection, called control gate 100, which acts as a gate in a general sense.
  • the other gate has no outer leads. It is completely wrapped in the two layers of the SiO2 film 102 and is floating. Therefore, it is called a floating gate 103, as shown in Fig. 1.
  • the floating gate MOS transistor works by changing the threshold voltage of the MOS transistor by using whether or not the floating gate stores a charge or a stored charge, thereby changing the external characteristics of the MOS transistor. This process can be described as follows. When a sufficiently high voltage (such as 25 V) is applied to the drain and gate of the MOS transistor, and the source and the bottom of the village are grounded, the PN junction between the drain and the substrate is reverse-punched, generating a large amount of high-energy electrons. . These electrons are deposited on the floating gate through a thin layer of SiOx film, which causes the floating gate to have a negative charge. If this process is maintained long enough, the floating gate will accumulate enough electrons.
  • a sufficiently high voltage such as 25 V
  • the electrons on the floating gate can be stored for a long time because there is no discharge loop.
  • a negative charge is applied to the floating gate, a positive charge is induced on the surface of the substrate, which causes the turn-on voltage of the MOS transistor to become high.
  • the threshold voltage which enables the MOS transistor to be turned on is applied to the gate of the MOS transistor at this time, and the MOS transistor will remain in the off state.
  • the storage unit uses this principle to store binary data.
  • the charge on the floating gate can be modified in two ways:
  • an embodiment of the present invention provides a floating gate transistor based on a TFT manufacturing technology, a manufacturing method thereof, an application method, and a display driving circuit, wherein the floating gate can store a certain electric charge, thereby being capable of storing data.
  • the role is a floating gate transistor based on a TFT manufacturing technology, a manufacturing method thereof, an application method, and a display driving circuit, wherein the floating gate can store a certain electric charge, thereby being capable of storing data.
  • An aspect of the present invention provides a floating gate transistor including a substrate, a floating gate, a source, a drain, and a control gate disposed on the substrate, further comprising: a first insulating film sequentially disposed on the substrate a polysilicon film in which a channel region is formed, and a position of the channel region corresponds to a position of the floating gate.
  • a second insulating film and a third insulating film are sequentially disposed on the polysilicon film, and the floating gate is disposed between the second insulating film and the third insulating film.
  • the third insulating film is respectively disposed on the two sides of the floating gate with a first opening and a second opening, and the first opening and the second opening respectively extend to the polysilicon film to form a source via And a drain via, wherein the source via and the drain via are provided with a metal thin film to form a source and a drain, respectively.
  • a portion of the third insulating film corresponding to the floating gate is deposited with a metal thin film to form a control gate.
  • the first insulating film, the second insulating film, and the third insulating film are made of one or both of SiOx, SiNx, and SiOxNy.
  • Another aspect of the present invention also provides a display driving circuit comprising the above floating gate transistor.
  • Still another aspect of the present invention provides a method for fabricating a floating gate transistor, comprising the steps of: sequentially forming a first insulating film and a polysilicon film on a substrate; forming a channel region in the polysilicon film; Forming a second insulating film and a third insulating film on the film, and a floating gate disposed between the second insulating film and the third insulating film; forming a source region and a drain region in the polysilicon film Forming a control gate on the third insulating film.
  • sequentially forming a first insulating film and a polysilicon film on the substrate comprising: sequentially depositing the first insulating film and the amorphous silicon film on the substrate; performing annealing treatment to form the amorphous silicon film Polysilicon film.
  • forming a channel region in the polysilicon film includes: coating a surface of the polysilicon film with a first layer of photoresist, and performing photolithographic exposure on the polysilicon film and the first layer of photoresist a region corresponding to the reserved region is a channel region; and a borane ion or a phosphine ion is implanted in the channel region, so that the polysilicon film located in the channel region forms P-type polysilicon or N-type polysilicon; A stripping process removes the first layer of photoresist; an annealing process is performed.
  • forming a second insulating film and a third insulating film in the polysilicon film, and a floating gate disposed between the second insulating film and the third insulating film includes: using a vapor deposition method in the a second insulating film and a second amorphous silicon film are sequentially deposited on the polysilicon film; a second layer of photoresist is coated on the surface of the second amorphous silicon film, and lithographic exposure is performed to make the second layer of lithography Retaining a region of the glue corresponding to the channel region; using an etching process, retaining a region of the second layer of amorphous silicon film corresponding to the channel region to form a floating gate; stripping the second a layer of photoresist; depositing a third insulating film on the surface of the second insulating film and the surface of the floating gate by vapor deposition.
  • forming a source region and a drain region in the polysilicon film includes: coating a third layer of photoresist on the third layer of insulating film, exposing and developing the third layer of photoresist; Etching the second insulating film, the third insulating film to remove the second insulating film, and the third insulating film corresponds to the unreserved region of the third photoresist A region in which a source region and a drain region are formed in the polysilicon film.
  • forming a control gate on the third insulating film includes: heavily doping a borane ion or a phosphorus ion in the source region and the drain region to form a good conductive layer; a three-layer photoresist; depositing a layer on the second insulating film, the unetched region of the third insulating film, and the source and drain regions formed in the polysilicon film by vapor deposition a metal film; depositing a fourth layer of photoresist on the metal film, exposing and developing the fourth layer of photoresist; performing etching to form a source, a drain, and a control gate on the metal film; The fourth layer of photoresist is stripped.
  • Still another aspect of the present invention provides a method for applying a floating gate transistor fabricated by using the method of fabricating a floating gate transistor, comprising the steps of: connecting a control gate and a source with a pre- The voltage source, the channel region and the drain are grounded; after a predetermined time, the power is turned off, a predetermined amount of negative charges are accumulated on the floating gate, and the threshold voltage of the floating gate transistor reaches a set value.
  • the method further includes: testing a voltage of the thin film transistor, grounding the control gate and the source when the voltage of the thin film transistor exceeds a preset adjustment voltage, and connecting the channel region and the drain to the preset voltage The power supply; when the voltage of the thin film transistor is less than a preset adjustment voltage, the returning step connects the control gate and the source to a power source having a preset voltage, and the channel region and the drain of the polysilicon film are grounded.
  • FIG. 1 is a schematic view showing the structure of a floating gate MOS transistor in the prior art
  • FIG. 2 is a schematic structural view of a floating gate thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a plan view showing a floating gate thin film transistor according to an embodiment of the present invention.
  • 4 to 21 are schematic structural views showing the first step to the eighteenth step of the method for fabricating a floating gate transistor according to an embodiment of the present invention
  • FIG. 22 is a schematic diagram showing a power connection structure of a floating gate transistor application method according to an embodiment of the present invention
  • FIG. 23 is a schematic diagram showing a power connection structure of a floating gate transistor application method according to an embodiment of the present invention.
  • the floating gate technology is currently widely used in EPROM, EEPROM, Flash memory and other devices.
  • a device having a memory function is also required, but due to factors such as manufacturing process and demand, a device having a memory function has not been fabricated on a glass substrate.
  • an embodiment of the present invention provides a floating gate transistor including a substrate 1, a floating gate 3, a source 4, a drain 5, and a control gate 6 disposed on the substrate 1. .
  • the floating gate transistor further includes a first insulating film 7 and a polysilicon film 8 which are sequentially disposed on the substrate 1.
  • a channel region 2 is formed in the polysilicon film 8, and the position of the channel region 2 corresponds to the position of the floating gate 3. That is, the polysilicon film 8 serves as an active layer of the TFT.
  • a second insulating film 9 and a third insulating film 10 are sequentially disposed on the polysilicon film 8, and the floating gate 3 is interposed between the second insulating film 9 and the third insulating film 10.
  • the third insulating film 10 is disposed on both sides of the floating gate 3 (also on both sides of the channel region of the polysilicon film 8), and is respectively provided with a first opening and a second opening, the first opening and the second opening
  • the openings extend inwardly to the polysilicon film 8 to form source vias 41 and drain vias 51, respectively.
  • the source via 41 and the drain via 51 are provided with a metal thin film in contact with the source region and the drain region of the polysilicon film 8 to form the source 4 and the drain 5, respectively.
  • a portion of the third insulating film 10 corresponding to the floating gate 3 is provided with a metal film to form the control gate 6.
  • the control gate 6 corresponds to the channel region of the polysilicon film 8 via the floating gate 3; the planar area of the control gate 6 may be greater than or equal to the planar area of the floating gate 3.
  • a metal film is deposited on the third insulating film 10, and the metal film covers the exposed portion of the polysilicon film 8 at the same time, and then exposed to the third insulating film 10 by photolithography.
  • the control gate 6 is formed at a corresponding position, and the source 4 and the drain 5 are formed in the exposed portions of the polysilicon film 8, respectively.
  • Source 4 and drain 5 can also be connected to respective wirings or devices, respectively, as desired.
  • the source 4 and the drain 5 may be connected to the data line and the pixel electrode, respectively. These wirings connected to the source 4 and the drain 5 can be prepared together with the source 4 and the drain 5.
  • the first insulating film, the second insulating film, and the third insulating film may be made of one or a combination of SiOx, SiNx, and SiOxNy.
  • the floating gate technology is applied to the field of TFTs
  • the substrate may be a glass substrate (or a quartz substrate, a plastic substrate, etc.), so that the floating gate transistor applied to the display driving circuit can store charges, and can be further used for adjustment.
  • TFT threshold voltage TFT threshold voltage
  • the floating gate transistor of the present embodiment is capable of adjusting the threshold voltage of the TFT, and eliminates the problem that the entire circuit does not operate due to the inaccuracy of the threshold voltage of the TFT in the production process of the backplane such as the LCD.
  • GOA Gate On Array
  • COA Color Filter on Array
  • one pixel uses several MOS transistors for compensation, driving and other functions. If the technique of this embodiment is used, the number of MOS transistors can be greatly reduced, the number of pixels and the resolution of the display can be increased.
  • GOA technology is a high-tech design in TFT-LCD.
  • the basic concept is to integrate the gate drive of the liquid crystal panel on the glass substrate to form a scan drive circuit for the panel; COA integrates the color filter and the array substrate.
  • One of the integration technologies together.
  • An embodiment of the present invention further provides a method for fabricating a floating gate transistor, comprising the steps of: sequentially forming a first insulating film 7 and a polysilicon film 8 on a substrate;
  • a source 4, a drain 5, and a control gate 6 are formed on the third insulating film.
  • An example of sequentially forming the first insulating film 7 and the polysilicon film 8 on the substrate includes: sequentially depositing the first insulating film 7 and the first amorphous silicon film 81 on the substrate 1; performing annealing treatment to make The first layer of amorphous silicon film 81 forms the polysilicon film 8.
  • the polysilicon film 8 can be patterned to obtain an island-like pattern, for example, a photolithography process.
  • An example of forming a channel region in the polysilicon film 8 includes: coating a surface of the polysilicon film 8 with a first layer of photoresist 11, exposing and developing the first layer of photoresist 11, the polysilicon film a region on the 8 corresponding to the unretained region of the first layer of photoresist 11 is used to obtain a channel region, that is, the first layer of photoresist 11 exposes a channel region; and borane is implanted in the channel region
  • the ionic or phosphonium ions are such that the polysilicon film 8 located in the channel region forms P-type polysilicon or N-type polysilicon; the first layer of photoresist 11 is removed by a lift-off process; and then, an annealing process is performed.
  • a second insulating film 9 and a third insulating film 10 are formed on the polysilicon film 8, and an example of the floating gate 3 disposed between the second insulating film 9 and the third insulating film 10 includes: A second insulating film 9 and a second amorphous silicon film 12 are sequentially deposited on the polysilicon film 8 by vapor deposition; a second layer of photoresist 13 is coated on the surface of the second amorphous silicon film 12.
  • the floating gate 3 can also be made of materials other than the crystalline silicon film.
  • An example of forming a source region and a drain region in the polysilicon film includes: applying a third layer of photoresist 14 on the third layer of insulating film 10, exposing the third layer of photoresist 14, Developing; then, etching the second insulating film 9 and the third insulating film 10 to remove the second insulating film 9, the third insulating film 10, and the third A region corresponding to the unretained region of the layer photoresist 14 is provided with a first via hole and a second via hole to expose the source region 82 and the drain region 83 in the polysilicon film 8.
  • One example of forming the control gate 6 on the third insulating film 10 includes: heavily doping borane ions or phosphonium ions in the source region 82 and the drain region 83 so that the source The region 82 and the drain region 83 are in good contact with the metal thin film deposited in the subsequent step; peeling off the third layer of photoresist 14; using the vapor deposition method on the second insulating film 9, the third layer A non-etched region of the insulating film 10 and a source region 82 and a drain region 83 formed on the polysilicon film 8 are deposited with a metal film 15; a fourth layer of photoresist 16 is deposited on the metal film 15 to The fourth layer of photoresist 16 is exposed and developed; etching is performed to form a control gate 6 on the metal film 15, and the fourth layer of photoresist 16 is stripped.
  • the metal thin film 15 can be, for example, aluminum or aluminum alloy. Preparation of copper, copper alloy, etc.
  • the method of fabricating the floating gate transistor is as follows:
  • the first insulating film 7 and the first amorphous silicon film 81 are sequentially grown on the substrate 1 by PECVD (plasma enhanced vapor deposition) as shown in FIG. 4; then, an ELA (excimer laser annealing) process is used to make the non-
  • the crystalline silicon film 81 becomes a polysilicon film 8, as shown in FIG. 5; a first photoresist layer 11 is formed using a mask (lithography) process, and the first photoresist layer 11 is exposed to the channel region 2, as shown in 6 is shown.
  • the lithography process generally includes processing such as gluing, exposure, development, etc., and will not be described in detail herein.
  • the second amorphous silicon film is used.
  • 12 is etched into the floating gate 3, as shown in FIG. 12; using the lift-off process, the second layer of photoresist 13 on the surface is stripped, as shown in FIG. 13; the third insulating film 10 is grown by PECVD, and the third layer is insulated.
  • the film 10 completely covers the floating gate 3 as shown in FIG. 14; a region for forming the source via 41 and the drain via 51 of the transistor is exposed in the third layer photoresist 14 using a mask process, such as Figure 15; using an etching process, etching the source a hole 41 and a drain via 51, as shown in FIG.
  • a region where the heavily doped polysilicon film 8 is exposed using a doping process results in a source region 82 and a drain region 83, for example, a source via 41 and a drain.
  • a borane ion or a phosphorus ion is implanted in a corresponding region of the via 51, as shown in FIG. 17; a third layer of photoresist 14 is removed by a lift-off process, as shown in FIG. 18; using sputtering (spraying) a device, depositing a metal film 15 as shown in FIG.
  • Embodiments of the present invention also provide an application method of a floating gate transistor fabricated by using the floating gate transistor fabrication method, including the following steps: connecting a control gate and a source to a power supply having a preset voltage, and a channel region And draining the ground; after a predetermined time, the power is turned off, a predetermined amount of negative charges are accumulated on the floating gate, and the threshold voltage of the floating gate transistor reaches a set value. The threshold voltage of the transistor is changed by whether or not the charge or stored charge is stored on the floating gate. After a preset time, the floating gate can store enough charge.
  • the preset voltage in the embodiment is 25V, but the present invention is not limited thereto, and an appropriate preset voltage can be selected according to the prepared TFT.
  • the returning step connects the control gate and the source to a power source having a preset voltage, and the channel region and the drain of the polysilicon film are grounded.
  • the voltage of the floating gate transistor exceeds a preset adjustment voltage
  • the voltage can also be performed by ultraviolet irradiation.
  • the process of adjusting the threshold voltage of the TFT is as follows: Connect the programming power supply VCC to the control gate and source, ground the channel region and the drain, as shown in FIG. 22; apply a power supply of 25V to the programming power supply, as needed The amount of the adjusted floating gate charge controls the programming time, as shown in Figure 23; after the programming power supply is applied, the source, drain, and channel regions are all disconnected from the programming supply.
  • TFT threshold voltage the voltage required for the floating gate transistor to start normally
  • the floating gate of the floating gate transistor can store a certain amount of charge, and the control gate needs to add the voltage of the floating gate to drive the transistor normally on the basis of the normal driving voltage.
  • the floating gate is used to adjust the threshold voltage of the TFT by this principle. This method avoids the inconsistency of the threshold voltage of the TFT, so that the entire circuit does not work normally, resulting in a large increase in cost.
  • the floating gate transistor adjusts the threshold voltage of the TFT. After the final process is completed, according to the threshold voltage test of the TFT, the floating gate charge is programmed for the TFT whose threshold voltage is not in the normal range, so that it can be reused, which greatly improves the product. Yield.
  • An embodiment of the present invention further provides a display driving circuit including a floating gate transistor.
  • the floating gate transistor includes a substrate 1 , a floating gate 3 , a source 4 , and a drain 5 disposed on the substrate 1 .
  • the floating gate transistor further includes a first insulating film 7 and a polysilicon film 8 sequentially disposed on the substrate 1, and a channel region 2 is formed in a middle portion of the polysilicon film 8, the position of the channel region 2 Corresponding to the position of the floating gate 3.
  • the arrangement of the channel region 2 facilitates the fabrication of the floating gate during the fabrication of the floating gate transistor. This is because if the bottom gate structure is used, the ELA process may cause damage to the metal gate.
  • a second insulating film 9 and a third insulating film 10 are sequentially disposed on the polysilicon film 8, and the floating gate 3 is disposed between the second insulating film 9 and the third insulating film 10.
  • the third insulating film 10 is respectively disposed on the two sides of the floating gate 3 with a first opening and a second opening, and the first opening and the second opening respectively extend inward to form a source of the polysilicon film 8 a via hole 41 and a drain via 51, wherein the source via 41 and the drain via 51 are provided with metal thin films in contact with the source region and the drain region of the polysilicon film 8, respectively, forming the source 4 And drain 5.
  • a portion of the third insulating film 10 corresponding to the floating gate 3 is deposited with a metal thin film to form the control gate 6.
  • the control gate 6 also corresponds to the channel region 2.
  • a metal film is deposited on the third insulating film 10, and the metal film covers a portion of the polysilicon film 8 exposed by the third insulating film 10, and then exposed by lithography.
  • the control electrode 6 is formed at a corresponding position of the third insulating film 10, and the source 4 and the drain 5 are formed in the exposed portions of the polysilicon film 8, respectively.
  • the first insulating film, the second insulating film, and the third insulating film may be formed by using one or a combination of SiOx, SiNx, and SiOxNy. (only part of the structure of the floating gate transistor is shown in Figure 2)
  • the floating gate transistor of the embodiment of the present invention can be used to replace the thin film transistor of the prior art, and the threshold voltage of the floating gate transistor is adjustable, thereby avoiding the occurrence of a situation in which the entire driving circuit cannot work normally due to the discrepancy of the TFT voltage.
  • An embodiment of the present invention further provides a method for manufacturing a display driving circuit, comprising the steps of: fabricating each electronic component of a display driving circuit on a PCB, wherein the manufacturing process of the floating gate transistor comprises:
  • a source 4, a drain 5, and a control gate 6 are formed on the third insulating film.
  • An example of sequentially forming the first insulating film 7 and the polysilicon film 8 on the substrate includes: sequentially depositing the first insulating film 7 and the first amorphous silicon film 81 on the substrate 1; performing annealing treatment to make The first layer of amorphous silicon film 81 forms the polysilicon film 8.
  • An example of forming a channel region on the polysilicon film 8 includes: coating a surface of the polysilicon film 8 with a first layer of photoresist 11, exposing and developing the first layer of photoresist 11, the polysilicon film a region of 8 that corresponds to an unretained region of the first layer of photoresist 11 is used to obtain a channel region; a borane ion or a phosphonium ion is implanted in the channel region such that the channel is located in the channel
  • the polysilicon film 8 of the region forms P-type polysilicon or N-type polysilicon; the first layer of photoresist 11 is removed by a lift-off process; and an annealing treatment is performed.
  • a second insulating film 9 and a third insulating film 10 are formed on the polysilicon film 8, and an example of the floating gate 3 disposed between the second insulating film 9 and the third insulating film 10 includes: A second insulating film 9 and a second amorphous silicon film 12 are sequentially deposited on the polysilicon film 8 by vapor deposition; a second layer of photoresist 13 is coated on the surface of the second amorphous silicon film 12.
  • An example of forming a source region and a drain region in the polysilicon film includes: applying a third layer of photoresist 14 on the third layer of insulating film 10, exposing the third layer of photoresist 14, Developing, exposing a portion corresponding to the source region and the drain region; etching the second insulating film 9 and the third insulating film 10 to remove the second insulating film 9, the A source region 82 and a drain region 83 are formed on the polysilicon film 8 in a region of the three-layer insulating film 10 corresponding to the unretained region of the third layer of photoresist 14.
  • One example of forming the control gate 6 on the third insulating film 10 includes: heavily doping borane ions or phosphonium ions in the source region 82 and the drain region 83 so that the source The region 82 and the drain region 83 are in good contact with the metal thin film deposited in the subsequent step; peeling off the third layer of photoresist 14; using the vapor deposition method on the second insulating film 9, the third layer An unetched region of the insulating film 10 and a source region 82 and a drain region 83 formed on the polysilicon film 8 are deposited with a metal film 15; a fourth layer of photoresist 16 is coated on the metal film 15 The fourth layer of photoresist 16 is exposed and developed; the metal film 15 is etched, a control gate 6 is formed on the metal film 15, and the fourth layer of photoresist 16 is peeled off.
  • Embodiments of the present invention also provide an application method of a display driving circuit.
  • the calibration can be performed by adjusting the threshold voltage of the floating gate transistor in the display driving circuit, so that the display driving circuit can work normally, wherein the floating gate transistor threshold voltage adjusting process comprises: connecting the control gate and the source with a preset voltage The power supply, the channel region and the drain are grounded; after a predetermined time, the power is turned off, a predetermined amount of negative charges are accumulated on the floating gate, and the threshold voltage of the floating gate transistor reaches a set value.
  • the threshold voltage of the transistor is changed by whether or not the charge is stored or stored on the floating gate.
  • the floating gate can store enough charge for a preset time.
  • the preset voltage in the embodiment is 25V, but the present invention is not limited thereto, and other suitable voltages may be used according to specific structures and materials.
  • the returning step connects the control gate and the source to a power source having a predetermined voltage, and the channel region and the drain of the polysilicon film are grounded.
  • voltage release can also be performed by ultraviolet irradiation.
  • the process of adjusting the threshold voltage of the TFT is as follows: The control gate and source are connected to the programming power supply VCC, the channel region and the drain are grounded, as shown in FIG. 22; the programming power supply applies a 25V power supply, as needed The amount of the adjusted floating gate charge controls the programming time, as shown in Figure 23; after the programming power supply is applied, the source, drain, and channel region poles are all disconnected from the programming power supply.
  • Test the TFT threshold voltage to determine whether the TFT threshold voltage meets the conditions for normal operation of the circuit. If it does not match, continue to adjust according to the above steps.
  • the floating gate of the floating gate transistor can store a certain amount of charge, and the control gate needs to add the voltage of the floating gate to drive the transistor normally on the basis of the normal driving voltage.
  • the floating gate is used to adjust the threshold voltage of the TFT by this principle. This method avoids the inconsistency of the threshold voltage of the TFT, so that the entire circuit does not work normally, resulting in a large increase in cost.
  • the floating gate transistor adjusts the threshold voltage of the TFT. After the final process is completed, according to the threshold voltage test of the TFT, the floating gate charge is programmed for the TFT whose threshold voltage is not in the normal range, so that the reuse can be repeated, and the yield of the product is greatly improved. .

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Abstract

提供一种悬浮栅晶体管及其制作方法、应用方法、显示器驱动电路。悬浮栅晶体管包括基板（1），设置在基板（1）上的悬浮栅极（3）、源极（4）、漏极（5）和控制栅极（6），还包括：基板（1）上依次设置的第一层绝缘薄膜（7）、多晶硅薄膜（8），多晶硅薄膜（8）中形成有沟道区域（2），沟道区域（2）的位置与悬浮栅极（3）的位置相对应。

Description

悬浮栅晶体管及其制作方法、 应用方法、 显示器驱动电路 技术领域
本发明的实施例涉及一种基于薄膜晶体管 （TFT )制作工艺的一种悬浮 栅晶体管及其制作方法、 应用方法、 显示器驱动电路。 背景技术
悬浮栅技术早在 20世纪 60年代已经提出， 但是由于受到当时制造技术 的限制， 一直到 80年代才被应用到存储领域。 如今的 EPROM, EEPROM, Flash存储器等都应用了悬浮栅技术。
"悬浮栅" 一词源于一种特殊的 MOS晶体管。 这种晶体管有源极 104、 漏极 105, 两个栅极。 其中的一个栅极有电气连接， 叫控制栅 100, 作为一般 意义上的栅极。 另一个栅极没有外引线， 它被完全包裹在两层 Si02 薄膜 102层里面， 是浮空的， 所以称之为悬浮栅 103, 如图 1所示。
悬浮栅 MOS 晶体管的工作原理是利用悬浮栅上是否储存有电荷或储存 电荷的多少来改变 MOS晶体管的阈值电压， 从而改变 MOS晶体管的外部 特性。 这个过程可描述如下。 当在 MOS晶体管的漏、 栅极加上足够高的电 压 (如 25 V ) ，且源极及村底接地时，漏极及村底之间的 PN结反向击穿， 产 生大量的高能电子。 这些电子穿过 4艮薄的 SiOx 薄膜层堆积在悬浮栅上， 从 而使悬浮栅带有负电荷。如这一过程维持足够长， 悬浮栅将积累足够的电子。 当移去外加电压后， 悬浮栅上的电子由于没有放电回路，所以能够长期保存。 当悬浮栅上带有负电荷时， 村底表面感应的是正电荷， 这就使得 MOS 晶 体管的开启电压变高。 这时， 原来能使 MOS晶体管导通的阈值电压加在此 时的 MOS晶体管栅极上， MOS晶体管将仍旧处于截止状态。 存储单元就是 利用这一原理来存储二进制数据的。 悬浮栅上的电荷可通过以下两种方法得 以修改：
(1)通过紫外线长时间的照射。 当紫外线照射时， 浮栅上的电子形成光 电巟而泄放。
(2)通过在漏、 栅之间加一大电压 (漏接电源正端， 栅接负端）。 这一大 电压将在 SiOx薄膜层中产生一强电场， 将电子从悬浮栅拉回到村底中， 从 而实现悬浮栅电荷的修改。
以上介绍悬浮栅技术， 都是基于半导体制造工艺， 在薄膜晶体管（TFT ) 制造领域目前还没有相应的制造技术。 发明内容
为了解决上述技术问题，本发明的实施例提供一种基于 TFT制造技术的 悬浮栅晶体管及其制作方法、 应用方法、 显示器驱动电路， 该悬浮栅极能够 存储一定的电荷， 从而能够起到存储数据的作用。
本发明的一个方面提供了一种悬浮栅晶体管， 包括基板， 设置在基板上 的悬浮栅极、 源极、 漏极和控制栅极， 还包括： 所述基板上依次设置的第一 层绝缘薄膜、 多晶硅薄膜， 所述多晶硅薄膜中形成有沟道区域， 所述沟道区 域的位置与所述悬浮栅极的位置相对应。
例如， 所述多晶硅薄膜上依次设置第二层绝缘薄膜和第三层绝缘薄膜， 所述第二层绝缘薄膜和第三层绝缘薄膜之间设有所述悬浮栅极。
例如， 所述第三层绝缘薄膜位于所述悬浮栅极的两侧分别设有第一开口 和第二开口， 所述第一开口和第二开口分别延伸至所述多晶硅薄膜形成源极 过孔和漏极过孔， 所述源极过孔和所述漏极过孔内设有金属薄膜分别形成源 极和漏极。
例如， 所述第三层绝缘薄膜的与所述悬浮栅极相对应的部位沉积一层金 属薄膜形成控制栅极。
例如， 所述第一层绝缘薄膜、 第二层绝缘薄膜、 第三层绝缘薄膜采用 SiOx、 SiNx、 SiOxNy中的一种或两种制作。
本发明的另一个方面还提供了一种显示器驱动电路， 包括上述的悬浮栅 晶体管。
本发明的再一个方面还提供了一种悬浮栅晶体管制作方法， 包括以下步 骤： 在基板上依次形成第一层绝缘薄膜和多晶硅薄膜； 在所述多晶硅薄膜中 形成沟道区域;在所述多晶硅薄膜上形成第二层绝缘薄膜和第三层绝缘薄膜， 以及设置在第二层绝缘薄膜和第三层绝缘薄膜之间的悬浮栅极； 在所述多晶 硅薄膜中形成源极区域和漏极区域;在所述第三层绝缘薄膜上形成控制栅极。 例如， 在基板上依次形成第一层绝缘薄膜和多晶硅薄膜， 包括： 在基板 上依次沉积所述第一层绝缘薄膜和非晶硅薄膜； 进行退火处理， 使得所述非 晶硅薄膜形成所述多晶硅薄膜。
例如， 在所述多晶硅薄膜中形成沟道区域， 包括： 在所述多晶硅薄膜表 面涂覆第一层光刻胶， 光刻曝光， 所述多晶硅薄膜上与所述第一层光刻胶的 未保留区域相对应的区域为沟道区域； 在所述沟道区域注入硼烷离子或磷烷 离子，使得所述位于所述沟道区域的所述多晶硅薄膜形成 P型多晶硅或 N型 多晶硅； 采用剥离工艺去除所述第一层光刻胶； 进行退火处理。
例如， 在所述多晶硅薄膜中形成第二层绝缘薄膜和第三层绝缘薄膜， 以 及设置在第二层绝缘薄膜和第三层绝缘薄膜之间的悬浮栅极包括： 采用气相 沉积法在所述多晶硅薄膜上依次沉积第二层绝缘薄膜、 第二层非晶硅薄膜； 在所述第二层非晶硅薄膜表面涂覆第二层光刻胶、 光刻曝光， 使得该第二层 光刻胶的保留区域与所述沟道区域相对应； 采用刻蚀工艺， 保留所述第二层 非晶硅薄膜上与所述沟道区域相对应的区域， 形成悬浮栅极； 剥离所述第二 层光刻胶； 采用气相沉积法在所述第二层绝缘薄膜表面、 所述悬浮栅极表面 沉积第三层绝缘薄膜。
例如， 在所述多晶硅薄膜中形成源极区域和漏极区域包括： 在所述第三 层绝缘薄膜上涂覆第三层光刻胶， 将该第三层光刻胶曝光、 显影； 对所述第 二层绝缘薄膜、 所述第三层绝缘薄膜进行刻蚀， 去除所述第二层绝缘薄膜、 所述第三层绝缘薄膜上与所述第三层光刻胶的未保留区域相对应的区域， 在 所述多晶硅薄膜中形成源极区域和漏极区域。
例如， 在所述第三层绝缘薄膜上形成控制栅极包括： 在所述源极区域和 所述漏极区域重掺杂硼烷离子或磷烷离子， 形成良好的导电层； 剥离所述第 三层光刻胶； 采用气相沉积法在所述第二层绝缘薄膜、 所述第三层绝缘薄膜 的未刻蚀区域以及所述多晶硅薄膜中形成的源极区域和漏极区域上沉积一层 金属薄膜； 在所述金属薄膜上沉积第四层光刻胶， 将该第四层光刻胶曝光、 显影； 进行刻蚀， 在所述金属薄膜上形成源极、 漏极、 控制栅极； 剥离所述 第四层光刻胶。
本发明的再一个方面还提供一种采用所述的悬浮栅晶体管制作方法制成 的悬浮栅晶体管的应用方法， 包括以下步骤： 将控制栅极和源极连接具有预 设电压的电源， 沟道区域和漏极接地； 经过一预设时间后断开电源， 所述悬 浮栅极上累积预定数量的负电荷， 所述悬浮栅晶体管的阈值电压达到设定数 值。
例如， 该方法还包括： 测试薄膜晶体管的电压， 在所述薄膜晶体管的电 压超过预设调整电压时， 将控制栅极和源极接地， 沟道区域和漏极连接具有 所述预设电压的电源； 当所述薄膜晶体管的电压小于预设调整电压时， 返回 步骤将控制栅极和源极连接具有预设电压的电源， 多晶硅薄膜的沟道区域和 漏极接地。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1表示现有技术中悬浮栅 MOS晶体管结构示意图；
图 2表示本发明实施例的悬浮栅薄膜晶体管结构示意图；
图 3表示本发明实施例的悬浮栅薄膜晶体管的平面示意图；
图 4-图 21分别表示本发明实施例的悬浮栅晶体管制作方法第一步骤至 第十八步骤中的结构示意图；
图 22表示本发明实施例的悬浮栅晶体管应用方法电源连接结构示意图； 图 23表示本发明实施例的悬浮栅晶体管应用方法电源连接结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个" 、 "一" 或者 "该"等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或 者物件涵盖出现在 "包括"或者 "包含"后面列举的元件或者物件及其等同， 并不排除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定 于物理的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间 接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被 描述对象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
悬浮栅技术目前广泛应用在 EPROM, EEPROM, Flash存储器等器件中。 但是在 TFT行业， 同样需要有存储功能的器件， 但是受到制造工艺， 需求度 等因素的影响， 一直没有在玻璃基板上制造出具有存储功能的器件。
如图 2和图 3所示， 本发明的一个实施例提供了一种悬浮栅晶体管， 包 括基板 1 , 设置在基板 1上的悬浮栅极 3、 源极 4、 漏极 5和控制栅极 6。
该悬浮栅晶体管还包括在所述基板 1上依次设置的第一层绝缘薄膜 7、 多晶硅薄膜 8。该多晶硅薄膜 8中形成沟道区域 2,所述沟道区域 2的位置与 所述悬浮栅极 3的位置相对应。 即多晶硅薄膜 8作为 TFT的有源层。
所述多晶硅薄膜 8上依次设置第二层绝缘薄膜 9和第三层绝缘薄膜 10, 所述第二层绝缘薄膜 9和第三层绝缘薄膜 10之间夹设有所述悬浮栅极 3。
所述第三层绝缘薄膜 10位于所述悬浮栅极 3的两侧（同样在多晶硅薄膜 8 的沟道区域两侧）分别设有第一开口和第二开口， 所述第一开口和第二开 口分别向内延伸至所述多晶硅薄膜 8形成源极过孔 41和漏极过孔 51。 所述 源极过孔 41和所述漏极过孔 51内设有与多晶硅薄膜 8的源极区和漏极区接 触的金属薄膜以分别形成源极 4和漏极 5。
所述第三层绝缘薄膜 10与所述悬浮栅极 3相对应的部位设置一层金属薄 膜形成控制栅极 6。 控制栅极 6隔着悬浮栅极 3与多晶硅薄膜 8的沟道区相 对应； 控制栅极 6的平面面积可以大于或等于悬浮栅极 3的平面面积。
实际应用中，所述第三层绝缘薄膜 10上沉积一层金属薄膜，所述金属薄 膜同时覆盖所述多晶硅薄膜 8的外露的部分， 然后经过光刻曝光在所述第三 层绝缘薄膜 10的相应位置形成所述控制栅极 6,在所述多晶硅薄膜 8的外露 的部分分别形成源极 4和漏极 5。 根据需要，源极 4和漏极 5还可以分别连接到相应的布线或器件。例如， 上述薄膜晶体管作为像素的开关元件时， 源极 4和漏极 5可以分别连接到数 据线和像素电极。 这些连接到源极 4和漏极 5的布线可以随源极 4和漏极 5 一起制备。
本实施例中， 例如， 第一层绝缘薄膜、 第二层绝缘薄膜、 第三层绝缘薄 膜均可以采用 SiOx、 SiNx、 SiOxNy中的一种或几种组合而制成。
本实施例中， 将悬浮栅技术应用到 TFT领域， 所述基板可以为玻璃基板 (或石英基板、 塑料基板等） ， 使得应用于显示器驱动电路的悬浮栅晶体管 可以存储电荷， 进一步的可用于调整 TFT阈值电压。
本实施例悬浮栅晶体管能够调节 TFT阈值电压， 消除了在例如 LCD的 背板生产过程中， 由于 TFT阈值电压不准使得整个电路不工作的问题。 在低 温多晶硅技术， GOA ( Gate On Array ) , COA ( Color Filter on Array )等技 术中， 一个像素使用几个 MOS 晶体管， 用来实现补偿、 驱动等功能。 如果 使用本实施例的技术， 可以大大减少 MOS 晶体管的个数， 增加像素的个数 和显示器的分辨率。
GOA技术是 TFT-LCD中一种高技术水平设计， 基本概念是将液晶面板 的栅极驱动集成在玻璃基板上， 形成对面板的扫描驱动电路； COA是将彩色 滤光片与阵列基板集成在一起的其中一种集成技术。
本发明的一个实施例还提供一种悬浮栅晶体管制作方法，包括以下步骤： 在基板上依次形成第一层绝缘薄膜 7和多晶硅薄膜 8;
在所述多晶硅薄膜 8中形成沟道区域 2;
在所述多晶硅薄膜 8上形成第二层绝缘薄膜 9和第三层绝缘薄膜 10, 以 及设置在第二层绝缘薄膜 9和第三层绝缘薄膜 10之间的悬浮栅极 3;
在所述多晶硅薄膜 8中形成源极区域和漏极区域；
在所述第三层绝缘薄膜上形成源极 4、 漏极 5、 控制栅极 6。
在基板上依次形成第一层绝缘薄膜 7和多晶硅薄膜 8的一个示例包括： 在基板 1上依次沉积所述第一层绝缘薄膜 7和第一层非晶硅薄膜 81;进行退 火处理， 使得所述第一层非晶硅薄膜 81形成所述多晶硅薄膜 8。
在制备了多晶硅薄膜 8之后， 如果需要形成用于 TFT的岛状有源层， 可 以对多晶硅薄膜 8进行构图以得到岛状图案， 构图方法例如为光刻工艺。 在所述多晶硅薄膜 8中形成沟道区域的一个示例包括： 在所述多晶硅薄 膜 8表面涂覆第一层光刻胶 11 , 对该第一层光刻胶 11曝光、 显影， 所述多 晶硅薄膜 8上与所述第一层光刻胶 11的未保留区域相对应的区域用于得到沟 道区域， 即第一层光刻胶 11暴露出沟道区域；在所述沟道区域注入硼烷离子 或磷烷离子， 使得所述位于所述沟道区域的所述多晶硅薄膜 8形成 P型多晶 硅或 N型多晶硅； 采用剥离工艺去除所述第一层光刻胶 11; 然后， 进行退火 处理。
在所述多晶硅薄膜 8上形成第二层绝缘薄膜 9和第三层绝缘薄膜 10, 以 及设置在第二层绝缘薄膜 9和第三层绝缘薄膜 10之间的悬浮栅极 3的一个示 例包括：采用气相沉积法在所述多晶硅薄膜 8上依次沉积第二层绝缘薄膜 9、 第二层非晶硅薄膜 12; 在所述第二层非晶硅薄膜 12表面涂覆第二层光刻胶 13、 将该第二层光刻胶 13曝光、 显影， 使得该第二层光刻胶 13的保留区域 与所述沟道区域相对应；采用刻蚀工艺，保留所述第二层非晶硅薄膜 12上与 所述沟道区域相对应的区域， 形成悬浮栅极 3; 剥离所述第二层光刻胶 13; 采用气相沉积法在所述第二层绝缘薄膜 9表面、 所述悬浮栅极 3表面沉积第 三层绝缘薄膜 10。 悬浮栅极 3也可以采用除非晶硅薄膜之外的材料。
在所述多晶硅薄膜中形成源极区域和漏极区域的一个示例包括： 在所述 第三层绝缘薄膜 10上涂覆第三层光刻胶 14, 将该第三层光刻胶 14曝光、 显 影； 然后， 对所述第二层绝缘薄膜 9、 所述第三层绝缘薄膜 10进行刻蚀， 去 除所述第二层绝缘薄膜 9、所述第三层绝缘薄膜 10上与所述第三层光刻胶 14 的未保留区域相对应的区域， 得到第一过孔和第二过孔， 露出在所述多晶硅 薄膜 8中的源极区域 82和漏极区域 83。
在所述第三层绝缘薄膜 10上形成控制栅极 6的一个示例包括:在所述源 极区域 82和所述漏极区域 83重掺杂硼烷离子或磷烷离子， 以便所述源极区 域 82和所述漏极区域 83与后续步骤中沉积的金属薄膜接触良好； 剥离所述 第三层光刻胶 14; 采用气相沉积法在所述第二层绝缘薄膜 9、 所述第三层绝 缘薄膜 10的未刻蚀区域以及所述多晶硅薄膜 8上形成源极区域 82和漏极区 域 83沉积一层金属薄膜 15;在所述金属薄膜 15上沉积第四层光刻胶 16,将 该第四层光刻胶 16曝光、 显影； 进行刻蚀， 在所述金属薄膜 15上形成控制 栅极 6; 剥离所述第四层光刻胶 16。 金属薄膜 15可以采用例如铝、 铝合金、 铜、 铜合金等制备。
在一具体实施例中， 悬浮栅晶体管制作方法如下：
使用 PECVD (等离子增强气相沉积法）在基板 1依次生长第一层绝缘 薄膜 7和第一层非晶硅薄膜 81 , 如图 4所示； 然后， 使用 ELA (准分子激光 退火）工艺， 使得非晶硅薄膜 81变成多晶硅薄膜 8, 如图 5所示； 使用掩膜 (光刻）工艺， 形成第一光刻胶层 11 , 该第一光刻胶层 11露出沟道区域 2, 如图 6所示。 光刻工艺一般包括涂胶、 曝光、 显影等处理， 在此不再详述。
使用掺杂工艺， 掺杂 B2H6 (硼烷）或 PH3 (磷烷） ， 使得沟道区域 2 变成 P+多晶硅（P型多晶硅）或 N+多晶硅（N型多晶硅） ， 如图 7所示； 使用剥离工艺， 剥去表面的第一层光刻胶 11 , 如图 8所示； 使用退火设备， 活化 P+多晶硅， 如图 9所示； 使用 PECVD依次生长第二层绝缘薄膜 9和第 二层非晶硅薄膜 12, 如图 10所示； 使用掩膜工艺， 得到的第二层光刻胶 13 挡住沟道区域 2上方部分， 如图 11所示； 使用刻蚀工艺，将第二非晶硅薄膜 12刻蚀为悬浮栅 3, 如图 12所示； 使用剥离工艺， 剥去表面第二层光刻胶 13, 如图 13所示； 使用 PECVD生长第三层绝缘薄膜 10, 该第三层绝缘薄 膜 10完全覆盖悬浮栅极 3 , 如图 14所示； 使用掩膜工艺， 在第三层光刻胶 14中露出用于形成晶体管的源极过孔 41和漏极过孔 51的区域， 如图 15所 示； 使用刻蚀工艺， 刻蚀出源极过孔 41和漏极过孔 51 , 如图 16所示； 使用 掺杂工艺，重掺杂多晶硅薄膜 8露出的区域得到源极区域 82和漏极区域 83, 例如在源极过孔 41和漏极过孔 51相对应的区域中注入硼烷离子或磷烷离子， 如图 17所示； 使用剥离工艺， 剥去表面第三层光刻胶 14, 如图 18所示； 使 用溅射（喷涂）设备， 沉积一层金属薄膜 15, 如图 19所示； 使用掩膜工艺， 在第四层光刻胶 16中漏出将要形成晶体管的源极、漏极、控制栅极所对应的 区域， 如图 20所示； 蚀刻金属薄膜 15 , 得到源极 4、 漏极 5和控制栅极 6, 源极 4和漏极 5分别与源极区域 82和漏极区域 83接触； 使用剥离工艺， 剥 去表面第四层光刻胶 16, 如图 21所示。
本发明的实施例还提供一种采用所述悬浮栅晶体管制作方法制成的悬浮 栅晶体管的应用方法， 包括以下步骤： 将控制栅极和源极连接具有预设电压 的电源， 将沟道区域和漏极接地； 经过一预设时间后断开电源， 所述悬浮栅 极上累积预定数量的负电荷， 所述悬浮栅晶体管的阈值电压达到设定数值。 利用悬浮栅上是否储存有电荷或储存电荷的多少来改变晶体管的阈值电 压， 经过预设时间， 悬浮栅极可以存储足够的电荷。
本实施例中所述预设电压为 25V, 但本发明并不限于此， 可以根据制备 的 TFT来选择适当的预设电压。
测试悬浮栅晶体管的电压， 在所述悬浮栅晶体管的电压超过预设调整电 压时， 将控制栅极和源极接地， 沟道区域和漏极连接具有所述预设电压的电 源； 当所述悬浮栅晶体管的电压小于预设调整电压时， 返回步骤将控制栅极 和源极连接具有预设电压的电源， 多晶硅薄膜的沟道区域和漏极接地。
当所述悬浮栅晶体管的电压超过预设调整电压时， 还可以通过紫外线照 射的方式进行电压! ^放。
在一个实施例中， 调整 TFT阈值电压的过程如下： 在控制栅极和源极连 接编程电源 VCC,将沟道区域和漏极接地，如图 22所示；编程电源施加 25V 的电源，根据需要调整的悬浮栅极电荷量的多少控制编程时间，如图 23所示； 编程电源施加完毕， 将源极、 漏极、 沟道区域都和编程电源断开。
测试 TFT 阈值电压 （悬浮栅晶体管正常启动所需的电压） ， 判断 TFT 阈值电压是否符合电路正常工作的条件， 不符合则继续按照上述步骤调整。
悬浮栅晶体管的悬浮栅极能够储存一定量的电荷， 控制栅极在正常驱动 电压的基础上需要再加上悬浮栅极的电压才能正常驱动晶体管。 悬浮栅就是 通过这个原理调整了 TFT的阈值电压。 这种方法避免了因 TFT阈值电压不 符， 使得整个电路不能正常工作， 导致成本的大量增加。 悬浮栅晶体管调整 TFT阈值电压可以在最终工艺完成后， 根据 TFT阈值电压测试情况， 对于那 些阈值电压不在正常范围内的 TFT进行悬浮栅电荷的编程，使得其能够重复 利用， 这大大提高了产品的良率。
本发明的实施例还提供一种显示器驱动电路， 包括悬浮栅晶体管， 如图 2所示， 该悬浮栅晶体管包括基板 1 ,设置在基板 1上的悬浮栅极 3、 源极 4、 漏极 5和控制栅极 6, 该悬浮栅晶体管还包括所述基板 1上依次设置的第一 层绝缘薄膜 7、 多晶硅薄膜 8, 在多晶硅薄膜 8中部形成沟道区域 2, 所述沟 道区域 2的位置与所述悬浮栅极 3的位置相对应。
所述沟道区域 2的设置利于在悬浮栅晶体管制作过程中悬浮栅的制作。 这是因为如果采用底栅结构的话， ELA工艺可能会对金属栅极造成破坏。 所述多晶硅薄膜 8上依次设置第二层绝缘薄膜 9和第三层绝缘薄膜 10, 所述第二层绝缘薄膜 9和第三层绝缘薄膜 10之间设有所述悬浮栅极 3。
所述第三层绝缘薄膜 10位于所述悬浮栅极 3的两侧分别设有第一开口和 第二开口， 所述第一开口和第二开口分别向内延伸至所述多晶硅薄膜 8形成 源极过孔 41和漏极过孔 51 , 所述源极过孔 41和所述漏极过孔 51内设有与 多晶硅薄膜 8的源极区和漏极区接触的金属薄膜分别形成源极 4和漏极 5。
所述第三层绝缘薄膜 10上与所述悬浮栅极 3相对应的部位沉积一层金属 薄膜形成控制栅极 6。 控制栅极 6也于沟道区域 2对应。
实际应用中，所述第三层绝缘薄膜 10上沉积一层金属薄膜，所述金属薄 膜同时覆盖所述多晶硅薄膜 8由该第三层绝缘薄膜 10外露的部分，然后经过 光刻曝光在所述第三层绝缘薄膜 10的相应位置形成所述控制栅极 6,在所述 多晶硅薄膜 8的外露的部分分别形成源极 4和漏极 5。
本实施例中， 第一层绝缘薄膜、 第二层绝缘薄膜、 第三层绝缘薄膜均可 以采用 SiOx、 SiNx、 SiOxNy中的一种或几种组合而制成。 （图 2中只显示 出了悬浮栅晶体管部分结构 )
本发明实施例的悬浮栅晶体管可用于代替现有技术中的薄膜晶体管， 该 悬浮栅晶体管的阈值电压可调，避免了因 TFT电压不符而导致整个驱动电路 不能正常工作的情况的发生。
本发明的实施例还提供一种显示器驱动电路制作方法， 包括以下步骤： 在 PCB板上制作显示器驱动电路的各个电子元件，其中悬浮栅晶体管的制作 工艺包括：
在基板上依次形成第一层绝缘薄膜 7和多晶硅薄膜 8;
在所述多晶硅薄膜 8中形成沟道区域 2;
在所述多晶硅薄膜 8上形成第二层绝缘薄膜 9和第三层绝缘薄膜 10, 以 及设置在第二层绝缘薄膜 9和第三层绝缘薄膜 10之间的悬浮栅极 3;
在所述多晶硅薄膜 8中形成源极区域和漏极区域；
在所述第三层绝缘薄膜上形成源极 4、 漏极 5、 控制栅极 6。
在基板上依次形成第一层绝缘薄膜 7和多晶硅薄膜 8的一个示例包括： 在基板 1上依次沉积所述第一层绝缘薄膜 7和第一层非晶硅薄膜 81;进行退 火处理， 使得所述第一层非晶硅薄膜 81形成所述多晶硅薄膜 8。 在所述多晶硅薄膜 8上形成沟道区域的一个示例包括： 在所述多晶硅薄 膜 8表面涂覆第一层光刻胶 11 , 将该第一层光刻胶 11曝光、 显影， 所述多 晶硅薄膜 8中与所述第一层光刻胶 11的未保留区域相对应的区域用于得到沟 道区域； 在所述沟道区域注入硼烷离子或磷烷离子， 使得所述位于所述沟道 区域的所述多晶硅薄膜 8形成 P型多晶硅或 N型多晶硅；采用剥离工艺去除 所述第一层光刻胶 11; 进行退火处理。
在所述多晶硅薄膜 8上形成第二层绝缘薄膜 9和第三层绝缘薄膜 10, 以 及设置在第二层绝缘薄膜 9和第三层绝缘薄膜 10之间的悬浮栅极 3的一个示 例包括：采用气相沉积法在所述多晶硅薄膜 8上依次沉积第二层绝缘薄膜 9、 第二层非晶硅薄膜 12; 在所述第二层非晶硅薄膜 12表面涂覆第二层光刻胶 13, 将该第二层光刻胶 13曝光、 显影， 使得该第二层光刻胶 13的保留区域 与所述沟道区域相对应；采用刻蚀工艺，保留所述第二层非晶硅薄膜 12上与 所述沟道区域相对应的区域， 形成悬浮栅极 3; 剥离所述第二层光刻胶 13; 采用气相沉积法在所述第二层绝缘薄膜 9表面、 所述悬浮栅极 3表面沉积第 三层绝缘薄膜 10。 该第三层绝缘薄膜 10覆盖悬浮栅极 3。
在所述多晶硅薄膜中形成源极区域和漏极区域的一个示例包括： 在所述 第三层绝缘薄膜 10上涂覆第三层光刻胶 14, 将该第三层光刻胶 14曝光、 显 影， 露出与源极区域和漏极区域对应的部分； 对所述第二层绝缘薄膜 9、 所 述第三层绝缘薄膜 10进行刻蚀， 去除所述第二层绝缘薄膜 9、 所述第三层绝 缘薄膜 10上与所述第三层光刻胶 14的未保留区域相对应的区域， 在所述多 晶硅薄膜 8上形成源极区域 82和漏极区域 83。
在所述第三层绝缘薄膜 10上形成控制栅极 6的一个示例包括:在所述源 极区域 82和所述漏极区域 83重掺杂硼烷离子或磷烷离子， 以便所述源极区 域 82和所述漏极区域 83与后续步骤中沉积的金属薄膜接触良好； 剥离所述 第三层光刻胶 14; 采用气相沉积法在所述第二层绝缘薄膜 9、 所述第三层绝 缘薄膜 10的未刻蚀区域以及所述多晶硅薄膜 8上形成源极区域 82和漏极区 域 83沉积一层金属薄膜 15;在所述金属薄膜 15上涂覆第四层光刻胶 16,将 该第四层光刻胶 16曝光、 显影； 对该金属薄膜 15进行刻蚀， 在所述金属薄 膜 15上形成控制栅极 6; 剥离所述第四层光刻胶 16。
本发明的实施例还提供一种显示器驱动电路的应用方法，在实际应用中， 可通过调整显示器驱动电路中的悬浮栅晶体管的阈值电压来进行校准， 使得 显示器驱动电路可正常工作， 其中， 悬浮栅晶体管阈值电压调整过程包括： 将控制栅极和源极连接具有预设电压的电源， 沟道区域和漏极接地； 经过一 预设时间后断开电源， 所述悬浮栅极上累积预定数量的负电荷， 所述悬浮栅 晶体管的阈值电压达到设定数值。
利用悬浮栅上是否储存有电荷或储存电荷的多少来改变晶体管的阈值电 压， 经过预设时间， 悬浮栅极可以存储足够的电荷。
本实施例中所述预设电压为 25V,但本发明并不限于此，根据具体结构、 材料可以采用其他适当的电压。
测试薄膜晶体管的电压，在所述薄膜晶体管的电压超过预设调整电压时， 将控制栅极和源极接地， 沟道区域和漏极连接具有所述预设电压的电源； 当 所述薄膜晶体管的电压小于预设调整电压时， 返回步骤将控制栅极和源极连 接具有预设电压的电源， 多晶硅薄膜的沟道区域和漏极接地。
当所述薄膜晶体管的电压超过预设调整电压时， 还可以通过紫外线照射 的方式进行电压释放。
在一具体实施例中， 调整 TFT阈值电压的过程如下： 在控制栅极和源极 连接编程电源 VCC,沟道区域和漏极接地，如图 22所示；编程电源施加 25V 的电源，根据需要调整的悬浮栅极电荷量的多少控制编程时间，如图 23所示； 编程电源施加完毕， 源极， 漏极， 沟道区域极都和编程电源断开。
测试 TFT阈值电压， 判断 TFT阈值电压是否符合电路正常工作的条件， 不符合则继续按照上述步骤调整。
悬浮栅晶体管的悬浮栅极能够储存一定量的电荷， 控制栅极在正常驱动 电压的基础上需要再加上悬浮栅极的电压才能正常驱动晶体管。 悬浮栅就是 通过这个原理调整了 TFT的阈值电压。 这种方法避免了因 TFT阈值电压不 符， 使得整个电路不能正常工作， 导致成本的大量增加。 悬浮栅晶体管调整 TFT阈值电压可以在最终工艺完成后， 根据 TFT阈值电压测试情况， 对于那 些阈值电压不在正常范围内的 TFT进行悬浮栅电荷的编程，使得能够重复利 用， 大大提高了产品的良率。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1. 一种悬浮栅晶体管， 包括基板， 设置在基板上的悬浮栅极、 源极、 漏 极和控制栅极， 还包括：
所述基板上依次设置的第一层绝缘薄膜、 多晶硅薄膜， 所述多晶硅薄膜 中形成有沟道区域， 所述沟道区域的位置与所述悬浮栅极的位置相对应。
2.根据权利要求 1所述的悬浮栅晶体管， 其中， 所述多晶硅薄膜上依次 设置第二层绝缘薄膜和第三层绝缘薄膜， 所述第二层绝缘薄膜和第三层绝缘 薄膜之间设有所述悬浮栅极。
3.根据权利要求 2所述的悬浮栅晶体管， 其中， 所述第三层绝缘薄膜中 位于所述悬浮栅极的两侧分别设有第一开口和第二开口， 所述第一开口和第 二开口分别延伸至所述多晶硅薄膜形成源极过孔和漏极过孔， 所述源极过孔 和所述漏极过孔内设有分别形成源极和漏极的金属薄膜。
4.根据权利要求 3所述的悬浮栅晶体管， 其中， 所述第三层绝缘薄膜上 与所述悬浮栅极相对应的部位设置一层金属薄膜形成所述控制栅极。
5.根据权利要求 3所述的悬浮栅晶体管， 其中， 所述第一层绝缘薄膜、 第二层绝缘薄膜、 第三层绝缘薄膜采用 SiOx、 SiNx、 SiOxNy中的一种或两 种制作。
6.一种显示器驱动电路，包括权利要求 1-5任一项所述的悬浮栅晶体管。
7.一种悬浮栅晶体管制作方法， 包括以下步骤：
在基板上依次形成第一层绝缘薄膜和多晶硅薄膜；
在所述多晶硅薄膜中形成沟道区域；
在所述多晶硅薄膜上形成第二层绝缘薄膜和第三层绝缘薄膜， 以及设置 在第二层绝缘薄膜和第三层绝缘薄膜之间的悬浮栅极；
在所述多晶硅薄膜中形成源极区域和漏极区域；
在所述第三层绝缘薄膜上形成源极、 漏极、 控制栅极。
8.根据权利要求 7所述的悬浮栅晶体管制作方法， 其中， 在基板上依次 形成第一层绝缘薄膜和多晶硅薄膜， 包括：
在基板上依次沉积所述第一层绝缘薄膜和非晶硅薄膜；
进行退火处理， 使得所述非晶硅薄膜形成所述多晶硅薄膜。
9.根据权利要求 7或 8所述的悬浮栅晶体管制作方法， 其中， 在所述多 晶硅薄膜中形成沟道区域， 包括：
在所述多晶硅薄膜表面涂覆第一层光刻胶， 将该第一层光刻胶曝光、 显 影， 所述多晶硅薄膜上与所述第一层光刻胶的未保留区域相对应的区域用于 形成所述沟道区域；
在所述沟道区域注入硼烷离子或磷烷离子， 使得所述位于所述沟道区域 的所述多晶硅薄膜形成 P型多晶硅或 N型多晶硅；
采用剥离工艺去除所述第一层光刻胶；
进行退火处理。
10.根据权利要求 7所述的悬浮栅晶体管制作方法， 其中， 在所述多晶 硅薄膜上形成第二层绝缘薄膜和第三层绝缘薄膜， 以及设置在第二层绝缘薄 膜和第三层绝缘薄膜之间的悬浮栅极包括：
采用气相沉积法在所述多晶硅薄膜上依次沉积第二层绝缘薄膜、 第二层 非晶硅薄膜；
在所述第二层非晶硅薄膜表面涂覆第二层光刻胶， 将该第二层光刻胶曝 光、 显影， 使得该第二层光刻胶的保留区域与所述沟道区域相对应；
采用刻蚀工艺， 保留所述第二层非晶硅薄膜上与所述沟道区域相对应的 区域， 形成悬浮栅极；
剥离所述第二层光刻胶；
采用气相沉积法在所述第二层绝缘薄膜表面、 所述悬浮栅极表面沉积第 三层绝缘薄膜。
11.根据权利要求 7或 10所述的悬浮栅晶体管制作方法， 其中， 在所述 多晶硅薄膜中形成源极区域和漏极区域包括：
在所述第三层绝缘薄膜上涂覆第三层光刻胶， 将该第三层光刻胶曝光、 显影；
对所述第二层绝缘薄膜、 所述第三层绝缘薄膜进行刻蚀， 去除所述第二 层绝缘薄膜、 所述第三层绝缘薄膜上与所述第三层光刻胶的未保留区域相对 应的区域， 露出所述多晶硅薄膜中形成源极区域和漏极区域的部分。
12.根据权利要求 11所述的悬浮栅晶体管制作方法， 其中， 在所述第三 层绝缘薄膜上形成控制栅极包括： 在所述源极区域和所述漏极区域重掺杂硼烷离子或磷烷离子， 形成导电 层；
剥离所述第三层光刻胶；
采用气相沉积法在所述第二层绝缘薄膜、 所述第三层绝缘薄膜的未刻蚀 区域以及所述多晶硅薄膜中形成的源极区域和漏极区域上沉积一层金属薄 膜；
在所述金属薄膜上沉积第四层光刻胶， 将该第四层光刻胶曝光、 显影； 进行刻蚀， 在所述金属薄膜上形成控制栅极；
剥离所述第四层光刻胶。
13. 一种采用权利要求 1-5任一项所述的悬浮栅晶体管的应用方法， 包 括以下步骤：
将控制栅极和源极连接具有预设电压的电源， 将多晶硅薄膜的沟道区域 和漏极接地；
经过一预设时间后断开电源， 所述悬浮栅极上累积预定数量的负电荷， 所述悬浮栅晶体管的阈值电压达到设定数值。
14.根据权利要求 13所述的悬浮栅晶体管的应用方法， 包括：
测试薄膜晶体管的电压，在所述薄膜晶体管的电压超过预设调整电压时， 将控制栅极和源极接地， 沟道区域和漏极连接具有所述预设电压的电源； 当 所述薄膜晶体管的电压小于预设调整电压时， 返回步骤将控制栅极和源极连 接具有预设电压的电源， 将多晶硅薄膜的沟道区域和漏极接地。
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