US20160020228A1 - Cmos transistor and method for fabricating the same, display panel and display device - Google Patents

Cmos transistor and method for fabricating the same, display panel and display device Download PDF

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US20160020228A1
US20160020228A1 US14/422,365 US201414422365A US2016020228A1 US 20160020228 A1 US20160020228 A1 US 20160020228A1 US 201414422365 A US201414422365 A US 201414422365A US 2016020228 A1 US2016020228 A1 US 2016020228A1
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active layer
layer
electrode
dopant ions
cmos transistor
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Chunsheng Jiang
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BOE Technology Group Co Ltd
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/22—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material

Definitions

  • the present invention relates to the field of touch panel technology, and particularly to a CMOS transistor and a method for fabricating the same, a display panel and a display device.
  • CMOS Complementary metal oxide semiconductor
  • PMOS positive channel metal oxide semiconductor
  • NMOS negative channel metal oxide semiconductor
  • CMOS has a characteristic of low power consumption and is widely used in integrated circuits.
  • a bottom gate type thin film transistor formed by six mask patterning processes in the prior art comprises a switching thin film transistor and a driving thin film transistor formed simultaneously on a base substrate, the switching thin film transistor comprises a gate electrode, a gate insulation layer, an active layer, an etch stop layer, source and drain electrodes, a passivation layer, a first channel and a pixel electrode, and the driving thin film transistor comprises a gate electrode, a passivation layer, a second channel and a pixel electrode, so that a jump layer connection between the switching thin film transistor and the driving thin film transistor is implemented, but such a structure may increase power consumption when applied to a display panel.
  • the present invention provides a CMOS transistor and a method for fabricating the same, a display panel and a display device, which may reduce the power consumption of the display panel.
  • the present invention provides a CMOS transistor comprising a first region and a second region provided on a base substrate, the first region comprises a first gate electrode, a first active layer, a first source electrode and a first drain electrode, and the second region comprises a second gate electrode, a second active layer, a second source electrode and a second drain electrode, first dopant ions are formed in the first active layer, second dopant ions are formed in the second active layer, a concentration of the first dopant ions is smaller than that of the second dopant ions, the first active layer is an n-type active layer, and the second active layer is a p-type active layer.
  • an etch stop layer is further formed between the first active layer and the first source electrode and the first drain electrode and between the second active layer and the second source electrode and the second drain electrode.
  • the first active layer is oxide material layer
  • the second active layer is oxide material layer
  • the oxide material is zinc oxide.
  • a first via hole, a second via hole, a third via hole and a fourth via hole are formed in the etch stop layer, the first source electrode and the first drain electrode are connected with the first active layer through the first via hole and the second via hole, respectively, and the second source electrode and the second drain electrode are connected with the second active layer through the third via hole and the fourth via hole, respectively.
  • the first dopant ions and the second dopant ions are both N ions.
  • the present invention provides a display panel, comprising the above CMOS transistor.
  • the present invention provides a display device, comprising the above display panel.
  • the present invention provides a method for fabricating a CMOS transistor, comprising steps of: forming a first gate electrode, a second gate electrode, a first active layer, a second active layer, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode on a base substrate; and injecting first dopant ions into the first active layer and injecting second dopant ions into the second active layer by a doping process, a concentration of the first dopant ions is smaller than that of the second dopant ions, the first active layer is an n-type active layer, and the second active layer is a p-type active layer.
  • the step of forming a first gate electrode, a second gate electrode, a first active layer, a second active layer, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode on a base substrate comprises: forming the first gate electrode and the second gate electrode on the base substrate by a patterning process; forming the first active layer and the second active layer on the base substrate on which the first gate electrode and the second gate electrode are formed; and forming the first source electrode, the second source electrode, the first drain electrode and the second drain electrode on the first active layer and the second active layer by a patterning process.
  • a planarization layer is formed on the first source electrode, the second source electrode, the first drain electrode and the second drain electrode before injecting the dopant ions;
  • the step of injecting first dopant ions into the first active layer and injecting second dopant ions into the second active layer by a doping process comprises: forming a photoresist layer on the planarization layer, the photoresist layer comprising a first photoresist region and a second photoresist region, the first photoresist region corresponding to the first active layer, and the second photoresist region corresponding to the second active layer; performing the doping process on the first active layer through the first photoresist region to inject N ions into the first active layer; performing the doping process on the second active layer through the second photoresist region to inject N ions into the second active layer; and removing the photoresist layer.
  • the step of forming the photoresist layer on the planarization layer comprises: applying photoresist on the planarization layer; and performing mask plate masking and exposure by using a half tone mask and performing development to form the first photoresist region and the second photoresist region.
  • a thickness of the first photoresist region is larger than that of the second photoresist region.
  • the thickness of the photoresist layer is equal to or larger than 3 ⁇ m
  • the thickness of the first photoresist region is ranged from 1.7 ⁇ m to 2.3 ⁇ m
  • the thickness of the second photoresist region is ranged from 0.7 ⁇ m to 1.3 ⁇ m.
  • the first active layer and the second active layer are made of oxide material.
  • the oxide material is zinc oxide.
  • an etch stop layer is formed on the first active layer and the second active layer by a patterning process, and a first via hole, a second via hole, a third via hole and a fourth via hole are formed in the etch stop layer, so that the first source electrode and the first drain electrode are connected with the first active layer through the first via hole and the second via hole, respectively, and the second source electrode and the second drain electrode are connected with the second active layer through the third via hole and the fourth via hole, respectively.
  • the first dopant ions and the second dopant ions are both N ions.
  • the concentration of the first dopant ions is smaller than that of the second dopant ions, and the first active layer is an n-type active layer and the second active layer is a p-type active layer, which may reduce the power consumption of the display panel.
  • FIG. 1 is a schematic diagram of a structure of a CMOS transistor according to a first embodiment of the present invention
  • FIG. 2 is a flow chart of a method for fabricating a CMOS transistor, according to a second embodiment of the present invention
  • FIG. 3 a is a schematic diagram illustrating forming a first gate electrode, a second gate electrode, a first active layer, a second active layer and a gate insulation layer in the method for fabricating the CMOS transistor;
  • FIG. 3 b is a schematic diagram illustrating forming a first source electrode, a first drain electrode, a second source electrode and a second drain electrode in the method for fabricating the CMOS transistor;
  • FIG. 3 c is a schematic diagram illustrating forming a photoresist layer in the method for fabricating the CMOS transistor
  • FIG. 3 d is a schematic diagram illustrating ion implantation in the method for fabricating the CMOS transistor
  • FIG. 3 e is a schematic diagram illustrating removing the photoresist layer in the method for fabricating the CMOS transistor.
  • FIG. 1 is a schematic diagram of a structure of a CMOS transistor according to a first embodiment of the present invention.
  • the CMOS transistor comprises a first region and second region provided on a base substrate 1 , the first region comprises a first gate electrode 31 , a first active layer 41 , a first source electrode 61 and a first drain electrode 71 provided on the base substrate 1 , and the second region comprises a second gate electrode 32 , a second active layer 42 , a second source electrode 62 and a second drain electrode 72 provided on the base substrate 1 .
  • first dopant ions are formed in the first active layer 41
  • second dopant ions are formed in the second active layer 42
  • a concentration of the first dopant ions is smaller than that of the second dopant ions.
  • both of the first dopant ions and the second dopant ions are N ions.
  • the first active layer 41 is an n-type active layer
  • the second active layer 42 is a p-type active layer
  • the first region is a NMOS region
  • the second region is a PMOS region.
  • the transistor according to the embodiment of the present invention can reduce power consumption of a display panel.
  • an etch stop layer 5 is formed between the first active layer 41 and the first source and drain electrodes 61 , 71 and between the second active layer 42 and the second source and drain electrodes 62 , 72 .
  • the first active layer 41 is an oxide material layer
  • the second active layer 42 is an oxide material layer.
  • the oxide material is zinc oxide. Since the first active layer 41 and the second active layer 42 are both oxide material layer and the oxide material has a disadvantage of corrosion intolerance, the etch stop layer 5 is formed on the first and second active layers 41 , 42 for protection.
  • the active layer oxide material layer
  • the etch stop layer is required to be formed on the active layer firstly and then the source and drain electrodes are fabricated.
  • a gate insulation layer 2 is formed between the first gate electrode 31 and the first active layer 41 and between the second gate electrode 32 and the second active layer 42 , and the first gate electrode 31 and the second gate electrode 32 are formed on the base substrate 1 .
  • a first via hole, a second via hole, a third via hole and a fourth via hole are formed in the etch stop layer 5 .
  • a position of the first via hole corresponds to the first source electrode 61 and the first active layer 41
  • a position of the second via hole corresponds to the first drain electrode 71 and the first active layer 41
  • a position of the third via hole corresponds to the second source electrode 62 and the second active layer 42
  • a position of the fourth via hole corresponds to the second drain electrode 72 and the second active layer 42 , so that the first source and drain electrodes 61 , 71 are connected with the first active layer 41 through the first and second via holes, respectively, and the second source and drain electrodes 62 , 72 are connected with the second active layer 42 through the third and fourth via holes, respectively.
  • the first via hole, the second via hole, the third via hole and the fourth via hole are formed in the etch stop layer 5 by a dry etching or other method, and then the first source electrode 61 , the second source electrode 62 , the first drain electrode 71 and the second drain electrode 72 are formed on the etch stop layer 5 by a patterning process.
  • the structure of CMOS transistor includes a bottom gate type structure and a top gate type structure.
  • the bottom gate type structure comprises a NMOS region 10 and a PMOS region 11
  • the NMOS region 10 comprises the first gate electrode 31 , the gate insulation layer 2 , the first active layer 41 , the etch stop layer 5 , the first source electrode 61 and the first drain electrode 71 sequentially provided from a side of the base substrate 1 for providing the CMOS transistor
  • the PMOS region 11 comprises the second gate electrode 32 , the gate insulation layer 2 , the second active layer 42 , the etch stop layer 5 , the second source electrode 62 and the second drain electrode 72 sequentially provided from the side of the base substrate 1 .
  • the top gate type structure comprises a NMOS region 10 and a PMOS region 11
  • the NMOS region 10 comprises the first active layer 41 , the etch stop layer 5 , the first source electrode 61 and the first drain electrode 71 , the gate insulation layer 2 and the first gate electrode 31 sequentially provided from a side of the base substrate 1 for providing the CMOS transistor
  • the PMOS region 11 comprises the second active layer 42 , the etch stop layer 5 , the second source electrode 62 and the second drain electrode 72 , the gate insulation layer 2 and the second gate electrode 32 sequentially provided from the side of the base substrate 1 .
  • the CMOS transistor in the embodiment of the present invention is described by taking the bottom gate type thin film transistor (i.e., the gate electrode is provided below the pattern of active layer) as an example, and it is merely an exemplary description, the scope of the present invention is not limited thereto.
  • the structure of the CMOS transistor may be varied according to a requirement in practical application, for example, the CMOS transistor in the technical solution of the present invention may also utilize the top gate type thin film transistor (i.e., the gate electrode is provided above the active layer).
  • the gate insulation layer 2 is formed between the first gate electrode 31 and the first source and drain electrodes 61 , 71 and between the second gate electrode 32 and the second source and drain electrodes 62 , 72 , and the first gate electrode 31 and the second gate electrode 32 are both formed above the gate insulation layer 2 .
  • FIG. 2 is a flow chart of a method for fabricating a CMOS transistor, according to a second embodiment of the present invention. As shown in FIG. 2 , the method comprises the following steps.
  • step S 11 a first gate electrode, a second gate electrode, a first active layer, a second active layer, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode are formed on a base substrate.
  • step S 11 may comprise the following steps.
  • step S 111 the first gate electrode and the second gate electrode are formed on the base substrate by a patterning process.
  • step S 112 the first active layer and the second active layer are formed on the base substrate on which the first gate electrode and the second gate electrode are formed, by a patterning process.
  • the method further comprises forming a gate insulation layer on the first gate electrode and the second electrode. After the gate insulation layer is formed, the first active layer and the second active layer are respectively formed on the regions of the gate insulation layer corresponding to the first gate electrode and the second gate electrode by a patterning process.
  • FIG. 3 a is a schematic diagram illustrating forming a first gate electrode 31 , a second gate electrode 32 , a first active layer 41 , a second active layer 42 and a gate insulation layer 2 in the method for fabricating the CMOS transistor. As shown in FIG.
  • a gate metal material layer is deposited on two regions (a first region and a second region) on a base substrate 1 , and the first gate electrode 31 and the second gate electrode 32 are formed by a patterning process, respectively; the gate insulation layer 2 is deposited on the first gate electrode 31 and the second gate electrode 32 ; an active metal oxide material layer is deposited on the regions of the gate insulation layer 2 corresponding to the first gate electrode 31 and the second gate electrode 32 , the active metal oxide material is preferably zinc oxide, and the first active layer 41 and the second active layer 42 are formed by a patterning process, respectively.
  • step S 113 the first source electrode, the second source electrode, the first drain electrode and the second drain electrode are formed on the first active layer and the second active layer by a patterning process.
  • FIG. 3 b is a schematic diagram illustrating forming the first source electrode 61 , the first drain electrode 71 , the second source electrode 62 and the second drain electrode 72 in the method for fabricating the CMOS transistor.
  • a source and drain metal material layer is deposited on the first active layer 41 and the second active layer 42 , and the first source electrode 61 , the first drain electrode 71 , the second source electrode 62 and the second drain electrode 72 are formed by a patterning process, respectively.
  • the patterning process may at least include photoresist coating, mask plate masking, exposure, development and photoresist stripping.
  • the method further comprises forming an etch stop layer on the first active layer and the second active layer by a patterning process.
  • the first source electrode, the second source electrode, the first drain electrode and the second drain electrode are formed on the etch stop layer by a patterning process.
  • step S 12 first dopant ions are injected into the first active layer and second dopant ions are injected into the second active layer, by a doping process, a concentration of the first dopant ions is smaller than that of the second dopant ions.
  • the first active layer 41 and the second active layer 42 are both zinc oxide material layer.
  • the first dopant ions and the second dopant ions are both N ions.
  • does and energy of ion implantation for the first active layer 41 and the second active layer 42 are respectively controlled according to concentrations of zinc oxide in the first active layer 41 and the second active layer 42 , so as to obtain the first dopant ions and the second dopant ions with different concentrations of dopant ions and allow the concentration of the first dopant ions to be smaller than that of the second dopant ions.
  • the first active layer 41 is an N type active layer
  • the second active layer 42 is a P type active layer.
  • the method further comprises forming a planarization layer 8 on the first source electrode 61 , the second source electrode 62 , the first drain electrode 71 and the second drain electrode 72 , as shown in FIG. 3 b.
  • step S 12 may comprise the following steps.
  • a photoresist layer is formed on the planarization layer 8 , the photoresist layer includes a first photoresist region and a second photoresist region, the first photoresist region corresponds to the first active layer, and the second photoresist region corresponds to the second active layer.
  • FIG. 3 c is a schematic diagram illustrating forming a photoresist layer in the method for fabricating the CMOS transistor.
  • forming the photoresist layer on the planarization layer 8 comprises: applying a photoresist layer on the planarization layer 8 , a thickness of the photoresist layer being equal to or larger than 3 ⁇ m; and performing mask plate masking and exposure on the photoresist layer by using a half tone mask plate and performing development to form the first photoresist region 91 and the second photoresist region 92 .
  • the thickness of the first photoresist region 91 is larger than that of the second photoresist region 92 , preferably, the thickness of the first photoresist region is ranged from 1.7 ⁇ m to 2.3 ⁇ m, and the thickness of the second photoresist region is ranged from 0.7 ⁇ m to 1.3 ⁇ m.
  • step S 122 the doping process is performed on the first active layer through the first photoresist region, so that the N ions are injected into the first active layer.
  • step S 123 the doping process is performed on the second active layer through the second photoresist region, so that the N ions are injected into the second active layer.
  • FIG. 3 d is a schematic diagram illustrating ion implantation in the method for fabricating the CMOS transistor.
  • the first photoresist region 91 corresponds to the first active layer 41
  • the second photoresist layer 92 corresponds to the second active layer 42 .
  • the first photoresist region 91 and the second photoresist region 92 may block N ion injection to reduce the injection concentration of N ion.
  • the thickness of the first photoresist region 91 is larger than that of the second photoresist region 92 , so that the concentration of N ions injected into the first active layer 41 through the first photoresist region 91 is smaller than that of N ions injected into the second active layer 42 through the second photoresist region 92 .
  • step S 124 the photoresist layer is removed.
  • FIG. 3 e is a schematic diagram illustrating removing the photoresist layer in the method for fabricating the CMOS transistor. As shown in FIG. 3 e , the remaining photoresist layer is removed to result in the CMOS transistor.
  • the first active layer 41 and the second active layer 42 are both made of oxide material.
  • the oxide material is zinc oxide.
  • the method further comprises forming a first via hole, a second via hole, a third via hole and a fourth via hole in the etch stop layer by a patterning process, a position of the first via hole corresponds to the first source electrode and the first active layer, a position of the second via hole corresponds to the first drain electrode and the first active layer, a position of the third via hole corresponds to the second source electrode and the second active layer, and a position of the fourth via hole corresponds to the second drain electrode and the second active layer, so that the first source electrode and the first drain electrode are connected with the first active layer through the first via hole and second via hole, respectively, and the second source electrode and the second drain electrode are connected with the second active layer through the third via hole and fourth via hole, respectively.
  • a third embodiment of the present invention provides a display panel that comprises CMOS transistors.
  • CMOS transistor in this embodiment utilizes the CMOS transistor in the first embodiment, and the specific implementation thereof refers to the first embodiment and will not be described in detail herein.
  • a fourth embodiment of the present invention provides a display device that comprises a display panel, and the display panel comprises CMOS transistors.
  • the display device in this embodiment utilizes the CMOS transistor in the first embodiment, and the specific implementation thereof refers to the first embodiment and will not be described in detail herein.

Abstract

The present invention provides a CMOS transistor and a method for fabricating the same, a display panel and a display device. The CMOS transistor comprises a first region and a second region provided on a base substrate, the first region comprises a first gate electrode, a first active layer, a first source electrode and a first drain electrode, and the second region comprises a second gate electrode, a second active layer, a second source electrode and a second drain electrode, first dopant ions are formed in the first active layer, second dopant ions are formed in the second active layer, a concentration of the first dopant ions is smaller than that of the second dopant ions, the first active layer is an n-type active layer, and the second active layer is a p-type active layer. The technical solution of the present invention can reduce power consumption of display panel.

Description

    FIELD OF THE INVENTION
  • The present invention relates to the field of touch panel technology, and particularly to a CMOS transistor and a method for fabricating the same, a display panel and a display device.
    • BACKGROUND OF THE INVENTION
  • Complementary metal oxide semiconductor (referred to as CMOS) consists of positive channel metal oxide semiconductor (referred to as PMOS) and negative channel metal oxide semiconductor (referred to as NMOS). CMOS has a characteristic of low power consumption and is widely used in integrated circuits.
  • A bottom gate type thin film transistor formed by six mask patterning processes in the prior art comprises a switching thin film transistor and a driving thin film transistor formed simultaneously on a base substrate, the switching thin film transistor comprises a gate electrode, a gate insulation layer, an active layer, an etch stop layer, source and drain electrodes, a passivation layer, a first channel and a pixel electrode, and the driving thin film transistor comprises a gate electrode, a passivation layer, a second channel and a pixel electrode, so that a jump layer connection between the switching thin film transistor and the driving thin film transistor is implemented, but such a structure may increase power consumption when applied to a display panel.
    • SUMMARY OF THE INVENTION
  • The present invention provides a CMOS transistor and a method for fabricating the same, a display panel and a display device, which may reduce the power consumption of the display panel.
  • To achieve the above objective, the present invention provides a CMOS transistor comprising a first region and a second region provided on a base substrate, the first region comprises a first gate electrode, a first active layer, a first source electrode and a first drain electrode, and the second region comprises a second gate electrode, a second active layer, a second source electrode and a second drain electrode, first dopant ions are formed in the first active layer, second dopant ions are formed in the second active layer, a concentration of the first dopant ions is smaller than that of the second dopant ions, the first active layer is an n-type active layer, and the second active layer is a p-type active layer.
  • Optionally, an etch stop layer is further formed between the first active layer and the first source electrode and the first drain electrode and between the second active layer and the second source electrode and the second drain electrode.
  • Optionally, the first active layer is oxide material layer, and the second active layer is oxide material layer.
  • Optionally, the oxide material is zinc oxide.
  • Optionally, a first via hole, a second via hole, a third via hole and a fourth via hole are formed in the etch stop layer, the first source electrode and the first drain electrode are connected with the first active layer through the first via hole and the second via hole, respectively, and the second source electrode and the second drain electrode are connected with the second active layer through the third via hole and the fourth via hole, respectively.
  • Optionally, the first dopant ions and the second dopant ions are both N ions.
  • To achieve the above objective, the present invention provides a display panel, comprising the above CMOS transistor.
  • To achieve the above objective, the present invention provides a display device, comprising the above display panel. To achieve the above objective, the present invention provides a method for fabricating a CMOS transistor, comprising steps of: forming a first gate electrode, a second gate electrode, a first active layer, a second active layer, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode on a base substrate; and injecting first dopant ions into the first active layer and injecting second dopant ions into the second active layer by a doping process, a concentration of the first dopant ions is smaller than that of the second dopant ions, the first active layer is an n-type active layer, and the second active layer is a p-type active layer.
  • Optionally, the step of forming a first gate electrode, a second gate electrode, a first active layer, a second active layer, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode on a base substrate comprises: forming the first gate electrode and the second gate electrode on the base substrate by a patterning process; forming the first active layer and the second active layer on the base substrate on which the first gate electrode and the second gate electrode are formed; and forming the first source electrode, the second source electrode, the first drain electrode and the second drain electrode on the first active layer and the second active layer by a patterning process.
  • Optionally, a planarization layer is formed on the first source electrode, the second source electrode, the first drain electrode and the second drain electrode before injecting the dopant ions; the step of injecting first dopant ions into the first active layer and injecting second dopant ions into the second active layer by a doping process comprises: forming a photoresist layer on the planarization layer, the photoresist layer comprising a first photoresist region and a second photoresist region, the first photoresist region corresponding to the first active layer, and the second photoresist region corresponding to the second active layer; performing the doping process on the first active layer through the first photoresist region to inject N ions into the first active layer; performing the doping process on the second active layer through the second photoresist region to inject N ions into the second active layer; and removing the photoresist layer.
  • Optionally, the step of forming the photoresist layer on the planarization layer comprises: applying photoresist on the planarization layer; and performing mask plate masking and exposure by using a half tone mask and performing development to form the first photoresist region and the second photoresist region.
  • Optionally, a thickness of the first photoresist region is larger than that of the second photoresist region.
  • Optionally, the thickness of the photoresist layer is equal to or larger than 3 μm, the thickness of the first photoresist region is ranged from 1.7 μm to 2.3 μm, and the thickness of the second photoresist region is ranged from 0.7 μm to 1.3 μm.
  • Optionally, the first active layer and the second active layer are made of oxide material.
  • Optionally, the oxide material is zinc oxide.
  • Optionally, before forming the first source electrode, the second source electrode, the first drain electrode and the second drain electrode, an etch stop layer is formed on the first active layer and the second active layer by a patterning process, and a first via hole, a second via hole, a third via hole and a fourth via hole are formed in the etch stop layer, so that the first source electrode and the first drain electrode are connected with the first active layer through the first via hole and the second via hole, respectively, and the second source electrode and the second drain electrode are connected with the second active layer through the third via hole and the fourth via hole, respectively.
  • Optionally, the first dopant ions and the second dopant ions are both N ions.
  • In the CMOS transistor and the method for fabricating the same, the display panel and the display device, the concentration of the first dopant ions is smaller than that of the second dopant ions, and the first active layer is an n-type active layer and the second active layer is a p-type active layer, which may reduce the power consumption of the display panel.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic diagram of a structure of a CMOS transistor according to a first embodiment of the present invention;
  • FIG. 2 is a flow chart of a method for fabricating a CMOS transistor, according to a second embodiment of the present invention;
  • FIG. 3 a is a schematic diagram illustrating forming a first gate electrode, a second gate electrode, a first active layer, a second active layer and a gate insulation layer in the method for fabricating the CMOS transistor;
  • FIG. 3 b is a schematic diagram illustrating forming a first source electrode, a first drain electrode, a second source electrode and a second drain electrode in the method for fabricating the CMOS transistor;
  • FIG. 3 c is a schematic diagram illustrating forming a photoresist layer in the method for fabricating the CMOS transistor;
  • FIG. 3 d is a schematic diagram illustrating ion implantation in the method for fabricating the CMOS transistor;
  • FIG. 3 e is a schematic diagram illustrating removing the photoresist layer in the method for fabricating the CMOS transistor.
    •  DESCRIPTION OF THE PREFERRED EMBODIMENT
  • To make those skilled in the art better understand the technical solutions of the present invention, the CMOS transistor and the method for fabricating the same, the display panel and the display device provided by the present invention will be described as below in details in conjunction with the accompanying drawings.
  • FIG. 1 is a schematic diagram of a structure of a CMOS transistor according to a first embodiment of the present invention. As shown in FIG. 1, the CMOS transistor comprises a first region and second region provided on a base substrate 1, the first region comprises a first gate electrode 31, a first active layer 41, a first source electrode 61 and a first drain electrode 71 provided on the base substrate 1, and the second region comprises a second gate electrode 32, a second active layer 42, a second source electrode 62 and a second drain electrode 72 provided on the base substrate 1. In the transistor, first dopant ions are formed in the first active layer 41, second dopant ions are formed in the second active layer 42, and a concentration of the first dopant ions is smaller than that of the second dopant ions. For example, both of the first dopant ions and the second dopant ions are N ions. In the transistor, the first active layer 41 is an n-type active layer, the second active layer 42 is a p-type active layer, the first region is a NMOS region, and the second region is a PMOS region. The transistor according to the embodiment of the present invention can reduce power consumption of a display panel.
  • Preferably, an etch stop layer 5 is formed between the first active layer 41 and the first source and drain electrodes 61, 71 and between the second active layer 42 and the second source and drain electrodes 62, 72. The first active layer 41 is an oxide material layer, and the second active layer 42 is an oxide material layer. Further, the oxide material is zinc oxide. Since the first active layer 41 and the second active layer 42 are both oxide material layer and the oxide material has a disadvantage of corrosion intolerance, the etch stop layer 5 is formed on the first and second active layers 41, 42 for protection. In addition, in practical application, since the active layer (oxide material layer) is likely to be damaged during etching the source and drain electrodes, the etch stop layer is required to be formed on the active layer firstly and then the source and drain electrodes are fabricated.
  • Preferably, a gate insulation layer 2 is formed between the first gate electrode 31 and the first active layer 41 and between the second gate electrode 32 and the second active layer 42, and the first gate electrode 31 and the second gate electrode 32 are formed on the base substrate 1.
  • Preferably, a first via hole, a second via hole, a third via hole and a fourth via hole are formed in the etch stop layer 5. A position of the first via hole corresponds to the first source electrode 61 and the first active layer 41, a position of the second via hole corresponds to the first drain electrode 71 and the first active layer 41, a position of the third via hole corresponds to the second source electrode 62 and the second active layer 42, and a position of the fourth via hole corresponds to the second drain electrode 72 and the second active layer 42, so that the first source and drain electrodes 61, 71 are connected with the first active layer 41 through the first and second via holes, respectively, and the second source and drain electrodes 62, 72 are connected with the second active layer 42 through the third and fourth via holes, respectively. After the etch stop layer 5 is fabricated on the first active layer 41 and the second active layer 42, the first via hole, the second via hole, the third via hole and the fourth via hole are formed in the etch stop layer 5 by a dry etching or other method, and then the first source electrode 61, the second source electrode 62, the first drain electrode 71 and the second drain electrode 72 are formed on the etch stop layer 5 by a patterning process.
  • In the embodiment, the structure of CMOS transistor includes a bottom gate type structure and a top gate type structure. The bottom gate type structure comprises a NMOS region 10 and a PMOS region 11, the NMOS region 10 comprises the first gate electrode 31, the gate insulation layer 2, the first active layer 41, the etch stop layer 5, the first source electrode 61 and the first drain electrode 71 sequentially provided from a side of the base substrate 1 for providing the CMOS transistor, and the PMOS region 11 comprises the second gate electrode 32, the gate insulation layer 2, the second active layer 42, the etch stop layer 5, the second source electrode 62 and the second drain electrode 72 sequentially provided from the side of the base substrate 1. The top gate type structure comprises a NMOS region 10 and a PMOS region 11, the NMOS region 10 comprises the first active layer 41, the etch stop layer 5, the first source electrode 61 and the first drain electrode 71, the gate insulation layer 2 and the first gate electrode 31 sequentially provided from a side of the base substrate 1 for providing the CMOS transistor, and the PMOS region 11 comprises the second active layer 42, the etch stop layer 5, the second source electrode 62 and the second drain electrode 72, the gate insulation layer 2 and the second gate electrode 32 sequentially provided from the side of the base substrate 1.
  • It should be noted that, the CMOS transistor in the embodiment of the present invention is described by taking the bottom gate type thin film transistor (i.e., the gate electrode is provided below the pattern of active layer) as an example, and it is merely an exemplary description, the scope of the present invention is not limited thereto. The structure of the CMOS transistor may be varied according to a requirement in practical application, for example, the CMOS transistor in the technical solution of the present invention may also utilize the top gate type thin film transistor (i.e., the gate electrode is provided above the active layer). In the case where the CMOS transistor in the technical solution of the present invention is the top gate type thin film transistor, the gate insulation layer 2 is formed between the first gate electrode 31 and the first source and drain electrodes 61, 71 and between the second gate electrode 32 and the second source and drain electrodes 62, 72, and the first gate electrode 31 and the second gate electrode 32 are both formed above the gate insulation layer 2.
  • FIG. 2 is a flow chart of a method for fabricating a CMOS transistor, according to a second embodiment of the present invention. As shown in FIG. 2, the method comprises the following steps.
  • In step S11, a first gate electrode, a second gate electrode, a first active layer, a second active layer, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode are formed on a base substrate.
  • Specifically, by taking a bottom gate type thin film transistor as an example, step S11 may comprise the following steps.
  • In step S111, the first gate electrode and the second gate electrode are formed on the base substrate by a patterning process.
  • In step S112, the first active layer and the second active layer are formed on the base substrate on which the first gate electrode and the second gate electrode are formed, by a patterning process.
  • Before step S112, the method further comprises forming a gate insulation layer on the first gate electrode and the second electrode. After the gate insulation layer is formed, the first active layer and the second active layer are respectively formed on the regions of the gate insulation layer corresponding to the first gate electrode and the second gate electrode by a patterning process.
  • FIG. 3 a is a schematic diagram illustrating forming a first gate electrode 31, a second gate electrode 32, a first active layer 41, a second active layer 42 and a gate insulation layer 2 in the method for fabricating the CMOS transistor. As shown in FIG. 3 a, a gate metal material layer is deposited on two regions (a first region and a second region) on a base substrate 1, and the first gate electrode 31 and the second gate electrode 32 are formed by a patterning process, respectively; the gate insulation layer 2 is deposited on the first gate electrode 31 and the second gate electrode 32; an active metal oxide material layer is deposited on the regions of the gate insulation layer 2 corresponding to the first gate electrode 31 and the second gate electrode 32, the active metal oxide material is preferably zinc oxide, and the first active layer 41 and the second active layer 42 are formed by a patterning process, respectively.
  • In step S113, the first source electrode, the second source electrode, the first drain electrode and the second drain electrode are formed on the first active layer and the second active layer by a patterning process.
  • FIG. 3 b is a schematic diagram illustrating forming the first source electrode 61, the first drain electrode 71, the second source electrode 62 and the second drain electrode 72 in the method for fabricating the CMOS transistor. As shown in FIG. 3 b, a source and drain metal material layer is deposited on the first active layer 41 and the second active layer 42, and the first source electrode 61, the first drain electrode 71, the second source electrode 62 and the second drain electrode 72 are formed by a patterning process, respectively. In the embodiment, the patterning process may at least include photoresist coating, mask plate masking, exposure, development and photoresist stripping.
  • Preferably, between step S112 and step S113, the method further comprises forming an etch stop layer on the first active layer and the second active layer by a patterning process. After the etch stop layer is formed, the first source electrode, the second source electrode, the first drain electrode and the second drain electrode are formed on the etch stop layer by a patterning process.
  • In step S12, first dopant ions are injected into the first active layer and second dopant ions are injected into the second active layer, by a doping process, a concentration of the first dopant ions is smaller than that of the second dopant ions.
  • Specifically, the first active layer 41 and the second active layer 42 are both zinc oxide material layer. The first dopant ions and the second dopant ions are both N ions. During injecting the first dopant ions into the first active layer 41 and injecting the second dopant ions into the second active layer 42 by the doping process, does and energy of ion implantation for the first active layer 41 and the second active layer 42 are respectively controlled according to concentrations of zinc oxide in the first active layer 41 and the second active layer 42, so as to obtain the first dopant ions and the second dopant ions with different concentrations of dopant ions and allow the concentration of the first dopant ions to be smaller than that of the second dopant ions. After the doping process, the first active layer 41 is an N type active layer, and the second active layer 42 is a P type active layer.
  • Preferably, between step S11 and step S12, the method further comprises forming a planarization layer 8 on the first source electrode 61, the second source electrode 62, the first drain electrode 71 and the second drain electrode 72, as shown in FIG. 3 b.
  • Specifically, step S12 may comprise the following steps.
  • In step S121, a photoresist layer is formed on the planarization layer 8, the photoresist layer includes a first photoresist region and a second photoresist region, the first photoresist region corresponds to the first active layer, and the second photoresist region corresponds to the second active layer.
  • FIG. 3 c is a schematic diagram illustrating forming a photoresist layer in the method for fabricating the CMOS transistor. As shown in FIG. 3 c, specifically, forming the photoresist layer on the planarization layer 8 comprises: applying a photoresist layer on the planarization layer 8, a thickness of the photoresist layer being equal to or larger than 3 μm; and performing mask plate masking and exposure on the photoresist layer by using a half tone mask plate and performing development to form the first photoresist region 91 and the second photoresist region 92. The thickness of the first photoresist region 91 is larger than that of the second photoresist region 92, preferably, the thickness of the first photoresist region is ranged from 1.7 μm to 2.3 μm, and the thickness of the second photoresist region is ranged from 0.7 μm to 1.3 μm.
  • In step S122, the doping process is performed on the first active layer through the first photoresist region, so that the N ions are injected into the first active layer.
  • In step S123, the doping process is performed on the second active layer through the second photoresist region, so that the N ions are injected into the second active layer.
  • FIG. 3 d is a schematic diagram illustrating ion implantation in the method for fabricating the CMOS transistor. As shown in FIG. 3 d, the first photoresist region 91 corresponds to the first active layer 41, and the second photoresist layer 92 corresponds to the second active layer 42. When performing the N ion injection through the first photoresist region 91 and the second photoresist region 92, the first photoresist region 91 and the second photoresist region 92 may block N ion injection to reduce the injection concentration of N ion. Since the thickness of the first photoresist region 91 is larger than that of the second photoresist region 92, so that the concentration of N ions injected into the first active layer 41 through the first photoresist region 91 is smaller than that of N ions injected into the second active layer 42 through the second photoresist region 92.
  • In step S124, the photoresist layer is removed.
  • FIG. 3 e is a schematic diagram illustrating removing the photoresist layer in the method for fabricating the CMOS transistor. As shown in FIG. 3 e, the remaining photoresist layer is removed to result in the CMOS transistor.
  • Preferably, the first active layer 41 and the second active layer 42 are both made of oxide material. The oxide material is zinc oxide.
  • Preferably, in the step of forming the etch stop layer (i.e., between step S112 and step S113), the method further comprises forming a first via hole, a second via hole, a third via hole and a fourth via hole in the etch stop layer by a patterning process, a position of the first via hole corresponds to the first source electrode and the first active layer, a position of the second via hole corresponds to the first drain electrode and the first active layer, a position of the third via hole corresponds to the second source electrode and the second active layer, and a position of the fourth via hole corresponds to the second drain electrode and the second active layer, so that the first source electrode and the first drain electrode are connected with the first active layer through the first via hole and second via hole, respectively, and the second source electrode and the second drain electrode are connected with the second active layer through the third via hole and fourth via hole, respectively.
  • A third embodiment of the present invention provides a display panel that comprises CMOS transistors.
  • The CMOS transistor in this embodiment utilizes the CMOS transistor in the first embodiment, and the specific implementation thereof refers to the first embodiment and will not be described in detail herein.
  • A fourth embodiment of the present invention provides a display device that comprises a display panel, and the display panel comprises CMOS transistors.
  • The display device in this embodiment utilizes the CMOS transistor in the first embodiment, and the specific implementation thereof refers to the first embodiment and will not be described in detail herein.
  • It should be understood that, the implementations described above are merely exemplary implementations for describing the principle of the present invention, but the present invention is not limited thereto. For the persons skilled in the art, various variations and improvements may be made without departing from the spirit and essence of the present invention, and these variations and improvements shall be deemed as falling within the protection scope of the present invention.

Claims (21)

1-18. (canceled)
19. A CMOS transistor, comprising a first region and a second region provided on a base substrate, the first region comprising a first gate electrode, a first active layer, a first source electrode and a first drain electrode, and the second region comprising a second gate electrode, a second active layer, a second source electrode and a second drain electrode,
wherein first dopant ions are formed in the first active layer, second dopant ions are formed in the second active layer, and a concentration of the first dopant ions is smaller than that of the second dopant ions; the first active layer is an n-type active layer, and the second active layer is a p-type active layer.
20. The CMOS transistor of claim 19, wherein an etch stop layer is formed between the first active layer and the first source and drain electrodes and between the second active layer and the second source and drain electrodes.
21. The CMOS transistor of claim 19, wherein the first active layer and the second active layer are oxide material layer.
22. The CMOS transistor of claim 21, wherein the oxide material layer is zinc oxide layer.
23. The CMOS transistor of claim 20, wherein a first via hole, a second via hole, a third via hole and a fourth via hole are formed in the etch stop layer, the first source electrode and the first drain electrode are connected with the first active layer through the first via hole and the second via hole, respectively, and the second source electrode and the second drain electrode are connected with the second active layer through the third via hole and the fourth via hole, respectively.
24. The CMOS transistor of claim 19, wherein the first dopant ions and the second dopant ions are both N ions.
25. A display device, comprising a display panel, the display panel comprising CMOS transistors, the CMOS transistor comprising a first region and a second region provided on a base substrate, the first region comprising a first gate electrode, a first active layer, a first source electrode and a first drain electrode, and the second region comprising a second gate electrode, a second active layer, a second source electrode and a second drain electrode,
wherein first dopant ions are formed in the first active layer, second dopant ions are formed in the second active layer, and a concentration of the first dopant ions is smaller than that of the second dopant ions; the first active layer is an n-type active layer, and the second active layer is a p-type active layer.
26. The display device of claim 25, wherein an etch stop layer is formed between the first active layer and the first source and drain electrodes and between the second active layer and the second source and drain electrodes.
27. The display device of claim 25, wherein the first active layer and the second active layer are oxide material layer.
28. The display device of claim 25, wherein the first dopant ions and the second dopant ions are both N ions.
29. A method for fabricating a CMOS transistor, comprising steps of:
forming a first gate electrode, a second gate electrode, a first active layer, a second active layer, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode on a base substrate; and
injecting first dopant ions into the first active layer and injecting second dopant ions into the second active layer by a doping process, wherein a concentration of the first dopant ions is smaller than that of the second dopant ions, the first active layer is an n-type active layer, and the second active layer is a p-type active layer.
30. The method for fabricating the CMOS transistor of claim 29, wherein the step of forming a first gate electrode, a second gate electrode, a first active layer, a second active layer, a first source electrode, a second source electrode, a first drain electrode and a second drain electrode on a base substrate comprises:
forming the first gate electrode and the second gate electrode on the base substrate by a patterning process;
forming the first active layer and the second active layer on the base substrate on which the first gate electrode and the second gate electrode are formed; and
forming the first source electrode, the second source electrode, the first drain electrode and the second drain electrode on the first active layer and the second active layer by a patterning process.
31. The method for fabricating the CMOS transistor of claim 29, wherein a planarization layer is formed on the first source electrode, the second source electrode, the first drain electrode and the second drain electrode before injecting the dopant ions;
the step of injecting first dopant ions into the first active layer and injecting second dopant ions into the second active layer by a doping process comprises:
forming a photoresist layer on the planarization layer, the photoresist layer comprising a first photoresist region and a second photoresist region, the first photoresist region corresponding to the first active layer, and the second photoresist region corresponding to the second active layer;
performing the doping process on the first active layer through the first photoresist region to inject N ions into the first active layer;
performing the doping process on the second active layer through the second photoresist region to inject N ions into the second active layer; and
removing the photoresist layer.
32. The method for fabricating the CMOS transistor of claim 31, wherein the step of forming the photoresist layer on the planarization layer comprises:
applying photoresist on the planarization layer; and
performing mask plate masking and exposure by using a half tone mask and performing development to form the first photoresist region and the second photoresist region.
33. The method for fabricating the CMOS transistor of claim 32, wherein a thickness of the first photoresist region is larger than that of the second photoresist region.
34. The method for fabricating the CMOS transistor of claim 33, wherein the thickness of the photoresist layer is equal to or larger than 3 μm, the thickness of the first photoresist region is ranged from 1.7 μm to 2.3 μm, and the thickness of the second photoresist region is ranged from 0.7 μm to 1.3 μm.
35. The method for fabricating the CMOS transistor of claim 29, wherein the first active layer and the second active layer are made of oxide material.
36. The method for fabricating the CMOS transistor of claim 35, wherein the oxide material is zinc oxide.
37. The method for fabricating the CMOS transistor of claim 29, wherein before forming the first source electrode, the second source electrode, the first drain electrode and the second drain electrode, an etch stop layer is formed on the first active layer and the second active layer by a patterning process, and a first via hole, a second via hole, a third via hole and a fourth via hole are formed in the etch stop layer, so that the first source electrode and the first drain electrode are connected with the first active layer through the first via hole and the second via hole, respectively, and the second source electrode and the second drain electrode are connected with the second active layer through the third via hole and the fourth via hole, respectively.
38. The method for fabricating the CMOS transistor of claim 29, wherein the first dopant ions and the second dopant ions are both N ions.
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Publication number Priority date Publication date Assignee Title
WO2022260478A1 (en) * 2021-06-11 2022-12-15 주성엔지니어링(주) Method of manufacturing power semiconductor element
US20230163200A1 (en) * 2021-03-08 2023-05-25 Ordos Yuansheng Optoelectronics Co., Ltd. Method for manufacturing display substrate

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106505067B (en) * 2015-09-08 2019-10-25 鸿富锦精密工业（深圳）有限公司 Cmos device and manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011135945A1 (en) * 2010-04-28 2011-11-03 シャープ株式会社 Semiconductor device, display device, and production method for semiconductor device and display device
US20130187154A1 (en) * 2010-07-30 2013-07-25 Hitachi, Ltd. Oxide semiconductor device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1806322A (en) * 2003-06-20 2006-07-19 夏普株式会社 Semiconductor device, its manufacturing method, and electronic device
KR100585410B1 (en) * 2003-11-11 2006-06-07 엘지.필립스 엘시디 주식회사 Method for switching and driving device for liquid crystal display device with driving circuit
KR101496148B1 (en) * 2008-05-15 2015-02-27 삼성전자주식회사 Semiconductor device and method of manufacturing the same
KR101100999B1 (en) * 2009-01-13 2011-12-29 삼성모바일디스플레이주식회사 CMOS Thin Film Transistor and fabrication method thereof and Organic Light Emitting Display device using thereof
JP6004635B2 (en) * 2011-02-01 2016-10-12 キヤノン株式会社 Manufacturing method of semiconductor device
CN102881571B (en) * 2012-09-28 2014-11-26 京东方科技集团股份有限公司 Active layer ion implantation method and active layer ion implantation method for thin-film transistor
CN103000631A (en) * 2012-12-12 2013-03-27 京东方科技集团股份有限公司 Complementary metal oxide semiconductor (CMOS) circuit structure and manufacture method and display device thereof
CN104638017B (en) * 2015-02-04 2017-10-13 京东方科技集团股份有限公司 Thin film transistor (TFT), dot structure and preparation method thereof, array base palte, display device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011135945A1 (en) * 2010-04-28 2011-11-03 シャープ株式会社 Semiconductor device, display device, and production method for semiconductor device and display device
US20130175535A1 (en) * 2010-04-28 2013-07-11 Sharp Kabushiki Kaisha Semiconductor device, display device, and production method for semiconductor device and display device
US20130187154A1 (en) * 2010-07-30 2013-07-25 Hitachi, Ltd. Oxide semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230163200A1 (en) * 2021-03-08 2023-05-25 Ordos Yuansheng Optoelectronics Co., Ltd. Method for manufacturing display substrate
WO2022260478A1 (en) * 2021-06-11 2022-12-15 주성엔지니어링(주) Method of manufacturing power semiconductor element

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