WO2014169601A1 - 低温多晶硅的制作方法、低温多晶硅薄膜和薄膜晶体管 - Google Patents
低温多晶硅的制作方法、低温多晶硅薄膜和薄膜晶体管 Download PDFInfo
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- WO2014169601A1 WO2014169601A1 PCT/CN2013/085683 CN2013085683W WO2014169601A1 WO 2014169601 A1 WO2014169601 A1 WO 2014169601A1 CN 2013085683 W CN2013085683 W CN 2013085683W WO 2014169601 A1 WO2014169601 A1 WO 2014169601A1
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- laser
- amorphous silicon
- temperature polysilicon
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- silicon layer
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 68
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000010409 thin film Substances 0.000 title claims abstract description 21
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 54
- 238000005224 laser annealing Methods 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000009826 distribution Methods 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 36
- 238000004519 manufacturing process Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- HGCGQDMQKGRJNO-UHFFFAOYSA-N xenon monochloride Chemical group [Xe]Cl HGCGQDMQKGRJNO-UHFFFAOYSA-N 0.000 claims description 2
- VZPPHXVFMVZRTE-UHFFFAOYSA-N [Kr]F Chemical compound [Kr]F VZPPHXVFMVZRTE-UHFFFAOYSA-N 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 78
- 239000013078 crystal Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229920001621 AMOLED Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- XJHCXCQVJFPJIK-UHFFFAOYSA-M caesium fluoride Chemical compound [F-].[Cs+] XJHCXCQVJFPJIK-UHFFFAOYSA-M 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- YBCAZPLXEGKKFM-UHFFFAOYSA-K ruthenium(iii) chloride Chemical group [Cl-].[Cl-].[Cl-].[Ru+3] YBCAZPLXEGKKFM-UHFFFAOYSA-K 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- YRQNNUGOBNRKKW-UHFFFAOYSA-K trifluororuthenium Chemical compound F[Ru](F)F YRQNNUGOBNRKKW-UHFFFAOYSA-K 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/02518—Deposited layers
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
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- H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour
- H10K71/421—Thermal treatment, e.g. annealing in the presence of a solvent vapour using coherent electromagnetic radiation, e.g. laser annealing
Definitions
- Embodiments of the present invention relate to a method of fabricating low temperature polysilicon, a low temperature polysilicon film based thereon, and a thin film transistor having the low temperature polysilicon film. Background technique
- the active matrix organic light-emitting diode panel has the advantages of high image quality, short response time of moving image, low power consumption, wide viewing angle and ultra-light and ultra-thin, making it the preferred choice for future display technology.
- AMOLED's backplane technology the fabrication of polysilicon layers includes excimer laser annealing (ELA), solid phase crystallization (SPC) and metal induced crystallization (MIC).
- ELA excimer laser annealing
- SPC solid phase crystallization
- MIC metal induced crystallization
- a method for realizing the production of an active layer of a transistor in a backplane is an excimer laser annealing (ELA) method.
- the excimer laser annealing (ELA) process is a relatively complex annealing process.
- ELA excimer laser annealing
- the control of grain size and grain uniformity has been a hot topic in the field of technology. Because the number and distribution of polycrystalline silicon grains covered by the channel region of the low-temperature polysilicon thin film transistor, that is, the uniformity problem, will directly affect the electrical properties of the low-temperature polysilicon thin film transistor, such as mobility, mobility, and threshold voltage uniformity. Wait.
- the thickness distribution of the amorphous silicon film is usually uneven, and the amorphous silicon film is usually thick in the middle thin portion or thin in the middle thick portion. Even amorphous silicon films with better uniformity may have different distributions of film thicknesses.
- Conventional embodiments of the present invention provide a method for fabricating low-temperature polysilicon, comprising: forming a buffer layer on a substrate; forming an amorphous silicon layer on the buffer layer; performing heat treatment after forming the amorphous silicon layer; And according to the thickness distribution of the amorphous silicon layer, it is divided into a plurality of regions and subjected to laser annealing treatment to form a polysilicon layer.
- the thickness distribution of the amorphous silicon layer it is divided into at least one film layer thickness region and at least one film layer thin region for laser annealing treatment; wherein, when performing laser annealing treatment, the film layer thickness is The laser energy density used in the zone is greater than the laser energy density used in the thin zone of the film layer Degree.
- the amorphous silicon layer is divided into three regions, the thinner middle region is the second region, and the thicker two portions are the first region and the third region, respectively; the laser annealing condition in the first region
- the laser pulse frequency is about 200-400 Hz, the overlap rate is about 92%-98%, the laser energy density is about 240-250 mJ/cm 2
- the laser annealing condition in the second zone is: the laser pulse frequency is about 200-400Hz, the overlap ratio is about 92%-98%, the laser energy density is about 230-240 mJ/cm 2
- the laser annealing condition in the third zone is: the laser pulse frequency is about 200-400HZ, and the overlap ratio is about 92%-98%, the laser energy density is about 240-250 mJ/cm 2 .
- the amorphous silicon layer is divided into three regions, the thicker central region is the second region, and the thinner two sides are the first region and the third region, respectively; laser annealing in the first region
- the conditions are: laser pulse frequency is about 200-400HZ, overlap rate is about 92%-98%, laser energy density is about 220-250 mJ/cm 2 ; laser annealing condition in the second zone is: laser pulse frequency is about 200-400 Hz, the overlap ratio is about 92%-98%, the laser energy density is about 260-280 mJ/cm 2 ; the laser annealing condition in the third zone is: the laser pulse frequency is about 200-400 Hz, the overlap ratio is About 92%-98%, the laser energy density is about 250-270 mJ/cm 2 .
- the buffer layer comprises a silicon oxide film layer of about 50-150 nm thick deposited on the substrate of the substrate and a silicon oxide film layer of about 100-350 nm thick deposited later.
- an amorphous silicon layer of about 30-50 nm is deposited on the buffer layer.
- the amorphous silicon layer is subjected to heat treatment for about 0.5 to 3 hours at a temperature of about 400 to 500 °C.
- the amorphous silicon layer is subjected to laser annealing treatment using an excimer laser.
- the excimer laser is ruthenium chloride or ruthenium fluoride or an argon fluoride excimer laser.
- Embodiments of the present invention also provide a low temperature polysilicon film prepared based on the above method, comprising a buffer layer and a polysilicon layer sequentially formed on the same side of the substrate.
- Embodiments of the present invention also provide a thin film transistor including the above low temperature polysilicon film.
- FIG. 2 is a schematic structural view of a substrate of a village in the present invention.
- FIG. 3 is a thickness distribution diagram of an amorphous silicon layer according to Embodiment 1 of the present invention.
- FIG. 4 is a comparative diagram of the polycrystalline silicon grain distribution prepared by the method of the first embodiment and the conventional method;
- FIG. 5 is a thickness distribution diagram of the amorphous silicon layer according to the second embodiment of the present invention.
- Figure 6 is a comparison of the polycrystalline silicon grain distribution prepared by the method of the second embodiment and the conventional method.
- an embodiment of the present invention provides a method for fabricating a low temperature (generally referred to as a temperature below 600 ° C) polysilicon (LTPS), comprising: forming (eg, depositing) a buffer layer on a substrate of a substrate. 20; forming, for example, depositing an amorphous silicon layer 30 on the buffer layer 20; performing heat treatment after forming the amorphous silicon layer; and dividing the amorphous silicon layer 30 into a plurality of regions for laser annealing treatment according to the thickness distribution. Annealing is performed on different regions using lasers of different energies to convert the amorphous silicon layer into a polysilicon layer.
- LTPS low temperature polysilicon
- the substrate substrate 10 may be pre-cleaned first.
- the pre-cleaning can be carried out in various ways, for example, by washing with a cleaning liquid or by using a wind knife.
- the buffer layer 20 can function, for example, to prevent metal ions in the substrate substrate 10 from diffusing to the prepared LTPS active region, reducing defect centers and reducing leakage current generation; and a suitable buffer layer can improve the back surface of the polysilicon. Quality, prevents leakage current at the back interface of polysilicon; proper buffer layer thickness reduces heat transfer, slows the cooling rate of silicon heated by laser, and helps to form larger crystalline grains.
- the heat treatment can dehydrogenate the amorphous silicon layer 30 to prevent laser annealing of the amorphous silicon layer 30. Hydrogen explosion occurs.
- the buffer layer 20 may be deposited on the substrate 10 by plasma enhanced chemical vapor deposition (PECVD).
- PECVD plasma enhanced chemical vapor deposition
- the buffer layer 20 includes a double buffer layer in which a silicon nitride (SiN x ) thin film layer 21 of about 50 to 150 nm thick and a silicon oxide (SiO 2 ) thin film layer 22 of about 100 to 350 nm are sequentially formed on the substrate substrate 10.
- the function of the double buffer layer is as follows: silicon oxide is more suitable for forming polycrystalline silicon than silicon nitride. Silicon nitride has better effect on blocking pollutants from the substrate of the village, so the amorphous silicon layer is selected.
- the upper layer of the buffer layer of the contact surface is silicon oxide, and the lower layer of the surface in contact with the substrate substrate is silicon nitride.
- the buffer layer 20 can also be a single-layer SiO 2 film layer. The effect of using a double buffer layer is better than the effect of using a single layer of Si0 2 buffer layer.
- An amorphous silicon layer 30 of about 30 to 50 nm is formed on the buffer layer 20 by a deposition method. After the step of depositing the amorphous silicon layer on the buffer layer is completed, the amorphous silicon layer is subjected to heat treatment for about 0.5 to 3 hours at a temperature of about 400 to 500 °C.
- the amorphous silicon layer is subjected to laser annealing treatment using an excimer laser, for example, laser annealing treatment using an excimer laser such as xenon chloride (XeCl), cesium fluoride or argon fluoride.
- an excimer laser such as xenon chloride (XeCl), cesium fluoride or argon fluoride.
- the thickness distribution of the amorphous silicon layer 30 at least one film thickness region and at least one film thin region are divided into laser annealing treatment.
- the thick layer of the film means that the thickness of the amorphous silicon layer in this region is relatively thick, and the thin portion of the thin film refers to the relatively thin thickness of the amorphous silicon layer in this region. It is generally divided according to the thickness distribution of the entire amorphous silicon layer.
- the laser energy density employed in the film thickness region is greater than the laser energy density employed in the thin film region.
- the method for fabricating low-temperature polysilicon considers the inconsistency of laser energy absorption by amorphous silicon of different thicknesses, and divides the amorphous silicon layer into a plurality of regions for different laser annealing treatment, and can be used for each region.
- a suitable laser annealing treatment process condition is selected to obtain a large-sized and uniformly distributed polycrystalline silicon film over the entire substrate range.
- the substrate substrate 10 used in one embodiment of the present invention is covered with an organic light-emitting diode panel 11 over the entire substrate substrate 10.
- an organic light-emitting diode panel 11 over the entire substrate substrate 10.
- Amorphous silicon layer on the substrate of the village When the thickness distribution is "the middle is thin and the two sides are thick", as shown in FIG. 3, the amorphous silicon layer can be divided into three regions, and the thinner region (for example, the thickness is less than 400 angstroms) is the second region. B1, the two sides of the thicker (for example, the thickness is greater than or equal to 400 angstroms) are the first area A1 and the third area C1, respectively, and the method for performing laser annealing treatment includes:
- the laser annealing conditions in the first zone A1 are: laser pulse frequency is about 200-400 Hz, preferably about 300 Hz, laser overlap rate is about 92%-98%, and laser energy density is about 240-250 mJ/cm 2
- the laser annealing conditions in the second zone B1 are: laser pulse frequency is about 200-400HZ, preferably about 300 Hz, laser overlap rate is about 92%-98%, laser energy density is about 230-240 mJ/cm 2
- the laser annealing conditions in the third zone C1 are: laser pulse frequency is about 200-400HZ, preferably about 300 Hz, laser overlap rate is about 92%-98%, laser energy density is about 240-250 mJ/cm 2 . Thicker and thinner are opposite. Therefore, the value of dividing the thicker and thinner regions is not limited to 400 angstroms, and may be other values.
- FIG. 4 is a schematic comparison diagram of a polycrystalline silicon grain size distribution F1 prepared by a method for preparing a low-temperature polysilicon produced by the method of the present invention, which is prepared by a conventional method of preparing a polycrystalline silicon grain size F1.
- the polycrystalline silicon crystal grains prepared by the method of the embodiment are substantially large crystal grains of uniform size, and the grain size of the ordinary method is different, the crystal grains of the central region are larger, and the crystal grains of the both sides are larger. The grain is smaller.
- the difference between this embodiment and the first embodiment is that the distribution of the three regions of the amorphous silicon layer on the substrate of the substrate is different, and the distribution of the embodiment is "the center is thick and the two sides are thin". As shown in FIG. 5, the middle portion of the thinner (for example, the thickness is less than 400 angstroms) is the second zone B2, and the two sides of the thicker (for example, the thickness is greater than or equal to 400 angstroms) are the first zone A2 and the third zone C2, respectively.
- the laser annealing treatment method includes:
- the laser annealing conditions in the first zone A2 are: the laser pulse frequency is about 200-400 Hz, preferably about 300 Hz, the laser overlap ratio is about 92%-98%, and the laser energy density is about 220-250 mJ/cm 2 .
- the laser annealing conditions in the second zone B2 are: the laser pulse frequency is about 200-400 Hz, preferably about 300 Hz, the laser overlap rate is about 92%-98%, and the laser energy density is about 260-280 mJ/cm. 2 ;
- the laser annealing conditions in the third zone C2 are: laser pulse frequency is about 200-400 Hz, preferably about 300 Hz, laser overlap rate is about 92%-98%, laser energy density is about 250-270 mJ/ Cm2.
- polycrystalline silicon grain size distribution F2 prepared by the method for preparing a polycrystalline silicon low-temperature polysilicon produced by the method of the present invention, which is prepared by a conventional method for preparing a polycrystalline silicon grain size F2; Indicate the comparison chart.
- the polycrystalline silicon crystal grains prepared by the method of the embodiment are substantially large crystal grains of uniform size, and the grain size of the ordinary method is different, the crystal grains of the central region are larger, and the crystal grains of the both sides are larger. The grain is smaller.
- the embodiment of the present invention also provides a low temperature polycrystalline silicon film prepared based on the above low temperature polysilicon fabrication method, comprising a buffer layer 20 and an amorphous silicon layer 30 which are sequentially formed on the same side of the substrate substrate 10.
- Embodiments of the present invention also provide a thin film transistor including the above low temperature polysilicon film.
- the thin film transistor includes a gate electrode, a gate insulating layer, an active layer using the above low temperature polysilicon film, a source and a drain, and the thin film transistor may be of various types such as a top gate type, a bottom gate type, or the like.
- the amorphous silicon layer is divided into a plurality of regions for laser annealing treatment, so that polycrystalline silicon in each region can obtain a large crystal grain size, and the polycrystalline silicon crystal grains in the entire substrate range The size is evenly distributed. Based on the low-temperature polysilicon film and the thin film transistor of the method, the polycrystalline silicon is a uniform large crystal grain.
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CN103219230B (zh) * | 2013-04-19 | 2015-09-30 | 京东方科技集团股份有限公司 | 低温多晶硅的制作方法、低温多晶硅薄膜和薄膜晶体管 |
CN103560076B (zh) | 2013-11-12 | 2016-01-06 | 深圳市华星光电技术有限公司 | 提升多晶硅层均一性的多晶硅制作方法 |
US9082615B2 (en) | 2013-11-13 | 2015-07-14 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Polysilicon manufacturing method that controls growth direction of polysilicon |
CN103594355B (zh) * | 2013-11-13 | 2016-03-16 | 深圳市华星光电技术有限公司 | 可控制多晶硅生长方向的多晶硅制作方法 |
CN104766890B (zh) * | 2014-01-06 | 2018-04-27 | 上海和辉光电有限公司 | 薄膜晶体管及其制造方法和应用 |
CN104779199B (zh) * | 2015-03-27 | 2019-01-22 | 深圳市华星光电技术有限公司 | 低温多晶硅tft基板结构及其制作方法 |
CN106373908B (zh) * | 2015-07-20 | 2019-07-02 | 成均馆大学校产学协力团 | 多晶硅沉积方法及用于其的沉积装置 |
CN106367728B (zh) * | 2015-07-20 | 2019-03-01 | 成均馆大学校产学协力团 | 多晶硅沉积方法及用于其的沉积装置 |
CN108987526A (zh) * | 2017-06-01 | 2018-12-11 | 江苏拓正茂源新能源有限公司 | 太阳能电池板的多晶硅薄膜制备方法 |
CN107799398B (zh) * | 2017-10-26 | 2020-06-23 | 京东方科技集团股份有限公司 | 多晶硅薄膜的制作方法、薄膜、晶体管、基板及激光设备 |
CN108231558B (zh) * | 2018-01-02 | 2020-07-28 | 京东方科技集团股份有限公司 | 一种准分子激光退火温度控制系统及方法和退火装置 |
CN114414747B (zh) * | 2022-03-14 | 2022-08-12 | 中芯越州集成电路制造(绍兴)有限公司 | 激光退火均匀性的验证方法 |
CN117265470A (zh) * | 2023-07-11 | 2023-12-22 | 安徽立光电子材料股份有限公司 | 一种超薄复合铜箔的制备方法及超薄复合铜箔 |
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