WO2019019266A1 - 低温多晶硅薄膜晶体管及其制作方法、显示设备 - Google Patents

低温多晶硅薄膜晶体管及其制作方法、显示设备 Download PDF

Info

Publication number
WO2019019266A1
WO2019019266A1 PCT/CN2017/100580 CN2017100580W WO2019019266A1 WO 2019019266 A1 WO2019019266 A1 WO 2019019266A1 CN 2017100580 W CN2017100580 W CN 2017100580W WO 2019019266 A1 WO2019019266 A1 WO 2019019266A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
polysilicon layer
via hole
forming
doped polysilicon
Prior art date
Application number
PCT/CN2017/100580
Other languages
English (en)
French (fr)
Inventor
李松杉
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US15/578,155 priority Critical patent/US20190221637A1/en
Publication of WO2019019266A1 publication Critical patent/WO2019019266A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/30—Organic light-emitting transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the invention belongs to the technical field of thin film transistor fabrication, and in particular to a low temperature polysilicon thin film transistor, a manufacturing method thereof and a display device.
  • liquid crystal display LCD
  • organic light emitting diode OLED
  • amorphous silicon thin film transistors are widely used as switching elements of LCD and OLED displays, but a-Si TFT LCDs are required to be thin, lightweight, high-definition, high in brightness, high in reliability, Requirements such as low power consumption are still limited.
  • Lower Temperature Polycrystal Silicon (LTPS) TFTs have significant advantages in meeting the above requirements compared to a-Si TFTs.
  • the leakage current I off of the low temperature polysilicon thin film transistor is increased, thereby affecting the characteristics of the low temperature polysilicon thin film transistor. This in turn affects the display quality of LCD and OLED displays.
  • a low temperature polysilicon thin film transistor includes: a substrate; a gate disposed on the substrate; a gate insulating layer disposed on the substrate and the gate; and a polysilicon layer Provided on the gate insulating layer, the polysilicon layer has a recess; the doped polysilicon layer, Provided on the polysilicon layer, the doped polysilicon layer has a through hole therein, the through hole completely exposes the groove; an etch barrier layer is disposed on the gate insulating layer and the doped polysilicon layer And filling the via hole and the recess, the etch barrier layer has a first via hole and a second via hole, wherein the first via hole and the second via hole respectively expose a doped polysilicon layer; a source and a drain disposed on the etch stop layer, the source filling the first via to contact a doped polysilicon layer exposed by the first via, the drain pad The second via is in contact with the doped polysilicon layer exposed by the second
  • the doped polysilicon layer is doped with boron ions.
  • the etch stop layer is made of an oxide of silicon and/or a nitride of silicon.
  • a display device comprising the above-described low temperature polysilicon thin film transistor.
  • a method for fabricating a low temperature polysilicon thin film transistor includes the steps of: providing a substrate; forming a gate on the substrate; fabricating on the substrate and the gate Forming a gate insulating layer; forming a polysilicon layer on the gate insulating layer; and forming a doped polysilicon layer on the polysilicon layer; forming a via hole in the doped polysilicon layer, and on the polysilicon layer Forming a recess, the through hole completely exposing the recess; forming an etch stop layer on the doped polysilicon layer, the gate insulating layer and the polysilicon layer; forming and forming in the etch barrier layer a first via and a second via, the first via and the second via exposing a doped polysilicon layer, respectively; forming a source and a drain on the etch stop layer, the source Filling the first via to contact a doped polysilicon layer exposed by the first via, the drain filling the second via to
  • the step of “forming a polysilicon layer on the gate insulating layer and a doped polysilicon layer on the polysilicon layer” includes: forming amorphous silicon on the gate insulating layer a layer; implanting ions in the amorphous silicon layer by ion implantation; recrystallizing the amorphous silicon layer by means of rapid thermal annealing to form a polysilicon layer and doping on the polysilicon layer Polysilicon layer.
  • the step of “forming a via hole in the doped polysilicon layer and in the polysilicon layer includes forming a via hole in the doped polysilicon layer using a halftone mask process, and forming a recess on the polysilicon layer.
  • the etch stop layer is made of an oxide of silicon and/or a nitride of silicon.
  • the ions implanted by the ion implantation technique are boron ions.
  • the invention has the beneficial effects that the invention can prevent the source and the drain from directly contacting the polysilicon layer, thereby reducing the leakage current of the low-temperature polysilicon thin film transistor, and further improving the characteristics of the low-temperature polysilicon thin film transistor.
  • FIG. 1 is a schematic structural view of a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • FIGS. 2A through 2I are process diagrams of a low temperature polysilicon thin film transistor in accordance with an embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a low temperature polysilicon thin film transistor according to an embodiment of the present invention.
  • a low temperature polysilicon thin film transistor includes a substrate 100, Gate 200, gate insulating layer 300, polysilicon layer 400, etch stop layer 500, source 600, drain 700, passivation layer 800, and doped polysilicon layer 900.
  • the substrate 100 may be, for example, a transparent glass substrate or a resin substrate, but the present invention is not limited thereto.
  • the gate 200 is disposed on the substrate 100.
  • the gate electrode 200 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto.
  • the gate insulating layer 300 is disposed on the gate 200 and the substrate 100.
  • the gate insulating layer 300 may be, for example, a SiN x /SiO x structure formed on the gate 200 and the substrate 100, but the present invention is not limited thereto.
  • the gate insulating layer 300 may also be a single layer of SiN x . Structure or SiO x structure.
  • the polysilicon layer 400 is disposed on the gate insulating layer 300.
  • the polysilicon active layer 400 has a recess 410 thereon.
  • the doped polysilicon layer 900 is disposed on the polysilicon layer 400.
  • the doped polysilicon layer 900 has a via 910 therein that completely exposes the recess 410.
  • the etch barrier layer 500 is disposed on the doped polysilicon layer 900 and the gate insulating layer 300, and the etch barrier layer 500 fills the via 910 and the recess 410 to be in contact with the polysilicon layer 400.
  • the etch barrier layer 500 has a first via 510 and a second via 520 exposing the doped polysilicon layer 900 on the side (left side) of the via 910 and the recess 410, and the second The via 520 exposes the doped polysilicon layer 900 on the other side (right side) of the via 910 and the recess 410.
  • the etching stopper layer 500 is formed of SiN x and/or SiO x , but the present invention is not limited thereto.
  • the source 600 and the drain 700 are disposed on the etch stop layer 500, and the source 600 fills the first via 510 to be in contact with the doped polysilicon layer 900 on the side of the via 910 and the recess 410, and the drain 700 is filled.
  • the via 520 is in contact with the doped polysilicon layer 900 on the other side of the via 910 and the recess 410.
  • the source 600 and the drain 700 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto.
  • the passivation layer 800 is disposed on the source 600, the drain 700, and the etch stop layer 500.
  • the passivation layer 800 is formed of an oxide of silicon such as SiO x , but the present invention is not limited thereto.
  • the low temperature polysilicon thin film transistor according to an embodiment of the present invention can be applied to a display device such as a liquid crystal display device and an OLED display device.
  • the low temperature polysilicon thin film transistor of the embodiment of the present invention can prevent the source 600 and the drain 700 from directly contacting the polysilicon layer 410, thereby reducing the leakage current of the low temperature polysilicon thin film transistor, thereby greatly improving the characteristics of the low temperature polysilicon thin film transistor.
  • FIGS. 2A through 2I are process diagrams of a low temperature polysilicon thin film transistor in accordance with an embodiment of the present invention.
  • Step 1 Referring to FIG. 2A, a substrate 100 is provided.
  • the substrate 100 may be, for example, an insulating and transparent glass substrate or a resin substrate, but the invention is not limited thereto.
  • a gate electrode 200 is formed on the substrate 100.
  • the gate electrode 400 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto.
  • a gate insulating layer 300 is formed on the substrate 100 and the gate 200.
  • the gate insulating layer 300 may be, for example, a SiN x /SiO x structure formed on the semiconductor body layer 210, but the invention is not limited thereto, for example, the gate insulating layer 300 may also be a single-layer SiN x structure or SiO x structure.
  • Step 4 Referring to FIG. 2D, a polysilicon layer 400 and a doped polysilicon layer 900 on the polysilicon layer are formed on the gate insulating layer 300.
  • the method of forming the polysilicon layer 400 and the doped polysilicon layer 900 on the polysilicon layer specifically includes: first, forming an amorphous silicon layer on the gate insulating layer 300 by plasma enhanced chemical vapor deposition (PECVD); Implanting ions (such as boron ions, etc.) into the amorphous silicon layer by ion implantation (Ion Implant) technology; then, recrystallizing the amorphous silicon layer by means of Rapid Thermal Anneal Thereby, a polysilicon layer 400 and a doped polysilicon layer 900 on the polysilicon layer 400 are formed.
  • PECVD plasma enhanced chemical vapor deposition
  • Ion Implant ion implantation
  • Step 5 Referring to FIG. 2E, a via 910 is formed in the doped polysilicon layer 900 and is in the polysilicon layer. A groove 410 is formed in the 400, and the through hole 910 completely exposes the groove 410.
  • a specific method of forming the via 910 and the recess 410 is: forming a via 910 in the doped polysilicon layer 900 by using a Halftone Mask (HTM) process, and forming a recess 410 on the polysilicon layer 400,
  • HTM Halftone Mask
  • the invention is not limited thereto.
  • Step 6 Referring to FIG. 2F, an etch stop layer 500 is formed on the gate insulating layer 300, the polysilicon layer 400, and the doped polysilicon layer 900.
  • the etching stopper layer 500 is formed of an oxide of silicon such as SiO x and/or a nitride of silicon such as SiN x , but the present invention is not limited thereto.
  • Step 7 referring to FIG. 2G, forming a first via 510 and a second via 520 in the etch barrier 500, the first via 510 exposing the doping on the side (left side) of the via 910 and the recess 410
  • the polysilicon layer 900 is exposed
  • the second via 520 exposes the doped polysilicon layer 900 on the other side (right side) of the via 910 and the recess 410.
  • Step 8 Referring to FIG. 2H, a source 600 and a drain 700 are formed on the etch barrier 500, and the source 600 fills the first via 510 to form a doped polysilicon layer on the side of the via 910 and the recess 410.
  • the drain 700 fills the second via 520 to contact the doped polysilicon layer 900 on the other side of the via 910 and the recess 410.
  • the source 600 and the drain 700 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto.
  • Step 9 Referring to FIG. 2I, a passivation layer 800 is formed on the source 600, the drain 700, and the etch barrier 500.
  • the passivation layer 800 is formed of an oxide of silicon such as SiO x , but the present invention is not limited thereto.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Mathematical Physics (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种低温多晶硅薄膜晶体管及其制作方法和显示设备。该薄膜晶体管包括：基板（100）；栅极（200），设置于基板（100）上；栅极绝缘层（300），设置于基板（100）和栅极（200）上；多晶硅层（400），设置于栅极绝缘层（300）上，多晶硅层（400）上具有凹槽（410）；掺杂多晶硅层（900），设置于多晶硅层（400）上且具有完全暴露凹槽（410）的通孔（910）；蚀刻阻挡层（500），设置于栅极绝缘层（300）和掺杂多晶硅层（900）上并填充通孔（910）和凹槽（410），且具有暴露掺杂多晶硅层（900）的第一过孔（510）和第二过孔（520）；源极（600）和漏极（700），设置于蚀刻阻挡层（500）上，源极（600）和漏极（700）分别填充第一过孔（510）和第二过孔（520），以分别与掺杂多晶硅层（900）接触；钝化层（800），设置于源极（600）、漏极（700）和蚀刻阻挡层（500）上。该薄膜晶体管能防止源极（600）和漏极（700）与多晶硅层（400）直接接触，从而减小漏电流。

Description

低温多晶硅薄膜晶体管及其制作方法、显示设备 技术领域
本发明属于薄膜晶体管制作技术领域，具体地讲，涉及一种低温多晶硅薄膜晶体管及其制作方法、显示设备。
背景技术
随着光电与半导体技术的演进，也带动了平板显示器(FlatPanel Display)的蓬勃发展，而在诸多平板显示器中，液晶显示器(Liquid Crystal Display，简称LCD)和有机发光二极管(OLED)显示器因具有高空间利用效率、低消耗功率、无辐射以及低电磁干扰等诸多优越特性，已成为市场的主流。
目前，作为LCD和OLED显示器的开关元件而广泛采用的是非晶硅薄膜三极管(a-Si TFT)，但a-Si TFT LCD在满足薄型、轻量、高精细度、高亮度、高可靠性、低功耗等要求仍受到限制。低温多晶硅(Lower Temperature Polycrystal Silicon，LTPS)TFT与a-Si TFT相比，在满足上述要求方面，具有明显优势。
然而在目前的低温多晶硅薄膜晶体管中，由于源极和漏极能够与未掺杂离子的多晶硅层接触，因此会导致低温多晶硅薄膜晶体管漏电流Ioff增大，从而影响低温多晶硅薄膜晶体管的特性，进而会影响LCD和OLED显示器的显示质量。
发明内容
为了解决上述现有技术的问题，本发明的目的在于提供一种能够减小漏电流的低温多晶硅薄膜晶体管及其制作方法、显示设备。
根据本发明的一方面，提供了一种低温多晶硅薄膜晶体管，其包括：基板；栅极，设置于所述基板上；栅极绝缘层，设置于所述基板和所述栅极上；多晶硅层，设置于所述栅极绝缘层上，所述多晶硅层上具有凹槽；掺杂多晶硅层， 设置于所述多晶硅层上，所述掺杂多晶硅层中具有通孔，所述通孔完全暴露所述凹槽；蚀刻阻挡层，设置于所述栅极绝缘层和所述掺杂多晶硅层上并填充所述通孔和所述凹槽，所述蚀刻阻挡层中具有第一过孔和第二过孔，所述第一过孔和所述第二过孔分别暴露出掺杂多晶硅层；源极和漏极，设置于所述蚀刻阻挡层上，所述源极填充所述第一过孔，以与所述第一过孔暴露出的掺杂多晶硅层接触，所述漏极填充所述第二过孔，以与所述第二过孔暴露出的掺杂多晶硅层接触；钝化层，设置于所述源极、所述漏极和所述刻蚀阻挡层上。
可选地，所述掺杂多晶硅层中掺杂有硼离子。
可选地，所述蚀刻阻挡层由硅的氧化物和/或硅的氮化物制成。
根据本发明的另一方面，还提供了一种显示设备，其包括上述的低温多晶硅薄膜晶体管。
根据本发明的又一方面，又提供了一种低温多晶硅薄膜晶体管的制作方法，其包括步骤：提供一基板；在所述基板上制作形成栅极；在所述基板和所述栅极上制作形成栅极绝缘层；在所述栅极绝缘层上制作形成多晶硅层以及位于所述多晶硅层上的掺杂多晶硅层；在所述掺杂多晶硅层中形成通孔，并在所述多晶硅层上形成凹槽，所述通孔完全暴露所述凹槽；在所述掺杂多晶硅层、所述栅极绝缘层和所述多晶硅层上制作形成蚀刻阻挡层；在所述蚀刻阻挡层中制作形成第一过孔和第二过孔，所述第一过孔和所述第二过孔分别暴露出掺杂多晶硅层；在所述蚀刻阻挡层上制作形成源极和漏极，所述源极填充所述第一过孔，以与所述第一过孔暴露出的掺杂多晶硅层接触，所述漏极填充所述第二过孔，以与所述第二过孔暴露出的掺杂多晶硅层接触；在所述源极、所述漏极和所述刻蚀阻挡层上制作形成钝化层。
可选地，所述步骤“在所述栅极绝缘层上制作形成多晶硅层以及位于所述多晶硅层上的掺杂多晶硅层”的方法包括：在所述栅极绝缘层上制作形成非晶硅层；利用离子植入技术在所述非晶硅层中植入离子；利用快速热退火的方式技术使所述非晶硅层再结晶，从而形成多晶硅层以及位于所述多晶硅层上的掺杂多晶硅层。
可选地，所述步骤“在所述掺杂多晶硅层中形成通孔，并在所述多晶硅层 上形成凹槽”的方法包括：利用半色调掩膜工艺在所述掺杂多晶硅层中形成通孔，并在所述多晶硅层上形成凹槽。
可选地，所述蚀刻阻挡层由硅的氧化物和/或硅的氮化物制成。
可选地，所述利用离子植入技术植入的离子为硼离子。
本发明的有益效果：本发明能防止源极和漏极与多晶硅层直接接触，从而减小低温多晶硅薄膜晶体管的漏电流，进而可以大幅度改善低温多晶硅薄膜晶体管的特性。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的低温多晶硅薄膜晶体管的结构示意图；
图2A至图2I是根据本发明的实施例的低温多晶硅薄膜晶体管的制程图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚器件，夸大了层和区域的厚度。相同的标号在整个说明书和附图中表示相同的元器件。
将理解的是，当诸如层、膜、区域或基板的元件被称作“在”另一元件“上”时，该元件可以直接在所述另一元件上，或者也可以存在中间元件。可选择地，当元件被称作“直接在”另一元件“上”时，不存在中间元件。
图1是根据本发明的实施例的低温多晶硅薄膜晶体管的结构示意图。
参照图1，根据本发明的实施例的低温多晶硅薄膜晶体管包括基板100、 栅极200、栅极绝缘层300、多晶硅层400、蚀刻阻挡层500、源极600、漏极700、钝化层800和掺杂多晶硅层900。
具体而言，基板100可例如是透明的玻璃基板或者树脂基板，但本发明并不限制于此。
栅极200设置于基板100上。栅极200可以是钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
栅极绝缘层300设置于栅极200和基板100上。这里，栅极绝缘层300可例如是在栅极200和基板100上形成的SiNx/SiOx结构，但本发明并不限制于此，例如栅极绝缘层300也可以是单层的SiNx结构或SiOx结构。
多晶硅层400设置于栅极绝缘层300上。多晶硅有源层400上具有凹槽410。
掺杂多晶硅层900设置于多晶硅层400上。掺杂多晶硅层900中具有通孔910，该通孔910完全暴露凹槽410。
蚀刻阻挡层500设置于掺杂多晶硅层900和栅极绝缘层300上，并且蚀刻阻挡层500填充通孔910和凹槽410，以与多晶硅层400接触。此外，蚀刻阻挡层500具有第一过孔510和第二过孔520，第一过孔510暴露出位于通孔910和凹槽410一侧(左侧)的掺杂多晶硅层900，而第二过孔520暴露出位于通孔910和凹槽410另一侧(右侧)的掺杂多晶硅层900。在本实施例中，蚀刻阻挡层500由SiNx和/或SiOx形成，但本发明并不限制于此。
源极600和漏极700设置于蚀刻阻挡层500上，源极600填充第一过孔510，以与位于通孔910和凹槽410一侧的掺杂多晶硅层900接触，漏极700填充第二过孔520，以与位于通孔910和凹槽410另一侧的掺杂多晶硅层900接触。源极600和漏极700可采用钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
钝化层800设置于源极600、漏极700和蚀刻阻挡层500。在本实施例中，钝化层800由硅的氧化物(诸如SiOx)形成，但本发明并不限制于此。
根据本发明的实施例的低温多晶硅薄膜晶体管可应用于显示设备中，诸如液晶显示设备和OLED显示设备中。本发明的实施例的低温多晶硅薄膜晶体管能防止源极600和漏极700与多晶硅层410直接接触，从而减小低温多晶硅薄膜晶体管的漏电流，进而可以大幅度改善低温多晶硅薄膜晶体管的特性。
以下对根据本发明的实施例的低温多晶硅薄膜晶体管的制作方法进行详细描述。
图2A至图2I是根据本发明的实施例的低温多晶硅薄膜晶体管的制程图。
根据本发明的实施例的金属氧化物薄膜晶体管的制作方法包括：
步骤一：参照图2A，提供一基板100。基板100可例如为一绝缘且透明的玻璃基板或树脂基板，但本发明并不限制于此。
步骤二：参照图2B，在基板100上制作形成栅极200。栅极400可以是钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
步骤三：参照图2C，在基板100和栅极200上制作形成栅极绝缘层300。这里，栅极绝缘层300可例如是在半导体本体层210上形成的SiNx/SiOx结构，但本发明并不限制于此，例如栅极绝缘层300也可以是单层的SiNx结构或SiOx结构。
步骤四：参照图2D，在栅极绝缘层300上制作形成多晶硅层400以及位于多晶硅层上的掺杂多晶硅层900。
这里，形成多晶硅层400以及位于多晶硅层上的掺杂多晶硅层900的方法具体包括：首先，利用等离子体增强化学气相沉积法(PECVD)在栅极绝缘层300上制作形成非晶硅层；接着，利用离子植入(Ion Implant)技术在所述非晶硅层中植入离子(诸如硼离子等)；接着，以快速热退火(Rapid Thermal Anneal)的方式使所述非晶硅层再结晶，从而生成多晶硅层400以及在多晶硅层400上的掺杂多晶硅层900。
步骤五：参照图2E，在掺杂多晶硅层900中形成通孔910，并在多晶硅层 400上形成凹槽410，通孔910完全暴露凹槽410。
这里，形成通孔910和凹槽410的具体方法是：利用半色调掩膜(HalfTone Mask，HTM)工艺在掺杂多晶硅层900中形成通孔910，并在多晶硅层400上形成凹槽410，但本发明并不限制于此。
步骤六：参照图2F，在栅极绝缘层300、多晶硅层400和掺杂多晶硅层900上制作形成蚀刻阻挡层500。这里，蚀刻阻挡层500由硅的氧化物(诸如SiOx)和/或硅的氮化物(诸如SiNx)形成，但本发明并不限制于此。
步骤七，参照图2G，在蚀刻阻挡层500中制作形成第一过孔510和第二过孔520，第一过孔510暴露出位于通孔910和凹槽410一侧(左侧)的掺杂多晶硅层900，而第二过孔520暴露出位于通孔910和凹槽410另一侧(右侧)的掺杂多晶硅层900。
步骤八：参照图2H，在蚀刻阻挡层500上制作形成源极600和漏极700，源极600填充第一过孔510，以与位于通孔910和凹槽410一侧的掺杂多晶硅层900接触，漏极700填充第二过孔520，以与位于通孔910和凹槽410另一侧的掺杂多晶硅层900接触。源极600和漏极700可采用钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
步骤九：参照图2I，在源极600、漏极700和蚀刻阻挡层500上制作形成钝化层800。这里，钝化层800由硅的氧化物(诸如SiOx)形成，但本发明并不限制于此。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (9)

  1. 一种低温多晶硅薄膜晶体管，其中，包括：
    基板；
    栅极，设置于所述基板上；
    栅极绝缘层，设置于所述基板和所述栅极上；
    多晶硅层，设置于所述栅极绝缘层上，所述多晶硅层上具有凹槽；
    掺杂多晶硅层，设置于所述多晶硅层上，所述掺杂多晶硅层中具有通孔，所述通孔完全暴露所述凹槽；
    蚀刻阻挡层，设置于所述栅极绝缘层和所述掺杂多晶硅层上并填充所述通孔和所述凹槽，所述蚀刻阻挡层中具有第一过孔和第二过孔，所述第一过孔和所述第二过孔分别暴露出掺杂多晶硅层；
    源极和漏极，设置于所述蚀刻阻挡层上，所述源极填充所述第一过孔，以与所述第一过孔暴露出的掺杂多晶硅层接触，所述漏极填充所述第二过孔，以与所述第二过孔暴露出的掺杂多晶硅层接触；
    钝化层，设置于所述源极、所述漏极和所述刻蚀阻挡层上。
  2. 根据权利要求1所述的低温多晶硅薄膜晶体管，其中，所述掺杂多晶硅层中掺杂有硼离子。
  3. 根据权利要求1所述的低温多晶硅薄膜晶体管，其中，所述蚀刻阻挡层由硅的氧化物和/或硅的氮化物制成。
  4. 一种显示设备，其中，包括权利要求1所述的低温多晶硅薄膜晶体管。
  5. 一种低温多晶硅薄膜晶体管的制作方法，其中，包括步骤：
    提供一基板；
    在所述基板上制作形成栅极；
    在所述基板和所述栅极上制作形成栅极绝缘层；
    在所述栅极绝缘层上制作形成多晶硅层以及位于所述多晶硅层上的掺杂多晶硅层；
    在所述掺杂多晶硅层中形成通孔，并在所述多晶硅层上形成凹槽，所述通孔完全暴露所述凹槽；
    在所述掺杂多晶硅层、所述栅极绝缘层和所述多晶硅层上制作形成蚀刻阻挡层；
    在所述蚀刻阻挡层中制作形成第一过孔和第二过孔，所述第一过孔和所述第二过孔分别暴露出掺杂多晶硅层；
    在所述蚀刻阻挡层上制作形成源极和漏极，所述源极填充所述第一过孔，以与所述第一过孔暴露出的掺杂多晶硅层接触，所述漏极填充所述第二过孔，以与所述第二过孔暴露出的掺杂多晶硅层接触；
    在所述源极、所述漏极和所述刻蚀阻挡层上制作形成钝化层。
  6. 根据权利要求5所述的制作方法，其中，所述步骤“在所述栅极绝缘层上制作形成多晶硅层以及位于所述多晶硅层上的掺杂多晶硅层”的方法包括：
    在所述栅极绝缘层上制作形成非晶硅层；
    利用离子植入技术在所述非晶硅层中植入离子；
    利用快速热退火的方式技术使所述非晶硅层再结晶，从而形成多晶硅层以及位于所述多晶硅层上的掺杂多晶硅层。
  7. 根据权利要求5所述的制作方法，其中，所述步骤“在所述掺杂多晶硅层中形成通孔，并在所述多晶硅层上形成凹槽”的方法包括：利用半色调掩膜工艺在所述掺杂多晶硅层中形成通孔，并在所述多晶硅层上形成凹槽。
  8. 根据权利要求5所述的制作方法，其中，所述蚀刻阻挡层由硅的氧化物和/或硅的氮化物制成。
  9. 根据权利要求6所述的制作方法，其中，所述利用离子植入技术植入的离子为硼离子。
PCT/CN2017/100580 2017-07-27 2017-09-05 低温多晶硅薄膜晶体管及其制作方法、显示设备 WO2019019266A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/578,155 US20190221637A1 (en) 2017-07-27 2017-09-05 Low-temperature polysilicon thin film transistor and manufacturing method and display device thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710624547.2A CN107403841A (zh) 2017-07-27 2017-07-27 低温多晶硅薄膜晶体管及其制作方法、显示设备
CN201710624547.2 2017-07-27

Publications (1)

Publication Number Publication Date
WO2019019266A1 true WO2019019266A1 (zh) 2019-01-31

Family

ID=60402330

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/100580 WO2019019266A1 (zh) 2017-07-27 2017-09-05 低温多晶硅薄膜晶体管及其制作方法、显示设备

Country Status (3)

Country Link
US (1) US20190221637A1 (zh)
CN (1) CN107403841A (zh)
WO (1) WO2019019266A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111433917A (zh) * 2017-12-23 2020-07-17 深圳市柔宇科技有限公司 薄膜晶体管、阵列基板及显示屏

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101320714A (zh) * 2008-07-08 2008-12-10 友达光电股份有限公司 薄膜晶体管矩阵基板的制造方法
CN103311309A (zh) * 2012-03-15 2013-09-18 三星显示有限公司 薄膜晶体管、显示设备和有机发光显示设备
CN103984130A (zh) * 2014-03-28 2014-08-13 友达光电股份有限公司 像素结构及显示面板
CN106409844A (zh) * 2016-11-29 2017-02-15 深圳市华星光电技术有限公司 底栅型多晶硅tft基板及其制作方法
CN106910748A (zh) * 2017-04-10 2017-06-30 深圳市华星光电技术有限公司 一种阵列基板、显示装置及其制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101320714A (zh) * 2008-07-08 2008-12-10 友达光电股份有限公司 薄膜晶体管矩阵基板的制造方法
CN103311309A (zh) * 2012-03-15 2013-09-18 三星显示有限公司 薄膜晶体管、显示设备和有机发光显示设备
CN103984130A (zh) * 2014-03-28 2014-08-13 友达光电股份有限公司 像素结构及显示面板
CN106409844A (zh) * 2016-11-29 2017-02-15 深圳市华星光电技术有限公司 底栅型多晶硅tft基板及其制作方法
CN106910748A (zh) * 2017-04-10 2017-06-30 深圳市华星光电技术有限公司 一种阵列基板、显示装置及其制作方法

Also Published As

Publication number Publication date
US20190221637A1 (en) 2019-07-18
CN107403841A (zh) 2017-11-28

Similar Documents

Publication Publication Date Title
US10312271B2 (en) Array substrate, manufacturing method thereof and display device
WO2018196087A1 (zh) 一种阵列基板、显示装置及其制作方法
US9761447B2 (en) Method for manufacturing TFT substrate and TFT substrate manufactured thereof
WO2018188146A1 (zh) 一种阵列基板、显示装置及其制作方法
WO2016173322A1 (zh) 一种阵列基板及其制作方法、及显示装置
WO2017092142A1 (zh) 低温多晶硅tft基板的制作方法
KR100601374B1 (ko) 박막 트랜지스터 및 그 제조방법과 박막 트랜지스터를포함하는 평판표시장치
CN107425044B (zh) 一种柔性显示面板、其制作方法及显示装置
US9876040B1 (en) Method for manufacturing TFT substrate
WO2015123903A1 (zh) 一种低温多晶硅薄膜晶体管、阵列基板及其制作方法
WO2018152875A1 (zh) 薄膜晶体管的制作方法、薄膜晶体管及显示器
US9735186B2 (en) Manufacturing method and structure thereof of TFT backplane
WO2017070868A1 (zh) N型tft的制作方法
WO2020062426A1 (zh) 阵列基板及其制备方法和显示器件
WO2016201725A1 (zh) 低温多晶硅tft基板的制作方法及低温多晶硅tft基板
WO2018032579A1 (zh) 一种tft基板的制备方法
US10629746B2 (en) Array substrate and manufacturing method thereof
WO2019184026A1 (zh) Cmos晶体管的制备方法、阵列基板的制备方法
WO2018192009A1 (zh) 一种制作低温多晶硅薄膜晶体管的方法
CN107393953B (zh) 低温多晶硅薄膜晶体管及其制作方法、有机发光显示器
WO2019019266A1 (zh) 低温多晶硅薄膜晶体管及其制作方法、显示设备
WO2016165223A1 (zh) 一种多晶硅薄膜晶体管及其制作方法和显示装置
WO2019071670A1 (zh) N型薄膜晶体管及其制备方法、oled显示面板的制备方法
US20180374953A1 (en) Metal oxide thin film transistor and method of manufacturing the same, and display panel
US20190221672A1 (en) Low temperature polysilicon thin film transistor and preparation method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17919483

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17919483

Country of ref document: EP

Kind code of ref document: A1