WO2023050238A1 - 非晶硅薄膜晶体管及其制备方法、显示面板 - Google Patents

非晶硅薄膜晶体管及其制备方法、显示面板 Download PDF

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WO2023050238A1
WO2023050238A1 PCT/CN2021/121965 CN2021121965W WO2023050238A1 WO 2023050238 A1 WO2023050238 A1 WO 2023050238A1 CN 2021121965 W CN2021121965 W CN 2021121965W WO 2023050238 A1 WO2023050238 A1 WO 2023050238A1
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Prior art keywords
amorphous silicon
ions
semiconductor layer
thin film
drain
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PCT/CN2021/121965
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English (en)
French (fr)
Inventor
苏海东
李峰
方业周
姚磊
闫雷
王成龙
李凯
朱晓刚
杨桦
候林
高云
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/907,790 priority Critical patent/US20240222511A1/en
Priority to CN202180002739.4A priority patent/CN116195033A/zh
Priority to PCT/CN2021/121965 priority patent/WO2023050238A1/zh
Publication of WO2023050238A1 publication Critical patent/WO2023050238A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices

Definitions

  • the present disclosure relates to the field of display technology, in particular to an amorphous silicon thin film transistor, a manufacturing method thereof, and a display panel.
  • Thin-film transistors (thin-film transistors, TFTs) play an important role in display panels as switching devices.
  • a thin film transistor generally includes a gate, a gate insulating layer, an active layer and a source-drain layer stacked in sequence along a direction away from the substrate, and the source-drain layer includes a source and a drain.
  • the material of the active layer may be amorphous silicon (amorphous silicon, a-Si).
  • the present application provides an amorphous silicon thin film transistor, its preparation method, and a display panel, which can solve the problem of poor switching characteristics of the thin film transistor in the related art. Described technical scheme is as follows:
  • an amorphous silicon thin film transistor is provided, and the amorphous silicon thin film transistor includes:
  • An amorphous silicon semiconductor layer, a source electrode, and a drain electrode are sequentially arranged on the base substrate;
  • the region of the amorphous silicon semiconductor layer close to the source and drain contains ions doped by ion implantation process, and the surface of the amorphous silicon semiconductor layer close to the source and drain
  • the concentration of the ions in the region is greater than or equal to 5 ⁇ 10 20 ions/cm 3 .
  • a certain depth of the surface region of the amorphous silicon semiconductor layer close to the source and drain has the ions doped by the ion implantation process, and the concentration of the ions increases with the distance from the surface region Farther away and smaller.
  • a certain depth of the surface region of the amorphous silicon semiconductor layer close to the source and drain has the ions doped by the ion implantation process, and the concentration of the ions increases with the distance from the surface region The farther away first increases and then decreases;
  • the thickness of the region in which the concentration of the ions increases with distance from the surface region is smaller than the thickness of the region in which the concentration of the ions decreases with distance from the surface region.
  • the concentration of the ions is greater than or equal to 3 ⁇ 10 20 ions/cm 3 ;
  • the first depth is between 0-50 Angstroms.
  • the concentration of the ions is greater than or equal to 5 ⁇ 10 20 ions/cm 3 ;
  • the second depth is between 0 and 20 Angstroms
  • the concentration of the ions is less than or equal to 5 ⁇ 10 19 ions/cm 3 ;
  • the third depth is between 600-1300 Angstroms
  • the concentration of the ions is less than or equal to 3 ⁇ 10 19 ions/cm 3 ;
  • the fourth depth is greater than or equal to 1300 Angstroms.
  • the amorphous silicon semiconductor layer includes a source contact region, a drain contact region, and a channel region between the source contact region and the drain contact region;
  • the ions are distributed in the source contact region and the drain contact region.
  • the region of the source contact region and the drain contact region close to the base substrate is doped with the ions at a concentration less than or equal to 3 ⁇ 10 19 ions/cm 3 .
  • the doping concentration of the ions in the channel region is less than or equal to 3 ⁇ 10 19 ions/cm 3 ;
  • the thickness of the channel region, the source contact region and the drain contact region close to the base substrate is between 500-1000 angstroms.
  • the ions include phosphorous ions.
  • the amorphous silicon semiconductor layer includes a first amorphous silicon semiconductor layer and a second amorphous silicon semiconductor layer stacked along a side away from the base substrate;
  • the thickness of the first amorphous silicon semiconductor layer is smaller than that of the second amorphous silicon semiconductor layer, and the density of the first semiconductor layer is greater than that of the second semiconductor layer.
  • a ratio of the thickness of the first amorphous silicon semiconductor layer to the thickness of the second amorphous silicon semiconductor layer ranges from 0.1 to 0.5.
  • the amorphous silicon semiconductor layer is obtained by sequentially performing ion implantation, wet etching and a patterning process on the amorphous silicon film.
  • a method for preparing an amorphous silicon thin film transistor comprising:
  • the forming of the amorphous silicon semiconductor layer includes:
  • the material of the buffer layer is silicon oxide, silicon nitride or silicon oxynitride;
  • the buffer layer doped with the ions and the amorphous silicon thin film doped with the ions are etched using a wet etching process to obtain an amorphous silicon semiconductor layer, and the amorphous silicon semiconductor layer is close to
  • the concentration of the ions in the surface area of the source and drain is greater than or equal to 5 ⁇ 10 20 ions/cm 3 .
  • the wet etching process is used to etch the buffer layer doped with the ions and the amorphous silicon film doped with the ions to obtain an amorphous silicon semiconductor layer, including:
  • Etching the channel region located between the source contact region and the drain contact region in the remaining amorphous silicon film, and retaining the concentration of ions in the channel region is less than or equal to 3 ⁇ 10 19 ions per cubic centimeter.
  • the thickness of the buffer layer is smaller than the thickness of the amorphous silicon film.
  • the thickness of the buffer layer is between 200-300 angstroms
  • the thickness of the amorphous silicon film is between 1400-2000 angstroms
  • the etching thickness of the wet etching process is between 20-30 angstroms.
  • the etching solution used in the wet etching process is an acidic etching solution.
  • the etching thickness of the channel region located between the source contact region and the drain contact region is greater than or equal to 500 angstroms.
  • the atmosphere used in the ion implantation process includes phosphine, the ion dose is greater than or equal to e15 per square centimeter, and the accelerating voltage is greater than or equal to 20 kV and less than or equal to 30 kV.
  • the forming the amorphous silicon thin film on the base substrate includes:
  • the deposition rate of the first film layer is between 4-8 angstroms/second;
  • the deposition rate of the second film layer is between 30-50 Angstroms/second.
  • a display panel in yet another aspect, includes: a base substrate, and a plurality of amorphous silicon thin film transistors as described in the above aspect located on the base substrate; At the same time, the amorphous silicon thin film transistor and the low temperature polysilicon thin film crystal are provided.
  • the present application provides an amorphous silicon thin film transistor, the region of the amorphous silicon semiconductor layer near the source and the drain of the amorphous silicon thin film transistor contains ions doped by an ion implantation process, and the amorphous silicon semiconductor layer
  • the concentration of ions in the surface region close to the source and the drain is greater than or equal to 5 ⁇ 10 20 atoms/cc.
  • FIG. 1 is a schematic structural view of a display panel using an amorphous silicon thin film transistor
  • Fig. 2 is a schematic diagram of the distribution of the concentration of dopant ions in an amorphous silicon semiconductor layer along with the implantation depth;
  • FIG. 3 is a schematic structural view of a display panel using an amorphous silicon thin film transistor provided in an embodiment of the present application;
  • FIG. 4 is a schematic structural diagram of another display panel using amorphous silicon thin film transistors provided by the embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another display panel using amorphous silicon thin film transistors shown in the embodiment of the present application;
  • FIG. 6 is a flow chart of another method for manufacturing an amorphous silicon thin film transistor provided in an embodiment of the present application.
  • Fig. 7 is a schematic structural diagram of a substrate substrate provided by the implementation of the present application.
  • Fig. 8 is the variation relationship of the ion concentration in the buffer layer and the amorphous silicon film with the depth provided by the embodiment of the present application;
  • Fig. 9 is the relationship between ion concentration and depth in the amorphous silicon semiconductor layer provided by the embodiment of the present application.
  • Fig. 10 is a comparative diagram of the switching characteristics of the amorphous silicon thin film transistor prepared in the embodiment of the present application and the amorphous silicon thin film transistor prepared by the related technology;
  • FIG. 11 is a flowchart of a method for manufacturing an amorphous silicon thin film transistor provided in an embodiment of the present application.
  • Fig. 12 is a schematic structural diagram of another substrate substrate provided by the implementation of the present application.
  • FIG. 13 is a schematic structural diagram of another substrate provided by the implementation of the present application.
  • FIG. 1 is a schematic structural diagram of a display panel using amorphous silicon thin film transistors.
  • the amorphous silicon thin film transistor 10 in the display panel 01 may include: a gate (gate) 101 sequentially arranged on a base substrate (substrate) 11, a gate insulating layer (gate insulator, GI ) 102, an amorphous silicon semiconductor layer 103, a source (source) 104 and a drain (drain) 105.
  • the amorphous silicon semiconductor layer is doped with ions.
  • the N-type doped amorphous silicon semiconductor layer 103 can generally be formed by uniformly doping phosphine (PH 3 ) gas during the process of chemical vapor deposition (CVD) amorphous silicon semiconductor material.
  • PH 3 phosphine
  • CVD chemical vapor deposition
  • the production line of low temperature polysilicon (LTPS) thin film transistors usually uses ion implantation process to dope ions in the semiconductor.
  • the ion implantation process is a process in which an ion beam accelerated to a certain high energy is implanted into the surface layer of a semiconductor material to change the physical and chemical properties of the surface layer. For example, implanting boron, phosphorus or arsenic into silicon can change the conductivity of the silicon surface .
  • the depth and concentration of ion implantation can be controlled more precisely.
  • the production line equipment of low-temperature polysilicon thin film transistors can be used to develop a new preparation process for amorphous silicon thin film transistors, and produce amorphous silicon thin film transistor devices doped by ion implantation technology, which is conducive to the diversification of production line products and process integrate.
  • Fig. 2 is a schematic diagram of the concentration distribution of dopant ions in an amorphous silicon semiconductor layer with implantation depth.
  • the abscissa is the concentration of doping ions in the amorphous silicon semiconductor layer, and its unit is atoms/cubic centimeter (atoms/cc), and the ordinate is the depth of the amorphous silicon semiconductor layer, and its unit is Angstrom
  • the concentration of the dopant ions in the amorphous silicon semiconductor layer can be detected by detection equipment.
  • the detection device may be a transmission electron microscope or a secondary ion mass spectrometry (secondary ion mass spectroscopy, SIMS) analyzer, etc.
  • dopant ions are implanted into the amorphous silicon semiconductor layer through an ion implantation process, and the distribution of dopant ions in the thickness direction of the amorphous silicon semiconductor layer is approximately normal.
  • the dopant ion concentration of the surface layer of the amorphous silicon semiconductor layer close to the source and drain is low, and the ohmic contact performance between the amorphous silicon semiconductor layer and the source and drain layers is poor, which leads to the switching of the thin film transistor.
  • the characteristics are poor.
  • the switching current of the amorphous silicon thin film transistor prepared by the above ion implantation process is relatively small (for example, the switching current ratio is less than 10 5 ).
  • the amorphous silicon thin film transistor provided in the embodiment of the present application can be used in a display area of a display panel.
  • the amorphous silicon thin film transistor provided by the embodiment of the present application can be applied to small-sized mobile devices (Mobile), notebook computers (notebook, NB), tablet computers (iPAD), small and medium-sized monitors (monitor, MNT), medium and large-sized TVs (television, TV) and medium and large size MNT and other products.
  • Mobile mobile
  • notebook computers notebook, NB
  • tablet computers iPAD
  • small and medium-sized monitors monitoring
  • MNT medium and large-sized TVs
  • TV television
  • medium and large size MNT and other products medium and large size MNT and other products.
  • the amorphous silicon thin film transistor provided by the embodiment of the present application can be used in the display field or the chip field, and the display field can be a liquid crystal (liquid crystal display, LCD) display panel, an organic light-emitting diode OLED (organic light-emitting diode, OLED) display panel , quantum dot light emitting diodes (quantum dot light emitting diodes, QLED) display panels, micro light emitting diode display panels (micro light emitting diode, Micro LED) and sensing and other technical fields.
  • the amorphous silicon thin film transistor provided in the embodiment of the present application can be used as a switching thin film transistor in a pixel.
  • FIG. 3 is a schematic structural diagram of a display panel using amorphous silicon thin film transistors provided by an embodiment of the present application.
  • the amorphous silicon thin film transistor 20 in the display panel 02 may include: an amorphous silicon semiconductor layer 201 , a source 202 and a drain 203 sequentially disposed on the base substrate 21 .
  • the source electrode 202 and the drain electrode 203 are located in the same layer and can be prepared by the same patterning process. Wherein, both the source electrode 202 and the drain electrode 203 are electrically connected to the amorphous silicon semiconductor layer 201 .
  • the region of the amorphous silicon semiconductor layer 201 close to the source 202 and the drain 203 contains ions 201X doped by an ion implantation process, and the surface region of the amorphous silicon semiconductor layer 201 close to the source 202 and the drain 203
  • the concentration of ions within is greater than or equal to 5 ⁇ 10 20 ions per cubic centimeter (atoms/cc).
  • the concentration of doped ions 201X per unit volume in the surface area of the amorphous silicon semiconductor layer 201 is relatively high (ie, the number of ions per unit volume is relatively high). Therefore, better ohmic contact between the amorphous silicon semiconductor layer 201 and the source 202 and drain 203 can be achieved, and thus the amorphous silicon thin film transistor 20 can have a larger on-state current.
  • the embodiment of the present application provides an amorphous silicon thin film transistor, the region of the amorphous silicon semiconductor layer near the source and the drain contains ions doped by ion implantation process, and the amorphous silicon semiconductor layer
  • the concentration of ions in the surface region of the layer near the source and drain electrodes is greater than or equal to 5 ⁇ 10 20 atoms/cc.
  • the number of doped ions 201X per unit volume in the amorphous silicon semiconductor layer 201 is small or even zero. .
  • the amorphous silicon thin film transistor provided by the embodiment of the present application has a higher switching current ratio and better switching characteristics.
  • a certain depth in the surface region of the amorphous silicon semiconductor layer 201 close to the source electrode 202 and the drain electrode 203 has ions 201X doped by an ion implantation process, and the concentration of the ions 201X increases with the distance from the surface. Regions farther away can be increased first and then decreased. The thickness of the region where the concentration of ions 201X increases as the distance from the surface region increases is smaller than the thickness of the region where the concentration of ions 201X decreases as the distance from the surface region decreases.
  • the amorphous silicon thin film transistor provided by the embodiment of the present application has a higher switching current ratio and better switching characteristics.
  • the concentration of the ions 201X is greater than or equal to 3 ⁇ 10 20 atoms/cc.
  • the first depth is between 0-50 Angstroms.
  • the concentration of ions 201X is greater than or equal to 5 ⁇ 10 20 atoms/cc.
  • the second depth is between 0-20 Angstroms.
  • the concentration of ions 201X is less than or equal to 5 ⁇ 10 19 atoms/cc; the third depth is between 600 ⁇ 1300 angstroms.
  • the concentration of ions 201X is less than or equal to 3 ⁇ 10 19 atoms/cc; the fourth depth is greater than or equal to 1300 Angstroms.
  • FIG. 4 is a schematic structural diagram of another display panel using an amorphous silicon thin film transistor according to an embodiment of the present application.
  • the amorphous silicon semiconductor layer 201 includes a source contact region 2011 , a drain contact region 2012 , and a channel region 2013 located between the source contact region 2011 and the drain contact region 2012 .
  • the source contact region 2011 is electrically connected to the source 202
  • the drain contact region 2012 is electrically connected to the drain 203
  • Both the source contact region 2011 and the drain contact region 2012 are doped with ions 201X, and the channel region 2013 may be doped with very little ions 201X. In this way, the leakage current in the channel region 2013 can be reduced, and thus the leakage current in the amorphous silicon thin film transistor can be reduced.
  • the concentration of the dopant ions 201X in the region of the source contact region 2011 and the drain contact region 2012 close to the base substrate 21 is less than or equal to 3 ⁇ 10 19 atoms/cc. In this way, the leakage current in the region where the source contact region 2011 and the drain contact region 2012 are close to the base substrate 21 can be reduced, so that the leakage current in the amorphous silicon thin film transistor is relatively small.
  • the concentration of the dopant ions 201X in the channel region 2013 is less than or equal to 3 ⁇ 10 19 atoms/cc.
  • the thickness D1 of the channel region 2013 , the source contact region 2011 and the drain contact region 2012 close to the base substrate 21 is between 500-1000 angstroms. Based on this, on the one hand, the smaller thickness of the channel region 2013 can ensure that the number of doped ions 201X per unit volume in the channel region 2013 is smaller, so that the leakage current in the channel region 2013 is smaller; on the other hand Therefore, when the patterning process is performed on the side of the channel region 2013 away from the base substrate 21 , the channel region 2013 is thinner due to over-etching, which affects the performance of the amorphous silicon thin film transistor.
  • the thickness D2 of the source contact region 2011 and the drain contact region 2012 are equal, which can make the conductivity characteristics of the source contact region 2011 and the drain contact region 2012 basically the same, thereby making the performance of the amorphous silicon thin film transistor more stable.
  • the difference between the thickness of the source contact region 2011 and the drain contact region 2012 and the thickness of the channel region 2013 may be greater than or equal to 500 angstroms.
  • the depth of the source contact region 2011 and the drain contact region 2012 in the direction perpendicular to the thickness of the base substrate 21 where the ion 201X doping concentration is higher may be less than or equal to 500 angstroms. Therefore, the difference between the thickness of the source contact region 2011 and the drain contact region 2012 and the thickness of the channel region 2013 is greater than or equal to 500 Angstroms, so that there are ions 201X in the source contact region 2011 and the drain contact region 2012, and at the same time , can avoid having ions 201X in the channel region 2013 .
  • the leakage current in the channel 2013 can be reduced while achieving better ohmic contact between the source contact region 2011 and the source 202 , and between the drain contact region 2012 and the drain 203 . In this way, the switching characteristics of the amorphous silicon thin film transistor can be improved.
  • the ion 201X includes phosphorous ions.
  • phosphorus ions P +
  • the formation between the source electrode 202 and the drain electrode 203 and the amorphous silicon semiconductor layer 201 is better.
  • the ohmic contact is conducive to increasing the on-state current and improving the conductivity of the amorphous silicon thin film transistor in the on-state.
  • FIG. 5 is a schematic structural diagram of another display panel using amorphous silicon thin film transistors shown in the embodiment of the present application.
  • the amorphous silicon semiconductor layer includes a first amorphous silicon semiconductor layer 201 a and a second amorphous silicon semiconductor layer 201 b stacked along a side away from the base substrate 21 .
  • the thickness of the first amorphous silicon semiconductor layer 201a is less than the thickness of the second amorphous silicon semiconductor layer 201b
  • the film deposition rate when forming the first amorphous silicon semiconductor layer 201a is less than that of forming the second amorphous silicon semiconductor layer Film deposition rate at 201b.
  • the density of the film layer can be negatively correlated with the film deposition rate. That is, the greater the deposition rate of the film, the smaller the density of the film; the smaller the deposition rate of the film, the greater the density of the film. Therefore, the film deposition rate of the second amorphous silicon semiconductor layer 201b can be greater than the film deposition rate of the first amorphous silicon semiconductor layer 201a, so that the density of the first amorphous silicon semiconductor layer 201a is greater than that of the second amorphous silicon semiconductor layer 201a. Silicon semiconductor layer 201b.
  • the density of the first amorphous silicon semiconductor layer 201a can be made larger, with fewer defects, and the first The contact between the amorphous silicon semiconductor layer 201a and the gate insulating layer 205 is better, thereby ensuring the performance of the amorphous silicon thin film transistor.
  • the deposition rate of the film layer can be appropriately accelerated to improve the preparation efficiency of the amorphous silicon semiconductor layer 201 .
  • the ratio of the thickness of the first amorphous silicon semiconductor layer 201 a to the thickness of the second amorphous silicon semiconductor layer 201 b ranges from 0.1 to 0.5. Within this range, the preparation efficiency of the amorphous silicon semiconductor layer 201 can be effectively improved on the basis of ensuring the performance of the amorphous silicon semiconductor layer 201 .
  • the amorphous silicon semiconductor layer is obtained by successively performing ion implantation, wet etching and a patterning process on the amorphous silicon film.
  • precise control of the depth and quantity of ions implanted in the amorphous silicon semiconductor layer can be realized by controlling the energy and dose of ion implantation.
  • the energy of ion implantation can determine the implantation depth of ions in the amorphous silicon semiconductor layer, and the ion dose can determine the quantity of ions implanted in the amorphous silicon semiconductor layer.
  • the energy and dose of the ion implantation can be set as corresponding parameters according to actual production needs, which are not limited in this embodiment of the present application.
  • the wet etching process can accurately control the etching thickness of the amorphous silicon thin film, thereby making the etching degree of the amorphous silicon thin film relatively uniform, so as to ensure the stability of the prepared amorphous silicon thin film transistor.
  • One patterning process can realize the patterning treatment of the amorphous silicon thin film to form an amorphous silicon semiconductor layer having a source contact region, a drain contact region and a channel region.
  • the amorphous silicon thin film transistor 20 further includes a gate 204 and a gate insulating layer 205 which are located on the side of the amorphous silicon semiconductor layer 201 close to the base substrate 21 and stacked sequentially on the base substrate 21 .
  • the material of the gate insulating layer 205 may include silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or a mixed material of silicon dioxide and silicon nitride.
  • FIG. 5 shows an amorphous silicon thin film transistor with a bottom gate structure, and the amorphous silicon thin film transistor in the embodiment of the present application may also have a top gate structure, and the comparison in the embodiment of the present application is not limited.
  • the embodiment of the present application provides an amorphous silicon thin film transistor, the region of the amorphous silicon semiconductor layer of the amorphous silicon thin film transistor near the source and drain contains ions doped by ion implantation process , and the concentration of ions in the surface region of the amorphous silicon semiconductor layer close to the source and the drain is greater than or equal to 5 ⁇ 10 20 atoms/cc.
  • better ohmic contacts can be formed between the amorphous silicon semiconductor layer and the source and drain, thereby increasing the on-state current of the amorphous silicon thin film transistor.
  • the embodiment of the present application provides a method for manufacturing an amorphous silicon thin film transistor, which can be used to prepare the amorphous silicon thin film transistor 20 shown in FIG. 3 .
  • the method may include: sequentially forming an amorphous silicon semiconductor layer 201 , a source 202 and a drain 203 on a substrate 21 .
  • the amorphous silicon semiconductor layer 201 is formed, including:
  • An unpatterned amorphous silicon film and a buffer layer are sequentially deposited on the base substrate 21, and the material of the buffer layer is silicon oxide, silicon nitride or silicon oxynitride.
  • the ion implantation process is used to implant ions on the surface of the buffer layer away from the substrate, and the ions diffuse from the buffer layer to the amorphous silicon thin film layer.
  • the ion-doped buffer layer and the ion-doped amorphous silicon film are etched to obtain an amorphous silicon semiconductor layer 201, and the amorphous silicon semiconductor layer 201 is close to the source 202 and
  • the concentration of ions 201X in the surface region of the drain electrode 203 is greater than or equal to 5 ⁇ 10 20 atoms/cc.
  • the contact resistance between the source electrode 202 and the drain electrode 203 and the amorphous silicon semiconductor layer 201 can be reduced.
  • Better ohmic contact between the amorphous silicon semiconductor layer 201 and the source 202 and the drain 203 can be achieved, and thus the amorphous silicon thin film transistor 20 can have a larger on-state current. Therefore, the amorphous silicon thin film transistor 20 has a higher switching current ratio.
  • the embodiment of the present application provides a method for manufacturing an amorphous silicon thin film transistor.
  • the region near the source and drain of the amorphous silicon semiconductor layer of the amorphous silicon thin film transistor prepared by the method contains Ions are doped by an ion implantation process, and the concentration of ions in the surface region of the amorphous silicon semiconductor layer close to the source and drain is greater than or equal to 5 ⁇ 10 20 atoms/cc.
  • FIG. 6 is a flow chart of another manufacturing method of an amorphous silicon thin film transistor provided in an embodiment of the present application. This method can be used for the amorphous silicon thin film transistor provided in the above embodiments, for example, to prepare the amorphous silicon thin film transistor shown in FIG. 3 .
  • the method may include:
  • Step 501 sequentially depositing an unpatterned amorphous silicon thin film and a buffer layer on the base substrate.
  • the material of the buffer layer may be silicon oxide, silicon nitride or silicon oxynitride.
  • a base substrate 21 can be obtained first, and the first amorphous silicon sub-film is deposited on the base substrate on one side of the base substrate 21 according to the first film layer deposition rate; Layer deposition rate The second amorphous silicon semiconductor sub-film is deposited on the side of the first amorphous silicon sub-film away from the base substrate.
  • an amorphous silicon thin film is formed on the base substrate 21 .
  • the amorphous silicon thin film may cover the base substrate 21 in its entirety.
  • the deposition rate of the second film layer can be greater than the deposition rate of the first film layer, for example, the deposition rate of the first film layer can be between 4-8 angstroms/second; the deposition rate of the second film layer can be 30-50 angstroms/second between.
  • the thickness of the amorphous silicon film may be greater than or equal to 1600 angstroms and less than or equal to 2300 angstroms.
  • the thickness of the first amorphous silicon sub-film may be greater than or equal to 300 angstroms and less than or equal to 600 angstroms
  • the thickness of the second amorphous silicon sub-film may be greater than or equal to 1300 angstroms and less than or equal to 1700 angstroms.
  • the material of the base substrate 21 may include glass or polyimide and the like.
  • the thickness of the buffer layer may be smaller than that of the amorphous silicon film.
  • the thickness of the amorphous silicon film can be between 1400-2000 angstroms; the thickness of the buffer layer can be between 200-300 angstroms.
  • Step 502 using an ion implantation process to implant ions on the surface of the buffer layer away from the substrate, and the ions diffuse from the buffer layer to the amorphous silicon thin film layer.
  • the atmosphere used in the ion implantation process may include phosphine, and phosphorus ions in the phosphine may be implanted into the buffer layer and the amorphous silicon film.
  • the ion dose may be greater than or equal to e15 per square centimeter, and the accelerating voltage may be greater than or equal to 20 kV and less than or equal to 30 kV.
  • FIG. 7 is a schematic structural view of a base substrate at the end of step 502 .
  • a buffer layer 601 doped with ions 201X and an amorphous silicon thin film 602 are formed on the base substrate 21 through an ion implantation process.
  • the material used for the buffer layer is a material having similar ion permeability to amorphous silicon.
  • the material of the buffer layer may at least include silicon oxide.
  • the material of the buffer layer may also include silicon nitride.
  • FIG. 8 Based on this, after doping ions in the buffer layer and the amorphous silicon film by the ion implantation process, as shown in FIG. 8, FIG. alternative relation.
  • the abscissa is the depth, and its unit is Angstrom
  • the ordinate is the ion concentration, and its unit is atoms/cubic centimeter (atoms/cc).
  • the distribution of ions in the thickness direction of the buffer layer and the amorphous silicon film is approximately normal distribution.
  • the concentration of ions implanted into the buffer layer gradually increases in the thickness direction of the buffer layer, and the concentration of ions implanted into the amorphous silicon film first increases in the thickness direction of the amorphous silicon film. Gradually increase and then gradually decrease.
  • the thickness of the buffer layer formed in step 501 above may be determined based on the energy of ion implantation, so as to ensure that the ion implantation into the buffer layer and the amorphous silicon film
  • the ion concentration in the buffer layer gradually increases in the thickness direction of the buffer layer
  • the ion concentration in the amorphous silicon film first gradually increases in the thickness direction of the amorphous silicon film, and then gradually decreases, that is, to ensure that the ion The part with the highest concentration is located in the amorphous silicon film.
  • Step 503 using a wet etching process to etch the ion-doped buffer layer and the ion-doped amorphous silicon thin film to obtain an amorphous silicon semiconductor layer.
  • the concentration of ions in the surface region of the amorphous silicon semiconductor layer close to the source and the drain is greater than or equal to 5 ⁇ 10 20 atoms/cc.
  • Step 503 may include the following three steps 5031, 5032 and 5033:
  • the active layer region may refer to a region in the amorphous silicon thin film where an amorphous silicon semiconductor layer is to be formed.
  • Retaining the ion-implanted amorphous silicon film can be understood as not etching or only etching a part of the ion-implanted amorphous silicon film.
  • the etching thickness of the wet etching process is between 20-30 angstroms.
  • the buffer layer 601 has a fifth surface away from the base substrate 21
  • the amorphous silicon thin film 602 has a sixth surface close to the base substrate 21 . From the fifth surface to the sixth surface, the number of doped ions per unit volume in the buffer layer 601 and the amorphous silicon film 602 increases gradually at first, and then decreases gradually.
  • the buffer layer 601 and the amorphous silicon film 602 can be etched Part of the surface layer with less ions 201X per unit volume is etched away, so that the number of ions 201X per unit volume on the side away from the substrate 21 of the etched amorphous silicon film is the largest.
  • the etching solution used in the above wet etching process may be an acid etching solution, further, a hydrogen fluoride solution.
  • the portion with smaller ions per unit volume in the buffer layer 601 and the amorphous silicon thin film 602 may refer to the buffer layer 601 and the amorphous silicon thin film 602 in the direction from the fifth surface to the sixth surface.
  • the etching thickness of the wet etching process is related to the implantation energy of the ion implantation process. Generally, the greater the energy of ion implantation, the greater the depth of ion implantation, correspondingly, the greater the etching thickness of the wet etching process, so as to ensure that all the buffer layer 601 and the amorphous silicon film In 602, part of the film layer with smaller ions 201X per unit volume is etched away.
  • the etching solution used in the wet etching process is a hydrogen fluoride solution.
  • the etching thickness of the wet etching process is greater than or equal to 220 angstroms and less than or equal to 330 angstroms.
  • the etching thickness of the ion-doped amorphous silicon thin film 602 on the side away from the base substrate by wet etching process is greater than or equal to 20 angstroms and less than or equal to 30 angstroms.
  • the ratio of the etching rate of the hydrogen fluoride solution to the buffer layer 601 to the etching rate of the amorphous silicon film 602 is greater than or equal to 10.
  • the etching rate of hydrogen fluoride on the buffer layer 601 ranges from 5 angstroms/sec to 20 angstroms/sec.
  • the etching rate of the amorphous silicon thin film 602 by hydrogen fluoride is in the range of 0.5 angstrom/sec to 2 angstrom/sec.
  • the etching rate of the buffer layer 601 by the hydrogen fluoride solution is much higher than that of the amorphous silicon thin film 602, on the one hand, the fabrication efficiency of the amorphous silicon thin film transistor can be improved; on the other hand, the buffer layer 601 and the amorphous The ratio of the etching rate of the silicon film 602 controls the etching thickness of the buffer layer 601 and the amorphous silicon film 602 more accurately.
  • the etching thickness of the channel region located between the source contact region and the drain contact region is greater than or equal to 500 angstroms.
  • the amorphous silicon semiconductor layer can be obtained by etching the portion with a higher ion concentration in the channel region.
  • the finally formed amorphous silicon semiconductor layer 201 includes a source contact region 2011, a drain contact region 2012, and a channel region 2013 between the source contact region 2011 and the drain contact region 2012, the source contact Both the region 2011 and the drain contact region 2012 are doped with ions 201X, and the concentration of the doped ions 201X in the channel region 2013 is relatively small.
  • Step 504 forming a source and a drain on the side of the etched amorphous silicon film away from the substrate.
  • a metal thin film may be formed on the side of the etched amorphous silicon thin film away from the base substrate 21 .
  • the metal thin film can cover the base substrate 21 in its entirety.
  • a patterning process is performed on the metal thin film to obtain the source electrode 202 and the drain electrode 203 .
  • the source contact region 2011 is in contact with the source 202
  • the drain contact region 2012 is in contact with the drain 203 .
  • FIG. 9 for the structure of the base substrate.
  • FIG. 9 is a graph showing the variation of ion concentration with depth in the amorphous silicon semiconductor layer provided by the embodiment of the present application. Please refer to Figure 9, where the abscissa is depth and its unit is Angstrom The ordinate is the ion concentration, and its unit is atoms/cubic centimeter (atoms/cc).
  • the concentration of ions 201X in the surface region of the amorphous silicon semiconductor layer 201 close to the source 202 and the drain 203 is greater than or equal to 5 ⁇ 10 20 atoms/cc.
  • the contact resistance between the source electrode 202 and the drain electrode 203 and the amorphous silicon semiconductor layer 201 can be reduced.
  • Better ohmic contact between the amorphous silicon semiconductor layer 201 and the source 202 and the drain 203 can be achieved, and thus the amorphous silicon thin film transistor 20 can have a larger on-state current.
  • the leakage current in the region of the source contact region 2011 and the drain contact region 2012 close to the base substrate 21 can be made smaller, so that the leakage current in the amorphous silicon thin film transistor is smaller. Therefore, the amorphous silicon thin film transistor 20 has a higher switching current ratio.
  • FIG. 10 is a comparative diagram of switching characteristics of an amorphous silicon thin film transistor prepared in the embodiment of the present application and an amorphous silicon thin film transistor prepared by a related technology.
  • the abscissa is voltage, and its unit is volt (V), and the ordinate is current, and its unit is ampere (A).
  • Curve C1 in FIG. 13 is a curve of the drain current of the amorphous silicon TFT in the embodiment of the present application as a function of the gate voltage.
  • Curve C2 is the curve of the drain current of the amorphous silicon thin film transistor prepared by deposition doping in the related art as a function of the gate voltage
  • curve C3 is the amorphous silicon that uses the ion implantation process and does not etch the amorphous silicon semiconductor layer. The curve of drain current versus gate voltage of a thin film transistor.
  • the amorphous silicon thin film transistor prepared in the embodiment of the present application is compared with the amorphous silicon thin film transistor prepared in the related art.
  • Silicon thin film transistors have a large on-state current.
  • the gate voltage of the amorphous silicon thin film transistor is negative and the amorphous silicon thin film transistor is in the off state
  • the amorphous silicon thin film transistor prepared in the embodiment of the present application has a smaller The off-state current, that is, the switching current of the amorphous silicon thin film transistor prepared in the embodiment of the present application is relatively large.
  • the switching current ratio of the amorphous silicon thin film transistor in the embodiment of the present application can be greater than or equal to 10 6 .
  • the embodiment of the present application provides a method for manufacturing an amorphous silicon thin film transistor.
  • the region near the source and drain of the amorphous silicon semiconductor layer of the amorphous silicon thin film transistor prepared by the method contains Ions are doped by an ion implantation process, and the concentration of ions in the surface region of the amorphous silicon semiconductor layer close to the source and drain is greater than or equal to 5 ⁇ 10 20 atoms/cc.
  • FIG. 11 is a flowchart of a method for manufacturing an amorphous silicon thin film transistor provided in an embodiment of the present application. This method can be used for the amorphous silicon thin film transistor provided in the above embodiments, for example, to prepare the amorphous silicon thin film transistor shown in FIG. 3 . Referring to Figure 11, the method may include:
  • Step 401 forming an amorphous silicon thin film on a base substrate.
  • a base substrate 21 can be obtained first, and the first amorphous silicon sub-film is deposited on the base substrate on one side of the base substrate 21 according to the first film layer deposition rate; Layer deposition rate The second amorphous silicon semiconductor sub-film is deposited on the side of the first amorphous silicon sub-film away from the base substrate.
  • an amorphous silicon thin film is formed on the base substrate 21 .
  • the amorphous silicon thin film can cover the base substrate 21 in its entirety.
  • the second film deposition rate can be greater than the first film deposition rate, for example, the first film deposition rate can be greater than or equal to 4 angstroms/second, and less than or equal to 8 angstroms/second; the second film deposition rate It may be greater than or equal to 30 angstroms/sec and less than or equal to 50 angstroms/sec.
  • the thickness of the amorphous silicon film may be greater than or equal to 1600 angstroms and less than or equal to 2300 angstroms.
  • the thickness of the first amorphous silicon sub-film may be greater than or equal to 300 angstroms and less than or equal to 600 angstroms
  • the thickness of the second amorphous silicon sub-film may be greater than or equal to 1300 angstroms and less than or equal to 1700 angstroms.
  • the material of the base substrate 21 may include glass or polyimide and the like.
  • Step 402 doping ions in the amorphous silicon film by ion implantation process.
  • Doping ions 201X in the amorphous silicon film by ion implantation technology can control the depth and quantity (ie concentration) of ions 201X doped in the amorphous silicon film more accurately.
  • the atmosphere used in the ion implantation process may include phosphine (PH), that is, the ions 201X may be phosphorus ions.
  • PH phosphine
  • the ion dose used in the ion implantation process may be greater than or equal to e 15 per square centimeter, and the accelerating voltage may be greater than or equal to 20 kV and less than or equal to 30 kV.
  • phosphorus ions in phosphine can be implanted into the amorphous silicon film, and the phosphorus ions implanted into the amorphous silicon film can increase the conductivity of the amorphous silicon film.
  • FIG. 12 is a schematic structural diagram of another substrate at the end of step 302 .
  • the amorphous silicon film 301 on the substrate 21 has ions 201X doped by an ion implantation process.
  • Step 403 using a wet etching process to etch the side of the ion-doped amorphous silicon film away from the substrate.
  • ions 201X are implanted into the amorphous silicon film 301 through an ion implantation process, and the distribution of the ions 201X in the thickness direction of the amorphous silicon film 301 is approximately normal.
  • the amorphous silicon thin film 301 has a third surface and a fourth surface opposite, the third surface is the surface away from the base substrate 21, the second surface is the surface close to the base substrate 21, from the third surface In the direction to the fourth surface, the number of doped ions per unit volume in the amorphous silicon thin film 301 first gradually increases and then gradually decreases.
  • a wet etching process can be used to remove the ions in the amorphous silicon film 301 per unit volume. A small portion of the surface layer of 201X is etched away, so that the number of ions 201X per unit volume on the side away from the substrate 21 of the etched amorphous silicon film is the largest.
  • the etching solution used in the above wet etching process may be a hydrogen fluoride solution.
  • Part of the surface layer with relatively small ions per unit volume in the above-mentioned amorphous silicon film 301 may refer to the doped particles per unit volume in the amorphous silicon film 301 in the direction from the third surface to the fourth surface in the amorphous silicon film 301. Part of the amorphous silicon film where the number of ions gradually increases.
  • the etching thickness of the wet etching process is related to the implantation energy of the ion implantation process. Generally, the greater the energy of ion implantation, the greater the depth of ion implantation, correspondingly, the greater the etching thickness of the wet etching process, so as to ensure that the ions in the unit volume of the amorphous silicon film 301 can be The smaller part of the surface layer of 201X is etched away.
  • the etching thickness of the wet etching process may be greater than or equal to 220 angstroms and less than or equal to 330 angstroms.
  • Step 404 forming a source and a drain on the side of the etched amorphous silicon film away from the substrate.
  • a patterning process is performed on the etched amorphous silicon film to obtain a patterned amorphous silicon film.
  • the orthographic projection of the patterned amorphous silicon thin film on the substrate can cover the orthographic projection of the gate on the substrate.
  • a metal thin film can be formed on the side of the patterned amorphous silicon thin film away from the base substrate 21 .
  • the metal thin film can cover the base substrate 21 in its entirety.
  • a patterning process is performed on the metal thin film to obtain the source electrode 202 and the drain electrode 203 .
  • FIG. 13 is a schematic structural diagram of another substrate substrate at the end of step 404 .
  • the source electrode 202 and the drain electrode 203 are formed on the etched amorphous silicon film 302 .
  • the orthographic projection of the source electrode 202 on the base substrate 21 and the orthographic projection of the etched amorphous silicon thin film 302 on the base substrate 20 have overlapping regions.
  • the orthographic projection of the drain electrode 105 on the base substrate 20 and the orthographic projection of the etched amorphous silicon film 302 on the base substrate 20 have overlapping regions.
  • Step 405 performing a patterning process on the etched amorphous silicon film to obtain an amorphous silicon semiconductor layer.
  • performing a patterning process on the etched amorphous silicon film may include: using the source electrode 202 and the drain electrode 203 as a mask, using an etching process to process the groove of the amorphous silicon film.
  • the surface layer of the area where the channel is located is etched to etch away the part of the surface layer doped with ions to obtain the amorphous silicon semiconductor layer (201a and 201b).
  • the finally formed amorphous silicon semiconductor layer 201 includes a source contact region 2011, a drain contact region 2012, and a channel region 2013 between the source contact region 2011 and the drain contact region 2012, the source contact Both the region 2011 and the drain contact region 2012 are doped with ions 201X, and the channel region 2013 is not doped with ions.
  • the source contact region 2011 is in contact with the source 202
  • the drain contact region 2012 is in contact with the drain 203 .
  • the etching thickness of the etching process in the above one patterning process may be greater than or equal to 500 angstroms. In this way, it can be ensured that the channel region of the amorphous silicon semiconductor layer 201 obtained by etching is not doped with ions or has a low ion concentration, so that the leakage current of the amorphous silicon thin film transistor is small, thereby having a small off-state current .
  • the manufacturing process of the amorphous silicon thin film transistor can be simplified.
  • the embodiment of the present application provides a method for manufacturing an amorphous silicon thin film transistor.
  • the region near the source and drain of the amorphous silicon semiconductor layer of the amorphous silicon thin film transistor prepared by the method contains Ions are doped by an ion implantation process, and the concentration of ions in the surface region of the amorphous silicon semiconductor layer close to the source and drain is greater than or equal to 5 ⁇ 10 20 atoms/cc.
  • the display panel 02 may include: a base substrate 21, and a plurality of amorphous silicon thin films provided on the base substrate 21 as provided in the above-mentioned embodiments Transistor 20 ( FIG. 3 shows an amorphous silicon thin film transistor 20 ), and the base substrate 21 may be equipped with amorphous silicon thin film transistor 20 and low temperature polysilicon thin film crystal at the same time.
  • the amorphous silicon thin film transistor 20 may be the amorphous silicon thin film transistor 20 shown in FIG. 3 or FIG. 5 .
  • the base substrate has a display area and a peripheral area, and the amorphous silicon thin film transistor can be located in the display area;
  • the display panel can also include: a plurality of low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) thin film transistors located in the peripheral area.
  • LTPS Low Temperature Poly-Silicon
  • the amorphous silicon thin film transistor and the low-temperature polysilicon thin film transistor can be prepared on the same production line by ion implantation.
  • the embodiment of the present application also provides a display device.
  • the display device may include a power supply component and the display panel as provided in the above embodiments.
  • the power supply component is used to supply power to the display panel.
  • the display device may be a liquid crystal display device, an organic light-emitting diode (organic light-emitting diode, OLED) display device (such as an active-matrix organic light-emitting diode (AMOLED)), Electronic paper, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame or navigator, etc. Any product or component with display function and fingerprint recognition function.
  • OLED organic light-emitting diode
  • AMOLED active-matrix organic light-emitting diode

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Abstract

本申请公开了一种非晶硅薄膜晶体管及其制备方法、显示面板，涉及显示技术领域。该非晶硅薄膜晶体管的非晶硅半导体层中靠近源极和漏极的区域包含有通过离子注入工艺掺杂的离子，且非晶硅半导体层中靠近源极和漏极的表面区域内的离子的浓度大于或等于5×10 20 atoms/cc。由此，可以使得非晶硅半导体层与源极和漏极之间均形成较好的欧姆接触，从而可提高非晶硅薄膜晶体管的开态电流。

Description

非晶硅薄膜晶体管及其制备方法、显示面板 技术领域
本公开涉及显示技术领域，特别涉及一种非晶硅薄膜晶体管及其制备方法、显示面板。
背景技术
薄膜晶体管(thin-film transistor，TFT)作为开关器件在显示面板中发挥着重要的应用。
相关技术中，薄膜晶体管一般包括沿远离衬底基板的方向依次层叠的栅极，栅极绝缘层，有源层以及源漏极层，该源漏极层包括源极和漏极。其中，有源层的材料可以为非晶硅(amorphous silicon，a-Si)。
但是，相关技术中的有源层与源漏极层之间的欧姆接触性能较差。
发明内容
本申请提供了一种非晶硅薄膜晶体管及其制备方法、显示面板，可以解决相关技术中薄膜晶体管的开关特性较差的问题。所述技术方案如下：
一方面，提供了一种非晶硅薄膜晶体管，所述非晶硅薄膜晶体管包括：
依次设置在衬底基板上的非晶硅半导体层，源极以及漏极；
其中，所述非晶硅半导体层中靠近所述源极和漏极的区域包含有通过离子注入工艺掺杂的离子，且所述非晶硅半导体层中靠近所述源极和漏极的表面区域内的所述离子的浓度大于或等于5×10 20离子/立方厘米。
可选的，所述非晶硅半导体层中靠近所述源极和漏极的表面区域的一定深度具有所述通过离子注入工艺掺杂的离子，所述离子的浓度随着距离所述表面区域越远而越小。
可选的，所述非晶硅半导体层中靠近所述源极和漏极的表面区域的一定深度具有所述通过离子注入工艺掺杂的离子，所述离子的浓度随着距离所述表面区域越远先增大后减小；
所述离子的浓度随着距离所述表面区域越远而越大的区域的厚度，小于所 述离子的浓度随着距离所述表面区域越远而越小的区域的厚度。
可选的，所述非晶硅半导体层中靠近所述源极和漏极的表面区域的第一深度处，所述离子的浓度大于或等于3×10 20离子/立方厘米；
所述第一深度在0～50埃之间。
可选的，所述非晶硅半导体层中靠近所述源极和漏极的表面区域的第二深度处，所述离子的浓度大于或等于5×10 20离子/立方厘米；
所述第二深度在0～20埃之间；
所述非晶硅半导体层中靠近所述源极和漏极的表面区域的第三深度处，所述离子的浓度小于或等于5×10 19离子/立方厘米；
所述第三深度在600～1300埃之间；
所述非晶硅半导体层中靠近所述源极和漏极的表面区域的第四深度处，所述离子的浓度小于或等于3×10 19离子/立方厘米；
所述第四深度大于或等于1300埃。
可选的，所述非晶硅半导体层包括源极接触区域，漏极接触区域，以及位于所述源极接触区域和所述漏极接触区域之间的沟道区域；
所述离子分布在所述源极接触区域和所述漏极接触区域。
可选的，所述源极接触区域和漏极接触区域靠近所述衬底基板的区域掺杂所述离子的浓度小于或者等于3×10 19离子/立方厘米。
可选的，所述沟道区域的掺杂所述离子的浓度小于或者等于3×10 19离子/立方厘米；
所述沟道区域和所述源极接触区域和漏极接触区域靠近所述衬底基板的区域厚度在500～1000埃之间。
可选的，所述离子包括磷离子。
可选的，所述非晶硅半导体层包括沿远离所述衬底基板一侧层叠设置的第一非晶硅半导体层和第二非晶硅半导体层；
其中，所述第一非晶硅半导体层的厚度小于所述第二非晶硅半导体层的厚度，所述第一半导体层的致密度大于所述第二半导体层的致密度。
可选的，所述第一非晶硅半导体层的厚度与所述第二非晶硅半导体层的厚度的比值范围为0.1至0.5。
可选的，所述非晶硅半导体层是对非晶硅薄膜先后进行离子注入、湿法刻蚀和一次构图工艺得到的。
另一方面，提供了一种非晶硅薄膜晶体管的制备方法，所述方法包括：
在衬底基板上依次形成非晶硅半导体层，源极以及漏极；
形成所述源极和所述漏极之前，所述形成非晶硅半导体层，包括：
在所述衬底基板上依次沉积未图案化的非晶硅薄膜和缓冲层，所述缓冲层的材料为硅的氧化物、硅的氮化物或硅的氮氧化物；
采用离子注入工艺在所述缓冲层远离所述衬底基板一侧的表面注入离子，所述离子由所述缓冲层扩散到所述非晶硅薄膜层；
采用湿法刻蚀工艺，对掺杂有所述离子的缓冲层，以及掺杂有所述离子的非晶硅薄膜进行刻蚀，得到非晶硅半导体层，所述非晶硅半导体层中靠近所述源极和漏极的表面区域内的所述离子的浓度大于或等于5×10 20离子/立方厘米。
可选的，所述采用湿法刻蚀工艺，对掺杂有所述离子的缓冲层，以及掺杂有所述离子的非晶硅薄膜进行刻蚀，得到非晶硅半导体层，包括：
采用湿法刻蚀工艺，完全刻蚀掉有源层区域之外的缓冲层和非晶硅薄膜；
采用湿法刻蚀工艺，完全刻蚀掉所述有源层区域的缓冲层，并保留注入有所述离子的非晶硅薄膜；
对保留的所述非晶硅薄膜中，位于源极接触区域和漏极接触区域之间的沟道区域进行刻蚀，并保留所述沟道区域中离子的浓度小于或等于3×10 19离子/立方厘米的部分。
可选的，所述缓冲层的厚度小于所述非晶硅薄膜的厚度。
可选的，所述缓冲层的厚度在200～300埃之间；
所述非晶硅薄膜的厚度在1400～2000埃之间；
所述湿法刻蚀工艺的刻蚀厚度在20～30埃之间。
可选的，所述湿法刻蚀工艺中采用的刻蚀溶液为酸性刻蚀液。
可选的，所述对保留的所述非晶硅薄膜中，位于源极接触区域和漏极接触区域之间的沟道区域进行刻蚀的刻蚀厚度大于或等于500埃。
可选的，所述离子注入工艺中采用的气氛包括磷化氢，离子剂量大于或等于e 15个/平方厘米，加速电压大于或等于20千伏且小于或等于30千伏。
可选的，所述在衬底基板上形成非晶硅薄膜包括：
按照第一膜层沉积速率在所述衬底基板上沉积第一非晶硅薄膜；
按照第二膜层沉积速率在所述第一非晶硅薄膜远离所述衬底基板的一侧沉积第二非晶硅半导体薄膜；
其中，所述第一膜层沉积速率在4～8埃/秒之间；
所述第二膜层沉积速率在30～50埃/秒之间。
又一方面，提供了一种显示面板，所述显示面板包括：衬底基板，以及位于所述衬底基板上的多个如上述方面所述的非晶硅薄膜晶体管；所述衬底基板上同时具备所述非晶硅薄膜晶体管以及低温多晶硅薄膜晶体。
本申请提供的技术方案带来的有益效果至少包括：
本申请提供了一种非晶硅薄膜晶体管，该非晶硅薄膜晶体管的非晶硅半导体层中靠近源极和漏极的区域包含有通过离子注入工艺掺杂的离子，且非晶硅半导体层中靠近源极和漏极的表面区域内的离子的浓度大于或等于5×10 20atoms/cc。由此，可以使得非晶硅半导体层与源极和漏极之间均形成较好的欧姆接触，从而可提高非晶硅薄膜晶体管的开态电流。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是一种采用非晶硅薄膜晶体管的显示面板的结构示意图；
图2是一种非晶硅半导体层中掺杂离子的浓度随注入深度分布情况示意图；
图3是本申请实施例提供的一种采用非晶硅薄膜晶体管的显示面板的结构示意图；
图4是本申请实施例提供的另一种采用非晶硅薄膜晶体管显示面板的结构示意图；
图5是本申请实施例示出的另一种采用非晶硅薄膜晶体管显示面板的结构示意图；
图6是本申请实施例提供的另一种非晶硅薄膜晶体管的制备方法的流程图；
图7是本申请实施提供的一种衬底基板的结构示意图；
图8是本申请实施例提供的缓冲层和非晶硅薄膜中的离子浓度随深度的变化关系；
图9是本申请实施例提供的非晶硅半导体层中的离子浓度随深度的变化关系；
图10是本申请实施例制备的非晶硅薄膜晶体管和相关技术制备的非晶硅薄膜晶体管的开关特性对比图；
图11是本申请实施例提供的一种非晶硅薄膜晶体管的制备方法的流程图；
图12是本申请实施提供的另一种衬底基板的结构示意图；
图13是本申请实施提供的另一种衬底基板的结构示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述。
如图1所示，图1是一种采用非晶硅薄膜晶体管的显示面板的结构示意图。参考图1可以看出，该显示面板01中的非晶硅薄膜晶体管10可以包括：依次设置在衬底基板(substrate)11上的栅极(gate)101，栅极绝缘层(gate insulator，GI)102，非晶硅半导体层103，源极(source)104和漏极(drain)105。其中，非晶硅半导体层中掺杂有离子。该N型掺杂非晶硅半导体层103一般可以通过在化学气象沉积(chemical vapor deposition，CVD)非晶硅半导体材料的过程中均匀地掺杂磷化氢(PH 3)气体形成。通过在非晶硅半导体层103中掺杂离子，可以使得非晶硅半导体层103和源极104以及漏极105之间实现良好的欧姆接触。由此，可以确保该非晶硅薄膜晶体管具有较高的开启电流和较小的关闭电流，即该非晶硅薄膜晶体管的开关特性较好。
低温多晶硅(low temperature poly-silicon，LTPS)薄膜晶体管的生产产线通常是利用离子注入工艺在半导体中掺杂离子。离子注入工艺是将加速到一定高能量的离子束注入半导体材料表面层内，以改变表面层物理和化学性质的工艺，例如，在硅中注入硼、磷或砷，可以改变硅表面的电导率。通过离子注入工艺可以较精确的控制离子注入的深度和浓度。基于此，可以利用低温多晶硅薄膜晶体管的产线设备，开发新的非晶硅薄膜晶体管制备工艺，生产出由离子注入工艺掺杂的非晶硅薄膜晶体管器件，有利于产线产品多元化和工艺整合。
一般情况下，低温多晶硅薄膜晶体管的生产产线上的沉积设备没有设置掺杂气体管路。图2是一种非晶硅半导体层中掺杂离子的浓度随注入深度分布情况示意图。其中，横坐标为非晶硅半导体层中掺杂离子的浓度，其单位为原子/立方厘米(atoms/cc)，纵坐标为非晶硅半导体层的深度，其单位为埃
Figure PCTCN2021121965-appb-000001
非 晶硅半导体层中掺杂离子的浓度可以是通过检测设备检测得到的。该检测设备可以是透射电子显微镜或二次离子质谱(secondary ion mass spectroscopy，SIMS)分析仪等。
请参考图2，通过离子注入工艺将掺杂离子注入到非晶硅半导体层中，掺杂离子在非晶硅半导体层的厚度方向上的分布近似正态分布。导致非晶硅半导体层靠近源级和漏极的一侧的表层的掺杂离子浓度较低，非晶硅半导体层与源漏极层之间的欧姆接触性能较差，从而导致薄膜晶体管的开关特性较差。示例性的，通过上述离子注入工艺制备的非晶硅薄膜晶体管的开关电流比较小(例如，开关电流比小于10 5)。进而无法将低温多晶硅薄膜晶体管和非晶硅薄膜晶体管的制备工艺整合到同一条生产产线上。
上述部分和全部的技术问题通过本申请下述的有限的实施例可以优化。
本申请实施例提供的非晶硅薄膜晶体管可以用于显示面板的显示区域。
本申请实施例提供的非晶硅薄膜晶体管可以应用于小尺寸移动设备(Mobile)、笔记本电脑(notebook，NB)，平板电脑(iPAD)，中小尺寸的监视器(monitor，MNT)，中大尺寸的电视机(television，TV)以及中大尺寸的MNT等产品。
本申请实施例提供的非晶硅薄膜晶体管可以用于显示领域或芯片领域，显示领域可以是液晶(liquid crystal display，LCD)显示面板，有机发光二极管OLED(organic light-emitting diode，OLED)显示面板，量子点发光二极管(quantum dot light emitting diodes，QLED)显示面板，微型发光二极管显示面板(micro light emitting diode，Micro LED)以及传感等技术领域中。其中，本申请实施例提供的非晶硅薄膜晶体管可以作为像素中的开关薄膜晶体管。
图3是本申请实施例提供的一种采用非晶硅薄膜晶体管的显示面板的结构示意图。参考图3可以看出，该显示面板02中的非晶硅薄膜晶体管20可以包括：依次设置在衬底基板21上的非晶硅半导体层201，源极202以及漏极203。
参考图3，源极202和漏极203位于同层，可以采用同一次构图工艺制备得到。其中，源极202和漏极203均与非晶硅半导体层201电连接。
其中，非晶硅半导体层201中靠近源极202和漏极203的区域包含有通过离子注入工艺掺杂的离子201X，且非晶硅半导体层201中靠近源极202和漏极203的表面区域内的离子的浓度大于或等于5×10 20离子每立方厘米 (atoms/cc)。
由于在非晶硅半导体层201的表面区域内单位体积内掺杂的离子201X的浓度较高(即单位体积内的离子的数量较高)。因此，可以使得非晶硅半导体层201与源级202和漏级203均能实现较好的欧姆接触，进而可以使得非晶硅薄膜晶体管20具有较大的开态电流。
综上所述，本申请实施例提供了一种非晶硅薄膜晶体管，该非晶硅半导体层中靠近源极和漏极的区域包含有通过离子注入工艺掺杂的离子，且非晶硅半导体层中靠近源极和漏极的表面区域内的离子的浓度大于或等于5×10 20atoms/cc。由此，可以使得非晶硅半导体层与源极和漏极之间均形成较好的欧姆接触，从而可提高非晶硅薄膜晶体管的开态电流。
可选的，请参考图3，非晶硅半导体201中靠近源极202和漏极203的表面区域的一定深度具有通过离子注入工艺掺杂的离子201X，离子201X的浓度随着距离表面区域越远而越小。在本申请实施例中，在非晶硅半导体层201的远离源极202和漏极203的区域中，非晶硅半导体层201中单位体积内掺杂的离子201X的数量较小甚至可以为零。如此，可以使得非晶硅半导体层201远离源级202和漏级203的部分的漏电流较小，可以降低非晶硅薄膜晶体管20的关态电流。基于上述分析可知，本申请实施例提供的非晶硅薄膜晶体管具有较高的开关电流比，其开关特性较好。
在一种可选的实施方式中，非晶硅半导体层201中靠近源极202和漏极203的表面区域的一定深度具有通过离子注入工艺掺杂的离子201X，离子201X的浓度随着距离表面区域越远可以先增大后减小。离子201X的浓度随着距离表面区域越远而越大的区域的厚度，小于离子201X的浓度随着距离表面区域越远而越小的区域的厚度。如此，在非晶硅半导体层201的远离源极202和漏极203的区域中，非晶硅半导体层201中单位体积内掺杂的离子201X的数量较小甚至可以为零。可以使得非晶硅半导体层201远离源级202和漏级203的部分的漏电流较小，可以降低非晶硅薄膜晶体管20的关态电流。基于上述分析可知，本申请实施例提供的非晶硅薄膜晶体管具有较高的开关电流比，其开关特性较好。
可选的，非晶硅半导体层201中靠近源极202和漏极203的表面区域的第一深度处，离子201X的浓度大于或等于3×10 20atoms/cc。第一深度在0～50埃之间。可以使得非晶硅半导体层与源极和漏极之间均形成较好的欧姆接触，从而可提高非晶硅薄膜晶体管的开态电流。
可选的，本申请实施例中是非晶硅半导体层201中，非晶硅半导体层201中靠近源极201和漏极203的表面区域的第二深度处，离子201X的浓度大于或等于5×10 20atoms/cc。第二深度在0～20埃之间。
非晶硅半导体层201中靠近源极202和漏极203的表面区域的第三深度处，离子201X的浓度小于或等于5×10 19atoms/cc；第三深度在600～1300埃之间。
非晶硅半导体层201中靠近源极202和漏极203的表面区域的第四深度处，离子201X的浓度小于或等于3×10 19atoms/cc；第四深度大于或等于1300埃。
可选的，如图4所示，图4是本申请实施例提供的另一种采用非晶硅薄膜晶体管的显示面板的结构示意图。非晶硅半导体层201包括源极接触区域2011，漏极接触区域2012，以及位于源极接触区域2011和漏极接触区域2012之间的沟道区域2013。其中，源极接触区域2011与源极202电连接，漏极接触区域2012与漏极203电连接，沟道区域2013分别与源极202和漏级203之间不存在直接接触。
源极接触区域2011和漏极接触区域2012中均掺杂有离子201X，沟道区域2013中可以掺杂极少的离子201X。如此，可以使得沟道区域2013中的漏电流较小，进而使得非晶硅薄膜晶体管中的漏电流较小。
可选的，源极接触区域2011和漏极接触区域2012靠近衬底基板21的区域掺杂离子201X的浓度小于或者等于3×10 19atoms/cc。如此，可以使得源极接触区域2011和漏极接触区域2012靠近衬底基板21的区域中的漏电流较小，从而使得非晶硅薄膜晶体管中的漏电流较小。
可选的，沟道区域2013的掺杂离子201X的浓度小于或者等于3×10 19atoms/cc。沟道区域2013和源极接触区域2011和漏极接触区2012域靠近衬底基板21的区域厚度D1在500～1000埃之间。基于此，一方面，沟道区域2013的厚度较小可以保证沟道区域2013中单位体积内掺杂的离子201X的数量较小，以使得沟道区域2013中的漏电流较小；另一方面，可以避免在对沟道区域2013远离衬底基板21的一侧进行图案化工艺时，过刻而导致的沟道区域2013较薄，影响非晶硅薄膜晶体管的性能。
请参考图4，源极接触区域2011和漏极接触区域2012的厚度D2相等，可以使得源极接触区域2011和漏极接触区域2012的导电特性基本相同，进而可以使得非晶硅薄膜晶体管的性能较稳定。
并且，源极接触区域2011和漏极接触区域2012的厚度与沟道区域2013的 厚度的差值可以大于或等于500埃。由于通常情况下，源极接触区域2011和漏极接触区域2012在垂直于衬底基板21的厚度方向上的离子201X掺杂浓度较大的部分的深度可以为小于或者等于500埃。因此，源极接触区域2011和漏极接触区域2012的厚度与沟道区域2013的厚度的差值大于或等于500埃，可以使得源极接触区域2011和漏极接触区域2012中具有离子201X，同时，可以避免沟道区域2013中具有离子201X。从而可以在源极接触区域2011与源极202，漏级接触区域2012与漏级203实现较好的欧姆接触的同时，减少沟道2013中的漏电流。如此，可以提高非晶硅薄膜晶体管的开关特性。
可选的，离子201X包括磷离子。通过在非晶硅半导体层201中的源极接触区域2011和漏极接触区域2012掺杂磷离子(P +)，使得源极202和漏极203与非晶硅半导体层201之间形成较好的欧姆接触，在开态的时候有利于提高开态电流，提高非晶硅薄膜晶体管的导电能力。
可选的，如图5所示，图5是本申请实施例示出的另一种采用非晶硅薄膜晶体管的显示面板的结构示意图。非晶硅半导体层包括沿远离衬底基板21一侧层叠设置的第一非晶硅半导体层201a和第二非晶硅半导体层201b。其中，第一非晶硅半导体层201a的厚度小于第二非晶硅半导体层201b的厚度，且形成第一非晶硅半导体层201a时的膜层沉积速率，小于形成第二非晶硅半导体层201b时的膜层沉积速率。其中，膜层的致密度可以与膜层沉积速率负相关。也即是，膜层沉积速率越大，膜层的致密度越小；膜层沉积速率越小，膜层的致密度越大。由此，第二非晶硅半导体层201b的膜层沉积速率可以大于第一非晶硅半导体层201a的膜层沉积速率，以使得第一非晶硅半导体层201a的致密度大于第二非晶硅半导体层201b。
在形成厚度较薄的第一非晶硅半导体层201a时，通过采用较小的膜层沉积速率，可以使得第一非晶硅半导体层201a的致密度较大，缺陷较少，并且使得第一非晶硅半导体层201a与栅极绝缘层205之间更加贴合，由此可以确保非晶硅薄膜晶体管的性能。而在形成厚度较厚的第二非晶硅半导体层201b时，可以适当加快膜层沉积速率，以提高非晶硅半导体层201的制备效率。
可选的，第一非晶硅半导体层201a的厚度与第二非晶硅半导体层201b的厚度的比值范围为0.1至0.5。在此范围内，可以在保证非晶硅半导体层201的性能的基础上，有效提升非晶硅半导体层201的制备效率。
可选的，非晶硅半导体层是对非晶硅薄膜先后进行离子注入、湿法刻蚀和 一次构图工艺得到的。其中，在进行离子注入时，可以通过控制离子注入的能量和剂量，实现对非晶硅半导体层中注入的离子的深度和数量的精确控制。其中，离子注入的能量可以决定非晶硅半导体层中离子的注入深度，离子剂量可以决定非晶硅半导体层中注入的离子的数量。需要说明的是，离子注入的能量和剂量可以根据实际生产的需要设置相应的参数，本申请实施例在此不做限制。
采用湿法刻蚀工艺可以较为精准的控制对非晶硅薄膜的刻蚀厚度，进而可以使得对非晶硅薄膜的刻蚀程度较为均一，以确保制备得到的非晶硅薄膜晶体管的稳定性。
一次构图工艺可以实现对非晶硅薄膜的图案化处理，以形成具有源极接触区域，漏极接触区域和沟道区域的非晶硅半导体层。
如图5所示，非晶硅薄膜晶体管20还包括位于非晶硅半导体层201靠近衬底基板21一侧，且在衬底基板21上依次层叠的栅极204和栅极绝缘层205。该栅极绝缘层205的材料可以包括二氧化硅(SiO 2)、氮化硅(Si 3N 4)或者二氧化硅和氮化硅的混合材料。需要说明的是，图5示出了底栅结构的非晶硅薄膜晶体管，本申请实施例中的非晶硅薄膜晶体管也可以为顶栅结构，本申请实施例对比不做限制。
综上所述，本申请实施例提供了一种非晶硅薄膜晶体管，该非晶硅薄膜晶体管的非晶硅半导体层中靠近源极和漏极的区域包含有通过离子注入工艺掺杂的离子，且非晶硅半导体层中靠近源极和漏极的表面区域内的离子的浓度大于或等于5×10 20atoms/cc。由此，可以使得非晶硅半导体层与源极和漏极之间均形成较好的欧姆接触，从而可提高非晶硅薄膜晶体管的开态电流。
本申请实施例提供的一种非晶硅薄膜晶体管的制备方法，该方法可以用于制备图3所示的非晶硅薄膜晶体管20。该方法可以包括：在衬底基板21上依次形成非晶硅半导体层201，源极202以及漏极203。
其中，形成源极202和漏极203之前，形成非晶硅半导体层201，包括：
在衬底基板21上依次沉积未图案化的非晶硅薄膜和缓冲层，缓冲层的材料为硅的氧化物、硅的氮化物或硅的氮氧化物。
采用离子注入工艺在缓冲层远离衬底基板一侧的表面注入离子，离子由缓冲层扩散到非晶硅薄膜层。
采用湿法刻蚀工艺，对掺杂有离子的缓冲层，以及掺杂有离子的非晶硅薄 膜进行刻蚀，得到非晶硅半导体层201，非晶硅半导体层201中靠近源极202和漏极203的表面区域内的离子201X的浓度大于或等于5×10 20atoms/cc。
如此，可以降低源极202和漏极203与非晶硅半导体层201之间的接触电阻。可以使得非晶硅半导体层201与源级202和漏级203均能实现较好的欧姆接触，进而可以使得非晶硅薄膜晶体管20具有较大的开态电流。从而使得非晶硅薄膜晶体管20具有较高的开关电流比。
综上所述，本申请实施例提供了一种非晶硅薄膜晶体管的制备方法，该方法制备得到的非晶硅薄膜晶体管的非晶硅半导体层中靠近源极和漏极的区域包含有通过离子注入工艺掺杂的离子，且非晶硅半导体层中靠近源极和漏极的表面区域内的离子的浓度大于或等于5×10 20atoms/cc。由此，可以使得非晶硅半导体层与源极和漏极之间均形成较好的欧姆接触，从而可提高非晶硅薄膜晶体管的开态电流。
图6是本申请实施例提供的另一种非晶硅薄膜晶体管的制备方法的流程图。该方法可以上述实施例所提供的非晶硅薄膜晶体管，例如用于制备图3所示的非晶硅薄膜晶体管。参考图6，该方法可以包括：
步骤501、在衬底基板上依次沉积未图案化的非晶硅薄膜和缓冲层。
其中，缓冲层的材料可以为硅的氧化物、硅的氮化物或硅的氮氧化物。
在本申请实施例中，可以先获取一衬底基板21，并依次在衬底基板21的一侧按照第一膜层沉积速率在衬底基板上沉积第一非晶硅子薄膜；按照第二膜层沉积速率在第一非晶硅子薄膜远离衬底基板的一侧沉积第二非晶硅半导体子薄膜。从而在衬底基板21上形成非晶硅薄膜。并且，该非晶硅薄膜可以整层覆盖该衬底基板21。
其中，第二膜层沉积速率可以大于第一膜层沉积速率，例如，该第一膜层沉积速率可以4～8埃/秒之间；第二膜层沉积速率可以在30～50埃/秒之间。
可选的，该非晶硅薄膜的厚度可以大于或等于1600埃且小于或等于2300埃。其中，第一非晶硅子薄膜的厚度可以大于或等于300埃且小于或等于600埃，第二非晶硅子薄膜的厚度可以大于或等于1300埃且小于或等于1700埃。
该衬底基板21的材质可以包括玻璃或者聚酰亚胺等。
其中，该缓冲层的厚度可以小于非晶硅薄膜的厚度。例如，非晶硅薄膜的厚度可以在1400～2000埃之间；缓冲层的厚度可以在200～300埃之间。
步骤502、采用离子注入工艺在缓冲层远离衬底基板一侧的表面注入离子，离子由缓冲层扩散到非晶硅薄膜层。
在本申请实施例中，离子注入工艺中采用的气氛可以包括磷化氢，该磷化氢中的磷离子可以注入至缓冲层和非晶硅薄膜。离子注入工艺中，离子剂量可以大于或等于e 15个/平方厘米，加速电压可以大于或等于20千伏且小于或等于30千伏。
请参考图7，图7是步骤502结束时，一种衬底基板的结构示意图，通过离子注入工艺掺杂有离子201X的缓冲层601和非晶硅薄膜602形成于衬底基板21上。
应理解的是，在本申请实施例中，该缓冲层所采用的材料是与非晶硅具有相似的离子穿透性的材料。例如，该缓冲层的材料可以至少可以包括氧化硅。或者，缓冲层的材料还可以包括氮化硅。
基于此，在通过离子注入工艺在缓冲层和非晶硅薄膜中掺杂离子后，如图8所示，图8是步骤502结束后，缓冲层和非晶硅薄膜中的离子浓度随深度的变化关系。其中，横坐标为深度，其单位为埃
Figure PCTCN2021121965-appb-000002
纵坐标为离子浓度，其单位为原子/立方厘米(atoms/cc)。离子在缓冲层和非晶硅薄膜的厚度方向上的分布近似正态分布。又由于该缓冲层的厚度较小，因此注入至缓冲层的离子的浓度在缓冲层的厚度方向上逐渐增大，注入至非晶硅薄膜的离子的浓度在非晶硅薄膜的厚度方向上先逐渐增大，后逐渐减小。
还应理解的是，由于离子注入的深度与离子注入的能量相关，因此上述步骤501中形成的缓冲层的厚度可以是基于离子注入的能量确定的，以确保离子注入缓冲层和非晶硅薄膜后，缓冲层中的离子浓度在缓冲层的厚度方向上逐渐增大，非晶硅薄膜中的离子的浓度在非晶硅薄膜的厚度方向上先逐渐增大，后逐渐减小，即确保离子浓度最大的部分位于非晶硅薄膜中。
步骤503、采用湿法刻蚀工艺，对掺杂有离子的缓冲层，以及掺杂有离子的非晶硅薄膜进行刻蚀，得到非晶硅半导体层。
其中，非晶硅半导体层中靠近源极和漏极的表面区域内的离子的浓度大于或等于5×10 20atoms/cc。
步骤503可以包括以下三个步骤5031、5032和5033：
5031、采用湿法刻蚀工艺，完全刻蚀掉有源层区域之外的缓冲层和非晶硅薄膜。
有源层区域可以指非晶硅薄膜中待形成非晶硅半导体层的区域。
5032、采用湿法刻蚀工艺，完全刻蚀掉有源层区域的缓冲层，并保留注入有离子的非晶硅薄膜。
即将有源层区域上的缓冲层全部刻蚀掉。保留注入有离子的非晶硅薄膜可以理解为，对注入有离子的非晶硅薄膜不进行刻蚀或者只刻蚀一部分。在对对注入有离子的非晶硅薄膜只刻蚀一部分时，湿法刻蚀工艺的刻蚀厚度在20～30埃之间。
请参考图7和图8，可以理解为：缓冲层601具有背离衬底基板21的第五表面，非晶硅薄膜602具有靠近衬底基板21的第六表面。从第五表面到第六表面的方向上，缓冲层601和非晶硅薄602中单位体积内掺杂的离子的数量先逐渐增大，后逐渐减小。
在本申请实施例中，为了使得最终形成的非晶硅半导体层与源极和漏极之间形成较好的欧姆接触，可以采用湿法刻蚀工艺将缓冲层601以及非晶硅薄膜602中单位体积内离子201X较小的部分表层刻蚀掉，使得刻蚀后的非晶硅薄膜在远离衬底基板21的一侧上的单位体积内离子201X的数量最大。上述湿法刻蚀工艺中采用的刻蚀溶液可以为酸性刻蚀液，进一步的，可以为氟化氢溶液。
上述缓冲层601和非晶硅薄602中单位体积内离子较小的部分，可以指在缓冲层601和非晶硅薄602中从第五表面到第六表面的方向上，缓冲层601和非晶硅薄602中单位体积内掺杂的离子的数量逐渐增大的膜层。
需要说明的是，该湿法刻蚀工艺的刻蚀厚度与离子注入工艺的注入能量相关。通常情况下，离子注入的能量越大，离子注入的深度就越大，相应的，该湿法刻蚀工艺的刻蚀厚度就越大，以确保能够将全部的缓冲层601以及非晶硅薄膜602中单位体积内离子201X较小的部分膜层均刻蚀掉。例如，湿法刻蚀工艺中采用的刻蚀溶液为氟化氢溶液。湿法刻蚀工艺的刻蚀厚度大于或等于220埃且小于或等于330埃。其中，对掺杂有离子的非晶硅薄膜602远离衬底基板的一侧进行湿法刻蚀工艺的刻蚀厚度大于或等于20埃且小于或等于30埃。
若湿法刻蚀工艺中采用的刻蚀溶液为氟化氢溶液，则氟化氢溶液对缓冲层601的刻蚀速率与对非晶硅薄膜602的刻蚀速率的比值大于或者等于10。例如，氟化氢对缓冲层601的刻蚀速率的范围在5埃/秒至20埃/秒的范围内。采用氟化氢对非晶硅薄膜602的刻蚀速率的范围在0.5埃/秒至2埃/秒的范围内。
由于氟化氢溶液对缓冲层601的刻蚀速率远大于对非晶硅薄膜602的刻蚀 速率，因此一方面可以提高非晶硅薄膜晶体管的制备效率，另一方面，可以根据缓冲层601和非晶硅薄膜602的刻蚀速率的比值，较精确的控制缓冲层601和非晶硅薄膜602的刻蚀厚度。
5033、对保留的非晶硅薄膜中，位于源极接触区域和漏极接触区域之间的沟道区域进行刻蚀，并保留沟道区域中离子的浓度小于或等于3×10 19atoms/cc的部分。
对保留的非晶硅薄膜中，位于源极接触区域和漏极接触区域之间的沟道区域进行刻蚀的刻蚀厚度大于或等于500埃。
可以通过刻蚀沟道区域中离子浓度较大的部分，得到非晶硅半导体层。参考图4，最终形成的非晶硅半导体层201包括源极接触区域2011，漏极接触区域2012，以及位于源极接触区域2011和漏极接触区域2012之间的沟道区域2013，源极接触区域2011和漏极接触区域2012中均掺杂有离子201X，沟道区域2013中掺杂离子201X的浓度较小。
步骤504、在刻蚀后的非晶硅薄膜远离衬底基板的一侧形成源极和漏极。
可以在刻蚀后的非晶硅薄膜远离衬底基板21的一侧形成金属薄膜。该金属薄膜可以整层覆盖该衬底基板21。之后，对金属薄膜进行一次构图工艺，得到源极202和漏极203。其中，源极接触区域2011与源极202接触，漏极接触区域2012与漏极203接触。步骤504结束时，衬底基板的结构也可以参考图9。
图9是本申请实施例提供的非晶硅半导体层中的离子浓度随深度的变化关系。请参考图9，其中，横坐标为深度，其单位为埃
Figure PCTCN2021121965-appb-000003
纵坐标为离子浓度，其单位为原子/立方厘米(atoms/cc)。本申请实施例中得到的非晶硅半导体层201，非晶硅半导体层201中靠近源极202和漏极203的表面区域内的离子201X的浓度大于或等于5×10 20atoms/cc。
如此，可以降低源极202和漏极203与非晶硅半导体层201之间的接触电阻。可以使得非晶硅半导体层201与源级202和漏级203均能实现较好的欧姆接触，进而可以使得非晶硅薄膜晶体管20具有较大的开态电流。并且，可以使得源极接触区域2011和漏极接触区域2012靠近衬底基板21的区域中的漏电流较小，从而使得非晶硅薄膜晶体管中的漏电流较小。从而使得非晶硅薄膜晶体管20具有较高的开关电流比。
如图10所示，图10是本申请实施例制备的非晶硅薄膜晶体管和相关技术制备的非晶硅薄膜晶体管的开关特性对比图。其中，横坐标为电压，其单位为 伏特(V)，纵坐标为电流，其单位为安培(A)。图13中的曲线C1为本申请实施例中的非晶硅薄膜晶体管的漏极电流随栅极电压变化的曲线。曲线C2为相关技术中使用沉积掺杂制备的非晶硅薄膜晶体管的漏极电流随栅极电压变化的曲线，曲线C3为使用离子注入工艺且不对非晶硅半导体层进行刻蚀的非晶硅薄膜晶体管的漏极电流随栅极电压变化的曲线。
从图10可以看出，在非晶硅薄膜晶体管的栅极电压为正，非晶硅薄膜晶体管处于开启状态时，本申请实施例制备的非晶硅薄膜晶体管相较于相关技术制备的非晶硅薄膜晶体管具有较大的开态电流。在非晶硅薄膜晶体管的栅极电压为负，非晶硅薄膜晶体管处于关闭状态时，本申请实施例制备的非晶硅薄膜晶体管相较于相关技术制备的非晶硅薄膜晶体管具有较小的关态电流，即本申请实施例制备的非晶硅薄膜晶体管开关电流比较大。经测试，本申请实施例中的非晶硅薄膜晶体管开关电流比可以大于或者等于10 6。
综上所述，本申请实施例提供了一种非晶硅薄膜晶体管的制备方法，该方法制备得到的非晶硅薄膜晶体管的非晶硅半导体层中靠近源极和漏极的区域包含有通过离子注入工艺掺杂的离子，且非晶硅半导体层中靠近源极和漏极的表面区域内的离子的浓度大于或等于5×10 20atoms/cc。由此，可以使得非晶硅半导体层与源极和漏极之间均形成较好的欧姆接触，从而可提高非晶硅薄膜晶体管的开态电流。
图11是本申请实施例提供的一种非晶硅薄膜晶体管的制备方法的流程图。该方法可以上述实施例所提供的非晶硅薄膜晶体管，例如用于制备图3所示的非晶硅薄膜晶体管。参考图11，该方法可以包括：
步骤401、在衬底基板上形成非晶硅薄膜。
在本申请实施例中，可以先获取一衬底基板21，并依次在衬底基板21的一侧按照第一膜层沉积速率在衬底基板上沉积第一非晶硅子薄膜；按照第二膜层沉积速率在第一非晶硅子薄膜远离衬底基板的一侧沉积第二非晶硅半导体子薄膜。从而在衬底基板21上形成非晶硅薄膜。并且，该非晶硅薄膜可以整层覆盖该衬底基板21。
其中，第二膜层沉积速率可以大于第一膜层沉积速率，例如，该第一膜层沉积速率可以大于或等于4埃/秒，且小于或等于8埃/秒；第二膜层沉积速率可以大于或等于30埃/秒，且小于或等于50埃/秒。
可选的，该非晶硅薄膜的厚度可以大于或等于1600埃且小于或等于2300埃。其中，第一非晶硅子薄膜的厚度可以大于或等于300埃且小于或等于600埃，第二非晶硅子薄膜的厚度可以大于或等于1300埃且小于或等于1700埃。
该衬底基板21的材质可以包括玻璃或者聚酰亚胺等。
步骤402、采用离子注入工艺在非晶硅薄膜中掺杂离子。
采用离子注入工艺在非晶硅薄膜中掺杂离子201X，可以较为精确的控制非晶硅薄膜中掺杂的离子201X的深度和数量(即浓度)。
其中，离子注入工艺中采用的气氛可以包括磷化氢(PH)，即离子201X可以为磷离子。离子注入工艺中采用的离子剂量可以大于或等于e 15个/平方厘米，加速电压可以大于或等于20千伏且小于或等于30千伏。
在离子注入工艺的过程中，磷化氢中的磷离子可以注入至非晶硅薄膜，注入至非晶硅薄膜中的磷离子可以增加非晶硅薄膜的导电性。
示例的，如图12所示，图12是步骤302结束时，另一种衬底基板的结构示意图，衬底基板21上的非晶硅薄膜301具有通过离子注入工艺掺杂的离子201X。
步骤403、采用湿法刻蚀工艺，对掺杂有离子的非晶硅薄膜远离衬底基板的一侧进行刻蚀。
请参考图12，通过离子注入工艺将离子201X注入到非晶硅薄301中，离子201X在非晶硅薄膜301的厚度方向上的分布近似正态分布。或者，可以理解为：非晶硅薄膜301具有相对的第三表面和第四表面，第三表面为背离衬底基板21的表面，第二表面为靠近衬底基板21的表面，从第三表面到第四表面的方向上，非晶硅薄膜301中单位体积内掺杂的离子的数量先逐渐增大，后逐渐减小。
在本申请实施例中，为了使得最终形成的非晶硅半导体层与源极和漏极之间形成较好的欧姆接触，可以采用湿法刻蚀工艺将非晶硅薄膜301中单位体积内离子201X较小的部分表层刻蚀掉，使得刻蚀后的非晶硅薄膜在远离衬底基板21的一侧上的单位体积内离子201X的数量最大。上述湿法刻蚀工艺中采用的刻蚀溶液可以为氟化氢溶液。
上述非晶硅薄膜301中单位体积内离子较小的部分表层，可以指在非晶硅薄膜301中从第三表面到第四表面的方向上，非晶硅薄膜301中单位体积内掺杂的离子的数量逐渐增大的部分非晶硅薄膜。
需要说明的是，该湿法刻蚀工艺的刻蚀厚度与离子注入工艺的注入能量相关。通常情况下，离子注入的能量越大，离子注入的深度就越大，相应的，该湿法刻蚀工艺的刻蚀厚度就越大，以确保能够将非晶硅薄膜301中单位体积内离子201X较小的部分表层均刻蚀掉。例如，湿法刻蚀工艺的刻蚀厚度可以大于或等于220埃且小于或等于330埃。
步骤404、在刻蚀后的非晶硅薄膜远离衬底基板的一侧形成源极和漏极。
首先，对刻蚀后的非晶硅薄膜进行一次构图工艺，得到图案化的非晶硅薄膜。该图案化的非晶硅薄膜在衬底基板上的正投影可以覆盖栅极在衬底基板上的正投影。
其次，可以在图案化的非晶硅薄膜远离衬底基板21的一侧形成金属薄膜。该金属薄膜可以整层覆盖该衬底基板21。之后，对金属薄膜进行一次构图工艺，得到源极202和漏极203。
示例的，如图13所示，图13是步骤404结束时，另一种衬底基板的结构示意图，源极202和漏极203形成于刻蚀后的非晶硅薄膜302上。
该源极202在衬底基板21上的正投影与刻蚀后的非晶硅薄膜302在衬底基板20上的正投影存在交叠区域。该漏极105在衬底基板20上的正投影与刻蚀后的非晶硅薄膜302在衬底基板20上的正投影存在交叠区域。
步骤405、对刻蚀后的非晶硅薄膜进行一次构图工艺，得到非晶硅半导体层。
请参考图4，本申请实施例中，对刻蚀后的非晶硅薄膜进行一次构图工艺可以包括：以源极202和漏极203为掩膜，采用刻蚀工艺对非晶硅薄膜的沟道所在的区域的表层进行刻蚀，以将掺杂有离子的部分表层刻蚀掉，得到非晶硅半导体层(201a和201b)。参考图4，最终形成的非晶硅半导体层201包括源极接触区域2011，漏极接触区域2012，以及位于源极接触区域2011和漏极接触区域2012之间的沟道区域2013，源极接触区域2011和漏极接触区域2012中均掺杂有离子201X，沟道区域2013中未掺杂离子。其中，源极接触区域2011与源极202接触，漏极接触区域2012与漏极203接触。
其中，上述一次构图工艺中的刻蚀工艺的刻蚀厚度可以大于或等于500埃。如此，可以确保刻蚀得到的非晶硅半导体层201的沟道区域中未掺杂离子或者离子浓度较小，以使得非晶硅薄膜晶体管的漏电流较小，从而具有较小的关态电流。
在上述步骤406中，由于能够以源极202和漏极203为掩膜对刻蚀后的非 晶硅薄膜进行再次刻蚀，因此可以简化非晶硅薄膜晶体管的制造工艺。
综上所述，本申请实施例提供了一种非晶硅薄膜晶体管的制备方法，该方法制备得到的非晶硅薄膜晶体管的非晶硅半导体层中靠近源极和漏极的区域包含有通过离子注入工艺掺杂的离子，且非晶硅半导体层中靠近源极和漏极的表面区域内的离子的浓度大于或等于5×10 20atoms/cc。由此，可以使得非晶硅半导体层与源极和漏极之间均形成较好的欧姆接触，从而可提高非晶硅薄膜晶体管的开态电流。
本申请实施例还提供了一种显示面板，参考图3，该显示面板02可以包括：衬底基板21，以及设置在该衬底基板21的多个如上述实施例所提供的非晶硅薄膜晶体管20(图3示出了一个非晶硅薄膜晶体管20)，且衬底基板21上可以同时具备非晶硅薄膜晶体管20以及低温多晶硅薄膜晶体。其中，该非晶硅薄膜晶体管20可以为图3或图5所示的非晶硅薄膜晶体管20。
可选的，衬底基板具有显示区域和周边区域，非晶硅薄膜晶体管可以位于显示区域；显示面板还可以包括：位于周边区域的多个低温多晶硅(Low Temperature Poly-Silicon，LTPS)薄膜晶体管。
该非晶硅薄膜晶体管和低温多晶硅薄膜晶体管可以在同一条生产线上采用离子注入工艺制备。
本申请实施例还提供了一种显示装置。该显示装置可以包括供电组件以及如上述实施例所提供的显示面板。该供电组件用于为显示面板供电。
可选的，该显示装置可以为液晶显示装置、有机发光二极管(organic light-emitting diode，OLED)显示装置(例如为有源矩阵有机发光二极管(active-matrix organic light-emitting diode，AMOLED))、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能以及指纹识别功能的产品或部件。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (21)

  1. 一种非晶硅薄膜晶体管，其特征在于，包括：
    依次设置在衬底基板上的非晶硅半导体层，源极以及漏极；
    其中，所述非晶硅半导体层中靠近所述源极和漏极的区域包含有通过离子注入工艺掺杂的离子，且所述非晶硅半导体层中靠近所述源极和漏极的表面区域内的所述离子的浓度大于或等于5×10 20离子/立方厘米。
  2. 根据权利要求1所述的非晶硅薄膜晶体管，其特征在于，所述非晶硅半导体层中靠近所述源极和漏极的表面区域的一定深度具有所述通过离子注入工艺掺杂的离子，所述离子的浓度随着距离所述表面区域越远而越小。
  3. 根据权利要求1所述的非晶硅薄膜晶体管，其特征在于，所述非晶硅半导体层中靠近所述源极和漏极的表面区域的一定深度具有所述通过离子注入工艺掺杂的离子，所述离子的浓度随着距离所述表面区域越远先增大后减小；
    所述离子的浓度随着距离所述表面区域越远而越大的区域的厚度，小于所述离子的浓度随着距离所述表面区域越远而越小的区域的厚度。
  4. 根据权利要求2或3任一所述的非晶硅薄膜晶体管，其特征在于，所述非晶硅半导体层中靠近所述源极和漏极的表面区域的第一深度处，所述离子的浓度大于或等于3×10 20离子/立方厘米；
    所述第一深度在0～50埃之间。
  5. 根据权利要求4所述的非晶硅薄膜晶体管，其特征在于，所述非晶硅半导体层中靠近所述源极和漏极的表面区域的第二深度处，所述离子的浓度大于或等于5×10 20离子/立方厘米；
    所述第二深度在0～20埃之间；
    所述非晶硅半导体层中靠近所述源极和漏极的表面区域的第三深度处，所述离子的浓度小于或等于5×10 19离子/立方厘米；
    所述第三深度在600～1300埃之间；
    所述非晶硅半导体层中靠近所述源极和漏极的表面区域的第四深度处，所 述离子的浓度小于或等于3×10 19离子/立方厘米；
    所述第四深度大于或等于1300埃。
  6. 根据权利要求1所述的非晶硅薄膜晶体管，其特征在于，所述非晶硅半导体层包括源极接触区域，漏极接触区域，以及位于所述源极接触区域和所述漏极接触区域之间的沟道区域；
    所述离子分布在所述源极接触区域和所述漏极接触区域。
  7. 根据权利要求6所述的非晶硅薄膜晶体管，其特征在于，所述源极接触区域和漏极接触区域靠近所述衬底基板的区域掺杂所述离子的浓度小于或者等于3×10 19离子/立方厘米。
  8. 根据权利要求6所述的非晶硅薄膜晶体管，其特征在于，所述沟道区域的掺杂所述离子的浓度小于或者等于3×10 19离子/立方厘米；
    所述沟道区域和所述源极接触区域和漏极接触区域靠近所述衬底基板的区域厚度在500～1000埃之间。
  9. 根据权利要求1所述的非晶硅薄膜晶体管，其特征在于，所述离子包括磷离子。
  10. 根据权利要求1所述的非晶硅薄膜晶体管，其特征在于，所述非晶硅半导体层包括沿远离所述衬底基板一侧层叠设置的第一非晶硅半导体层和第二非晶硅半导体层；
    其中，所述第一非晶硅半导体层的厚度小于所述第二非晶硅半导体层的厚度，所述第一半导体层的致密度大于所述第二半导体层的致密度。
  11. 根据权利要求10所述的非晶硅薄膜晶体管，其特征在于，所述第一非晶硅半导体层的厚度与所述第二非晶硅半导体层的厚度的比值范围为0.1至0.5。
  12. 根据权利要求1所述的非晶硅薄膜晶体管，其特征在于，所述非晶硅半 导体层是对非晶硅薄膜先后进行离子注入、湿法刻蚀和一次构图工艺得到的。
  13. 一种非晶硅薄膜晶体管的制备方法，其特征在于，所述方法包括：
    在衬底基板上依次形成非晶硅半导体层，源极以及漏极；
    形成所述源极和所述漏极之前，所述形成非晶硅半导体层，包括：
    在所述衬底基板上依次沉积未图案化的非晶硅薄膜和缓冲层，所述缓冲层的材料为硅的氧化物、硅的氮化物或硅的氮氧化物；
    采用离子注入工艺在所述缓冲层远离所述衬底基板一侧的表面注入离子，所述离子由所述缓冲层扩散到所述非晶硅薄膜层；
    采用湿法刻蚀工艺，对掺杂有所述离子的缓冲层，以及掺杂有所述离子的非晶硅薄膜进行刻蚀，得到非晶硅半导体层，所述非晶硅半导体层中靠近所述源极和漏极的表面区域内的所述离子的浓度大于或等于5×10 20离子/立方厘米。
  14. 根据权利要求13所述的方法，其特征在于，所述采用湿法刻蚀工艺，对掺杂有所述离子的缓冲层，以及掺杂有所述离子的非晶硅薄膜进行刻蚀，得到非晶硅半导体层，包括：
    采用湿法刻蚀工艺，完全刻蚀掉有源层区域之外的缓冲层和非晶硅薄膜；
    采用湿法刻蚀工艺，完全刻蚀掉所述有源层区域的缓冲层，并保留注入有所述离子的非晶硅薄膜；
    对保留的所述非晶硅薄膜中，位于源极接触区域和漏极接触区域之间的沟道区域进行刻蚀，并保留所述沟道区域中离子的浓度小于或等于3×10 19离子/立方厘米的部分。
  15. 根据权利要求13所述的方法，其特征在于，所述缓冲层的厚度小于所述非晶硅薄膜的厚度。
  16. 根据权利要求15所述的方法，其特征在于，所述缓冲层的厚度在200～300埃之间；
    所述非晶硅薄膜的厚度在1400～2000埃之间；
    所述湿法刻蚀工艺的刻蚀厚度在20～30埃之间。
  17. 根据权利要求13至16任一所述的方法，其特征在于，所述湿法刻蚀工艺中采用的刻蚀溶液为酸性刻蚀液。
  18. 根据权利要求17所述的方法，其特征在于，所述对保留的所述非晶硅薄膜中，位于源极接触区域和漏极接触区域之间的沟道区域进行刻蚀的刻蚀厚度大于或等于500埃。
  19. 根据权利要求13至16任一所述的方法，其特征在于，所述离子注入工艺中采用的气氛包括磷化氢，离子剂量大于或等于e 15个/平方厘米，加速电压大于或等于20千伏且小于或等于30千伏。
  20. 根据权利要求13至16任一所述的方法，其特征在于，所述在衬底基板上形成非晶硅薄膜包括：
    按照第一膜层沉积速率在所述衬底基板上沉积第一非晶硅薄膜；
    按照第二膜层沉积速率在所述第一非晶硅薄膜远离所述衬底基板的一侧沉积第二非晶硅半导体薄膜；
    其中，所述第一膜层沉积速率在4～8埃/秒之间；
    所述第二膜层沉积速率在30～50埃/秒之间。
  21. 一种显示面板，其特征在于，所述显示面板包括：衬底基板，以及位于所述衬底基板上的多个如权利要求1至12任一所述的非晶硅薄膜晶体管；
    所述衬底基板上同时具备所述非晶硅薄膜晶体管以及低温多晶硅薄膜晶体。
PCT/CN2021/121965 2021-09-29 2021-09-29 非晶硅薄膜晶体管及其制备方法、显示面板 WO2023050238A1 (zh)

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