TW201606988A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TW201606988A
TW201606988A TW104119459A TW104119459A TW201606988A TW 201606988 A TW201606988 A TW 201606988A TW 104119459 A TW104119459 A TW 104119459A TW 104119459 A TW104119459 A TW 104119459A TW 201606988 A TW201606988 A TW 201606988A
Authority
TW
Taiwan
Prior art keywords
semiconductor
tft
semiconductor device
electrode
layer
Prior art date
Application number
TW104119459A
Other languages
English (en)
Inventor
井手啓介
斉藤貴翁
神崎庸輔
高丸泰
金子誠二
松木薗広志
宮本忠芳
Original Assignee
夏普股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 夏普股份有限公司 filed Critical 夏普股份有限公司
Publication of TW201606988A publication Critical patent/TW201606988A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

Abstract

本發明之半導體裝置(100)具有基板(11)、第1TFT(10)、及第2TFT(20)。第1TFT具有：第1半導體層(12)，其被基板支持；第1閘極電極(14)，其係以介隔第1閘極絕緣層(13)與第1半導體層重疊之方式形成於第1半導體層上；第1絕緣層(16)，其覆蓋第1閘極電極；以及第1源極電極(17s)及第1汲極電極(17d)，其等形成於第1絕緣層上，且連接於第1半導體層。第2TFT具有：第2閘極電極(22)，其被基板支持；第2半導體層(25)，其係以介隔第2閘極絕緣層(23)與第2閘極電極重疊之方式形成於第2閘極電極，且含有氧化物半導體；以及第2源極電極(24s)及第2汲極電極(24d)，其等形成於第2閘極絕緣層與第2半導體層之間。第1半導體層及第2閘極電極係由共通之半導體膜(52)形成。

Description

半導體裝置
本發明係關於一種具有薄膜電晶體(TFT)之半導體裝置。
近年來，液晶顯示裝置等顯示裝置被廣泛用於移動電話、智慧型手機、平板型移動終端等。為了實現顯示裝置之小型化及邊框區域之窄小化(窄邊框化)，正在推進驅動單一積體電路型(驅動電路一體型或周邊電路一體型)之顯示裝置之開發。所謂邊框區域係指無助於顯示之區域，例如存在於顯示區域之周邊。於驅動單一積體電路型之顯示裝置中，像素驅動用TFT及驅動電路用TFT係設置於共通之基板上。此處，像素驅動用TFT係指連接於像素之TFT，驅動電路用TFT係指對像素驅動用TFT供給信號之驅動器IC(Integrated Circuit，積體電路)所包含之TFT。
驅動單一積體電路型之顯示裝置要求進一步之消耗電力之降低及窄邊框化。提出有對像素驅動用TFT及驅動電路用TFT使用具有互不相同之特性之TFT。例如，作為驅動電路用TFT，若使用具有高遷移率及低閾值電壓之TFT，則驅動電路用TFT能夠高速地進行動作，故而可實現顯示裝置之消耗電力之降低及/或窄邊框化。另一方面，作為像素驅動用TFT，若優先使用具有低漏電流之TFT，則能以低頻率驅動顯示裝置，從而可降低顯示裝置之消耗電力。
專利文獻1及專利文獻2揭示有一種於基板上具有像素驅動用TFT 及驅動電路用TFT之顯示裝置。像素驅動用TFT係使用氧化物半導體作為半導體層(活化層)之材料的TFT，驅動電路用TFT係使用低溫多晶矽(LTPS)作為半導體層之材料的TFT。
先前技術文獻 專利文獻
專利文獻1：日本專利特開2010-3910號公報
專利文獻2：國際公開第2012/176422號
然而，專利文獻1之顯示裝置存在以下問題。專利文獻1之顯示裝置之像素驅動用TFT係與氧化物半導體層之上表面相接地設置有源極電極及汲極電極之頂部接觸型TFT。於形成頂部接觸型TFT之步驟中，典型而言，以與氧化物半導體層之上表面中之至少通路部分相接之方式形成絕緣層。該絕緣層作為蝕刻終止層發揮功能，保護通道區域不受形成源極電極及汲極電極時之蝕刻影響。蝕刻終止層係藉由減輕TFT之半導體層所受到之損傷，而能夠抑制TFT之特性之變動。因此，於專利文獻1之顯示裝置中，因設置作為蝕刻終止層發揮功能之絕緣層，而有存在製造步驟數(光罩數)增加之情況的問題。
本發明之目的在於，不使製造步驟數增加便實現具有TFT之半導體裝置之消耗電力之降低及/或窄邊框化。
本發明之實施形態之半導體裝置包含：基板；第1TFT，其具有被上述基板支持之第1半導體層、以介隔第1閘極絕緣層與上述第1半導體層重疊之方式形成於上述第1半導體層上之第1閘極電極、覆蓋上述第1閘極電極之第1絕緣層、以及形成於上述第1絕緣層上且連接於上述第1半導體層之第1源極電極及第1汲極電極；以及第2TFT，其具 有被上述基板支持之第2閘極電極、以介隔第2閘極絕緣層與上述第2閘極電極重疊之方式形成於上述第2閘極電極且含有氧化物半導體之第2半導體層、以及形成於上述第2閘極絕緣層與上述第2半導體層之間之第2源極電極及第2汲極電極；且上述第1半導體層及上述第2閘極電極係由共通之半導體膜形成。。
於某一實施形態中，上述第1閘極絕緣層及上述第2閘極絕緣層係由共通之第1絕緣膜形成。
於某一實施形態中，上述第1閘極電極、上述第2源極電極及上述第2汲極電極係由共通之第1導電膜形成。
於某一實施形態中，進而具有覆蓋上述第2半導體層之第2絕緣層，且上述第1絕緣層及上述第2絕緣層係由共通之第2絕緣膜形成。
於某一實施形態中，進而具有第3閘極電極，該第3閘極電極介隔上述第2絕緣層與上述第2半導體層重疊。
於某一實施形態中，上述第1源極電極、上述第1汲極電極及上述第3閘極電極係由共通之第2導電膜形成。
於某一實施形態中，上述第2閘極電極與上述第3閘極電極電性連接。
於某一實施形態中，上述第2閘極電極與上述第2源極電極電性連接。
於某一實施形態中，上述第2半導體層包含In-Ga-Zn-O系半導體。
於某一實施形態中，上述In-Ga-Zn-O系半導體包含晶質部分。
於某一實施形態中，進而具有第3TFT，該第3TFT具有：第4閘極電極，其被上述基板支持；第3半導體層，其係以介隔第3閘極絕緣層與上述第4閘極電極重疊之方式形成於上述第4閘極電極，且含有氧化物半導體；以及第3源極電極及第3汲極電極，其等形成於上述第3閘 極絕緣層與上述第3半導體層之間；且上述第3汲極電極與上述第1汲極電極電性連接。
於某一實施形態中，上述第3半導體層包含In-Ga-Zn-O系半導體。
於某一實施形態中，上述第3半導體層之上述In-Ga-Zn-O系半導體包含晶質部分。
根據本發明之實施形態，不使製造步驟數增加便可實現具有TFT之半導體裝置之消耗電力之降低及/或窄邊框化。
10‧‧‧第1TFT
11‧‧‧基板
12‧‧‧第1半導體層
12d‧‧‧汲極區域
12i‧‧‧通道區域
12s‧‧‧源極區域
13‧‧‧第1閘極絕緣層
14‧‧‧第1閘極電極
16‧‧‧第1絕緣層
17d‧‧‧第1汲極電極
17s‧‧‧第1源極電極
18‧‧‧第1平坦化層
20‧‧‧第2TFT
20a‧‧‧第2TFT
20b‧‧‧第2TFT
22‧‧‧第2閘極電極
23‧‧‧第2閘極絕緣層
24d‧‧‧第2汲極電極
24s‧‧‧第2源極電極
25‧‧‧第2半導體層
26‧‧‧第2絕緣層
27‧‧‧第3閘極電極
28‧‧‧第2平坦化層
30a‧‧‧第3TFT
30b‧‧‧第3TFT
31‧‧‧半導體膜
32‧‧‧第4閘極電極
33‧‧‧第3閘極絕緣層
34d‧‧‧第3汲極電極
34s‧‧‧第3源極電極
35‧‧‧第3半導體層
36‧‧‧第3絕緣層
37‧‧‧第5閘極電極
38‧‧‧第3平坦化層
52‧‧‧半導體膜
53‧‧‧第1絕緣膜
54‧‧‧第1導電膜
55‧‧‧氧化物半導體膜
56‧‧‧第2絕緣膜
57‧‧‧第2導電膜
58‧‧‧平坦化膜
60‧‧‧像素電極
71d‧‧‧第1接觸孔
71s‧‧‧第1接觸孔
72‧‧‧第2接觸孔
73‧‧‧第3接觸孔
74‧‧‧第4接觸孔
75‧‧‧第5接觸孔
76‧‧‧第6接觸孔
77‧‧‧第7接觸孔
100‧‧‧半導體裝置
110‧‧‧半導體裝置
120‧‧‧半導體裝置
130‧‧‧半導體裝置
140‧‧‧半導體裝置
圖1(a)及(b)係本發明之實施形態之半導體裝置100之模式圖，(a)係沿著(b)中之1A-1A'線之半導體裝置100之模式性剖視圖，(b)係半導體裝置100之模式性俯視圖。
圖2(a)及(b)係本發明之另一實施形態之半導體裝置110之模式圖，(a)係沿著(b)中之2Aa-2Aa'線及2Ab-2Ab'線之半導體裝置110之模式性剖視圖，(b)係半導體裝置110之模式性俯視圖，(c)係半導體裝置110所具有之第2TFT20a之電路圖。
圖3(a)及(b)係本發明之又一實施形態之半導體裝置120之模式圖，(a)係沿著(b)中之3A-3A'線之半導體裝置120之模式性剖視圖，(b)係半導體裝置120之模式性俯視圖，(c)係半導體裝置120所具有之第2TFT20b之電路圖。
圖4(a)~(c)係分別用以說明半導體裝置110之製造方法之一例的模式性剖視圖。
圖5(a)及(b)係分別用以說明半導體裝置110之製造方法之一例的模式性剖視圖。
圖6(a)及(b)係本發明之又一實施形態之半導體裝置130之模式 圖，(a)係沿著(b)中之6Aa-6Aa'線及6Ab-6Ab'線之半導體裝置130之模式性剖視圖，(b)係半導體裝置130之模式性俯視圖。
圖7(a)及(b)係本發明之又一實施形態之半導體裝置140之模式圖，(a)係沿著(b)中之7Aa-7Aa'線及7Ab-7Ab'線之半導體裝置140之模式性剖視圖，(b)係半導體裝置140之模式性俯視圖。
以下，參照圖式，對本發明之實施形態之半導體裝置進行說明。實施形態之半導體裝置係例如用於顯示裝置(例如包含液晶顯示裝置或有機EL(Electroluminescence，電致發光)顯示裝置等)或顯示裝置之TFT基板。以下，例示液晶顯示裝置作為顯示裝置。再者，本發明之實施形態之半導體裝置並不限於顯示裝置。本發明並不限定於以下例示之實施形態。於以下之圖式中，具有實質上相同之功能之構成要素係以共通之參照符號表示，且存在省略其說明之情形。
於圖1(a)及(b)中表示本發明之實施形態之半導體裝置100之模式圖。圖1(a)係沿著圖1(b)中之1A-1A'線之半導體裝置100之模式性剖視圖，圖1(b)係半導體裝置100之模式性俯視圖。
如圖1(a)所示般，半導體裝置100具有基板11、第1TFT10及第2TFT20。第1TFT10具有：第1半導體層12，其被基板11支持；第1閘極電極14，其係以介隔第1閘極絕緣層13與第1半導體層12重疊之方式形成於第1半導體層12上；第1絕緣層16，其覆蓋第1閘極電極14；以及第1源極電極17s及第1汲極電極17d，其等形成於第1絕緣層上，且連接於第1半導體層12。第2TFT20具有：第2閘極電極22，其被基板11支持；第2半導體層25，其係以介隔第2閘極絕緣層23與第2閘極電極22重疊之方式形成於第2閘極電極22，且含有氧化物半導體；以及第2源極電極24s及第2汲極電極24d，其等形成於第2閘極絕緣層23與第2半導體層25之間。第1半導體層12及第2閘極電極22係由共通之半 導體膜52形成。
半導體裝置100之第2TFT20係第2半導體層25之下表面與第2源極電極24s及第2汲極電極24d相接之底部接觸型TFT。於形成第2TFT20之步驟中，無需對含有氧化物半導體之第2半導體層25形成蝕刻終止層。半導體裝置100可不增加製造步驟數(例如光罩數)而抑制第2TFT20之特性之變動。半導體裝置100不使製造步驟數增加，便可實現消耗電力之降低及/或窄邊框化。
半導體裝置100進而具有像素電極60，該像素電極60例如經由第2接觸孔72與第2汲極電極24d連接。半導體裝置100具有例如配置為矩陣狀之複數個像素。像素具有例如像素電極60、與像素電極60對向之對向電極、及設置於該等電極之間之液晶層。藉由對液晶層施加電壓，而控制液晶分子之配向。第2TFT20例如連接於複數個像素之各者，可用作像素之開關元件。由於第2半導體層25含有氧化物半導體，故而第2TFT20具有低漏電流，從而可降低半導體裝置100之消耗電力。
第2TFT20之第2閘極電極22係例如連接於對應之閘極匯流排線(未圖示)，第2源極電極24s係例如連接於對應之源極匯流排線(未圖示)。對閘極匯流排線，例如，自閘極驅動器(未圖示)以特定時序供給特定之信號電壓(例如掃描信號電壓)。對源極匯流排線，例如，自源極驅動器(未圖示)以特定時序供給特定之信號電壓(例如顯示信號電壓)。由於液晶顯示裝置之構造已眾所周知，故而省略詳細之說明。
第1TFT10可用於例如對像素供給信號之驅動電路。驅動電路包含例如閘極驅動器或源極驅動器。驅動電路係設置於例如半導體裝置100之配置有像素之區域(像素區域)的周邊。第1TFT10之第1半導體層12之通道區域12i係由例如低溫多晶矽(LTPS)形成。第1TFT10由於具有高遷移率及低閾值電壓，故而可實現半導體裝置100之消耗電力之 降低及/或窄邊框化。
半導體裝置100亦可進而具有控制電路(未圖示)，該控制電路例如對具有第1TFT10之驅動電路(包含例如閘極驅動器或源極驅動器)輸入特定之信號。
第2源極電極24s既可電性連接於源極匯流排線，亦可與源極匯流排線形成為一體。第2閘極電極22由於由半導體膜52形成，故而藉由與例如由金屬形成之閘極匯流排線電性連接而能夠降低電阻。源極匯流排線及閘極匯流排線既可分別由例如與第2源極電極24s及第2汲極電極24d共通之導電膜形成，亦可由與第1源極電極17s及第1汲極電極17d共通之導電膜形成。
如圖1(a)所示般，第1半導體層12包含通道區域12i、源極區域12s及汲極區域12d。第1閘極電極14係介隔第1閘極絕緣層13與通道區域12i重疊。形成第1半導體層12及第2閘極電極22之半導體膜52係由例如多晶矽形成。源極區域12s、汲極區域12d及第2閘極電極22係藉由例如對導電體膜52(例如多晶矽)摻雜雜質(例如硼)而形成。第1源極電極17s係經由例如第1接觸孔71s與源極區域12s電性連接，第1汲極電極17d係經由例如第1接觸孔71d與汲極區域12d電性連接。
如圖1(a)所示般，第1閘極絕緣層13及第2閘極絕緣層23係由例如共通之第1絕緣膜53形成。第1閘極電極14、第2源極電極24s及第2汲極電極24d係由例如共通之第1導電膜54形成。藉由利用共通之膜形成複數個絕緣層或複數個電極，可抑制半導體裝置之製造步驟數之增加。但是，半導體裝置100並不限定於上述構造。第1閘極絕緣層13及第2閘極絕緣層23亦可由互不相同之絕緣膜形成。第1閘極電極14、第2源極電極24s及第2汲極電極24d亦可由互不相同之導電膜形成。
第1TFT10進而具有第1平坦化層18，該第1平坦化層18例如覆蓋第1源極電極17s及第1汲極電極17d。第2TFT20進而具有例如覆蓋第2 半導體層25之第2絕緣層26。第2TFT20進而具有例如覆蓋第2絕緣層26之第2平坦化層28。第1絕緣層16及第2絕緣層26係由例如共通之第2絕緣膜56形成。第1絕緣層16及第2絕緣層26亦可由互不相同之絕緣膜形成。第1平坦化層18及第2平坦化層28係由例如相同之平坦化膜58形成。第1平坦化層18及第2平坦化層28亦可由互不相同之平坦化膜形成。
其次，參照圖2(a)~圖2(c)，對本發明之另一實施形態之半導體裝置110進行說明。圖2(a)及圖2(b)係半導體裝置110之模式圖，圖2(a)係沿著圖2(b)中之2Aa-2Aa'線及2Ab-2Ab'線之半導體裝置110之模式性剖視圖，圖2(b)係半導體裝置110之模式性俯視圖，圖2(c)係半導體裝置110所具有之第2TFT20a之電路圖。
如圖2(a)及圖2(b)所示般，半導體裝置110與半導體裝置100不同之處在於進而具有第3閘極電極27，該第3閘極電極27介隔第2絕緣層26與第2半導體層25重疊。半導體裝置110除了第3閘極電極27以外，其他部分可與半導體裝置100相同。
如圖2(a)及圖2(b)所示般，第3閘極電極27係由例如與第1源極電極17s及第1汲極電極17d共通之第2導電膜57形成。
半導體裝置110之第2TFT20a係第2半導體層25之下表面與第2源極電極24s及第2汲極電極24d相接之底部接觸型TFT。於形成第2TFT20a之步驟中，無需對含有氧化物半導體之第2半導體層25形成蝕刻終止層。半導體裝置110可不增加製造步驟數(例如光罩數)而抑制第2TFT20a之特性之變動。半導體裝置100不使製造步驟數增加，便可實現消耗電力之降低及/或窄邊框化。
半導體裝置110之第2TFT20a具有雙閘極構造，該雙閘極構造係將第2閘極電極22及第3閘極電極27配置於第2半導體層25之兩側，且2個電極介隔絕緣層(例如，第2閘極絕緣層23及第2絕緣層26之各者)與 第2半導體層25重疊。具有雙閘極構造之TFT可使施加至源極、汲極間之電壓分散，故而可有效地抑制漏電流之增加及短通道效應。半導體裝置110係藉由第2TFT20a具有雙閘極構造，而能夠有效地實現消耗電力之降低。
上述專利文獻2之顯示裝置具有底閘極型且底部接觸型之像素驅動用TFT。於專利文獻2之顯示裝置中，像素驅動用TFT之閘極電極係由與驅動電路用TFT之閘極電極共通之導電膜形成，像素驅動用TFT之源極電極及汲極電極係由與驅動電路用TFT之源極電極及汲極電極共通之導電膜形成。因此，為了將像素驅動用TFT設為雙閘極構造，必須新追加形成頂閘極電極之步驟，從而製造步驟數可能增加。
相對於此，於半導體裝置110中，第2TFT20a之第2閘極電極22係由與第1TFT10之第1半導體層12共通之半導體膜52形成。因此，可由與第1TFT10之第1源極電極17s及第1汲極電極17d共通之第2導電膜57形成可能成為第2TFT20a之頂閘極電極之第3閘極電極27。半導體裝置110可不增加製造步驟數而包含具有雙閘極構造之第2TFT20a。具有雙閘極構造之第2TFT20a可有效地抑制漏電流之增加。半導體裝置110不使製造步驟數增加，便可實現消耗電力之降低及/或窄邊框化。
如圖2(a)~圖2(c)所示般，第2閘極電極22例如經由第3接觸孔73與第3閘極電極27電性接觸。由於對2個閘極電極供給相同之信號電壓，故而第2TFT20a可實現高遷移率。半導體裝置110可有效地降低消耗電力。
半導體裝置110所具有之第2TFT20a之第2閘極電極22及第3閘極電極27亦可不電性連接。亦可分別對第2閘極電極22及第3閘極電極27施加信號電壓。施加至第2閘極電極22及第3閘極電極27之信號電壓既可相同，亦可不同。第3閘極電極27既可與閘極匯流排線形成為一體，亦可電性連接於閘極匯流排線。閘極匯流排線例如既可由第2導 電膜57形成，亦可由第1導電膜54形成。
其次，參照圖3(a)~圖3(c)，對本發明之又一實施形態之半導體裝置120進行說明。圖3(a)及圖3(b)係半導體裝置120之模式圖，圖3(a)係沿著圖3(b)中之3A-3A'線之半導體裝置120之模式性剖視圖，圖3(b)係半導體裝置120之模式性俯視圖，圖3(c)係半導體裝置120所具有之第2TFT20b之電路圖。
如圖3(a)~圖3(c)所示般，半導體裝置120與半導體裝置110不同之處在於第2閘極電極22與第2源極電極24s電性連接。半導體裝置120除了第2閘極電極22之電性連接以外，其他部分可與半導體裝置110相同。第2閘極電極22係例如經由第4接觸孔74與第2源極電極24s電性連接。
半導體裝置120之第2TFT20b係第2半導體層25之下表面與第2源極電極24s及第2汲極電極24d相接之底部接觸型TFT。於形成第2TFT20b之步驟中，無需對含有氧化物半導體之第2半導體層25形成蝕刻終止層。半導體裝置120可不增加製造步驟數(例如光罩數)而抑制第2TFT20b之特性之變動。半導體裝置120不使製造步驟數增加，便可實現消耗電力之降低及/或窄邊框化。
於半導體裝置120中，第2TFT20b之第2閘極電極22係由與第1TFT10之第1半導體層12共通之半導體膜52形成。因此，可由與第1TFT10之第1源極電極17s及第1汲極電極17d共通之第2導電膜57形成可能成為第2TFT20b之頂閘極電極之第3閘極電極27。半導體裝置120可不增加製造步驟數，而包含具有雙閘極構造之第2TFT20b。具有雙閘極構造之第2TFT20b可有效地抑制漏電流之增加。半導體裝置120不使製造步驟數增加，便可實現消耗電力之降低及/或窄邊框化。
半導體裝置120由於第2閘極電極22與第2源極電極24s電性連接，故而可抑制第2TFT20b之閾值電壓之偏移。例如，可抑制閾值電壓向 負方向偏移，故而可抑制第2TFT20b之漏電流增大。又，可抑制閾值電壓向正方向偏移，故而可抑制施加至第2TFT20b之驅動之電力增大。半導體裝置120不使製造步驟數增加，便可實現消耗電力之降低及/或窄邊框化。
其次，參照圖4(a)~圖4(c)及圖5(a)~圖5(b)，說明半導體裝置110之製造方法。圖4(a)~圖4(c)及圖5(a)~圖5(b)分別係模式性地表示半導體裝置110之製造方法之一例的剖視圖。
首先，如圖4(a)所示般，於基板11上形成半導體膜52。
例如，於將半導體堆積於基板11之整面而形成半導體膜52後，將半導體膜52圖案化成特定之形狀或圖案(例如島狀)。半導體膜52藉由圖案化而分別設置於形成第1TFT10及第2TFT20a之區域(有時分別稱為第1TFT區域之半導體膜52、及第2TFT區域之半導體膜52)。
基板11係絕緣性基板，例如為玻璃基板。半導體膜52係由例如多晶矽形成。由多晶矽形成之半導體膜52可藉由例如利用CVD(Chemical Vapor Deposition，化學氣相沈積)法使非晶矽(a-Si)堆積於基板11上，並使用準分子雷射將所形成之薄膜熔融結晶化(準分子雷射退火)而獲得。半導體膜52之厚度例如為30nm~100nm。
其次，如圖4(b)所示般，形成第1閘極絕緣層13及第2閘極絕緣層23。
第1閘極絕緣層13及第2閘極絕緣層23係由例如將絕緣性材料堆積於基板11之整面而形成之第1絕緣膜53形成。於堆積絕緣性材料時，可使用例如CVD法或PVD(Physical Vapor Deposition，物理氣相沈積)法。於堆積第1絕緣膜53後，亦可視需要對基板11之整面進行雜質之注入。於堆積第1絕緣膜53後，亦可將第1絕緣膜53圖案化成特定之形狀(圖案)。第1閘極絕緣層13及第2閘極絕緣層23分別包含例如二氧化矽(SiO2)、氮化矽(SiNx)、氮氧化矽(SiOxNy，x>y)、或氧氮化矽 (SiNxOy，x>y)。第1閘極絕緣層13及第2閘極絕緣層23既可分別為單層，亦可為複數層膜之積層構造。第1閘極絕緣層13及第2閘極絕緣層23之厚度分別為例如50nm~300nm。
其次，形成第1閘極電極14、第2源極電極24s及第2汲極電極24d。該等電極可藉由例如於將導電性材料(例如金屬)堆積於第1絕緣膜53上而形成第1導電膜54後，利用光微影製程圖案化成特定之形狀(圖案)而獲得。第1閘極電極14係介隔第1閘極絕緣層13與第1TFT區域之半導體膜52之一部分重疊。第2源極電極24s及第2汲極電極24d亦可介隔第2閘極絕緣層23與第2TFT區域之半導體膜52之一部分重疊。
第1導電膜54係由例如鋁(Al)、鎢(W)、鉬(Mo)、鉭(Ta)、鉻(Cr)、鈦(Ti)、銅(Cu)等金屬形成。第1導電膜54既可為包含上述金屬之合金，亦可含有上述金屬之氮化物。此處，例如，使鈦堆積而形成第1導電膜54，從而形成第1閘極電極14、第2源極電極24s及第2汲極電極24d。第1閘極電極14、第2源極電極24s及第2汲極電極24d之厚度分別為例如70nm~300nm。
其次，藉由對半導體膜52注入雜質(例如硼)，而形成第1半導體層12及第2閘極電極22。於注入雜質時，可使用例如離子注入法或熱擴散法。於注入雜質後，視需要進行退火。
於對半導體膜52注入雜質時，由第1導電膜54形成之第1閘極電極14、第2源極電極24s及第2汲極電極24d作為遮罩發揮功能。第1TFT區域之半導體膜52中之未與第1閘極電極14重疊之部分係藉由注入雜質而被賦予導電性，從而成為源極區域12s及汲極區域12d。與第1閘極電極14重疊之部分未被注入雜質，而成為通道區域12i。由第1TFT區域之半導體膜52形成包含通道區域12i、源極區域12s及汲極區域12d之第1半導體層12。
藉由對第2TFT區域之半導體膜52中之與第2源極電極24s及第2汲 極電極24d均不重疊之部分注入雜質，而被賦予導電性，從而形成第2閘極電極22。
其次，如圖4(c)所示般，於第2源極電極24s及第2汲極電極24d上形成第2半導體層25。
第2半導體層25包含氧化物半導體。第2半導體層25包含例如In-Ga-Zn-O系之半導體(以下，簡略記作「In-Ga-Zn-O系半導體」)。此處，In-Ga-Zn-O系半導體為In(銦)、Ga(鎵)、Zn(鋅)之三元系氧化物，且In、Ga及Zn之比率(組成比)並無特別限定，包含例如In：Ga：Zn=2：2：1、In：Ga：Zn=1：1：1、In：Ga：Zn=1：1：2等。第2半導體層25亦可包含例如InGaO3(ZnO)5。
具有In-Ga-Zn-O系半導體層之TFT由於具有高遷移率(與非晶矽(a-Si)TFT相比超過20倍)及低漏電流(與a-SiTFT相比未達100分之1)，故而適合用作驅動TFT及像素TFT。具有In-Ga-Zn-O系半導體層之TFT由於具有高遷移率，故而可實現TFT之小型化。若使用具有In-Ga-Zn-O系半導體層之TFT，則例如能夠大幅地削減半導體裝置之消耗電力及/或提高半導體裝置之解像度。
In-Ga-Zn-O系半導體既可為非晶體(非晶質)，亦可包含晶質部分。作為晶質In-Ga-Zn-O系半導體，較佳為c軸大致垂直於層面地配向之晶質In-Ga-Zn-O系半導體。此種In-Ga-Zn-O系半導體之結晶構造例如於日本專利特開2012-134475號公報有所揭示。為參考起見，將日本專利特開2012-134475號公報之全部揭示內容引用至本說明書中。
第2半導體層25亦可包含其他氧化物半導體來代替In-Ga-Zn-O系半導體。例如亦可包含Zn-O系半導體(ZnO)、In-Zn-O系半導體(IZO(註冊商標))、Zn-Ti-O系半導體(ZTO)、Cd-Ge-O系半導體、Cd-Pb-O系半導體、CdO(氧化鎘)、Mg-Zn-O系半導體、In-Sn-Zn-O系半 導體(例如In2O3-SnO2-ZnO)、In-Ga-Sn-O系半導體等。
Zn-O系半導體包含例如於ZnO中不添加任何雜質元素者、或於ZnO中添加有雜質之半導體。Zn-O系半導體包含例如添加有1族元素、13族元素、14族元素、15族元素或17族元素等中之一種、或複數種雜質元素之半導體。Zn-O系半導體包含例如氧化鎂鋅(MgxZn1-xO)或氧化鎘鋅(CdxZn1-xO)。Zn-O系半導體既可為非晶體(非晶質)，亦可為多晶體，或亦可為非晶質狀態及多晶狀態混合之微晶狀態者。
第2半導體層25之厚度例如為30nm~100nm。此處，例如，於利用濺鍍法將氧化物半導體成膜後，藉由光微影製程加工成特定之形狀(圖案)，而形成第2半導體層25。於形成第2半導體層25後，亦可視需要進行退火。退火係例如於大氣中、氮氣氛圍中、或氧氣氛圍中進行。退火係於形成氧化物半導體之薄膜後，既可於圖案化之前進行，亦可於圖案化之後進行。
其次，如圖5(a)所示般，形成第1絕緣層16及第2絕緣層26。
第1絕緣層16及第2絕緣層26係由例如將絕緣性材料堆積於基板11之整面而形成之第2絕緣膜56形成。於堆積第2絕緣膜56後，亦可將第2絕緣膜56圖案化成特定之形狀(圖案)。第1絕緣層16及第2絕緣層26分別含有例如二氧化矽(SiO2)、氮化矽(SiNx)、氮氧化矽(SiOxNy，x>y)、或氧氮化矽(SiNxOy，x>y)。第1絕緣層16及第2絕緣層26既可分別為單層，亦可為複數層膜之積層構造。第1絕緣層16及第2絕緣層26之厚度分別為例如50nm~300nm。第1絕緣膜53及第2絕緣膜56既可為相同厚度，亦可為互不相同之厚度。於第2TFT20a具有雙閘極構造之情形時，較佳為第2閘極絕緣層23及第2絕緣層26為相同厚度。
其次，形成2個第1接觸孔71s及71d與第3接觸孔73。第1接觸孔71s及71d係設置於第1閘極絕緣層13及第1絕緣層16之開口部，且係分別到達至源極區域12s及汲極區域12d之開口部。第3接觸孔73係設置 於第2閘極絕緣層23及第2絕緣層26之開口部，且係到達至第2閘極電極22之開口部。接觸孔係藉由例如光微影製程而形成，該光微影製程包括如下步驟：於絕緣層上，形成具有用以形成接觸孔之開口部的光阻遮罩；及對絕緣層進行蝕刻。
其次，形成第1源極電極17s、第1汲極電極17d及第3閘極電極27。該等電極係例如藉由光微影製程將於第2絕緣膜56上堆積導電性材料(例如金屬)而形成之第2導電膜57加工成特定之形狀(圖案)而獲得。第1源極電極17s及第1汲極電極17d分別經由第1接觸孔71s及第1接觸孔71d與源極區域12s及汲極區域12d之各者電性連接。
第2導電膜57係由例如鋁(Al)、鎢(W)、鉬(Mo)、鉭(Ta)、鉻(Cr)、鈦(Ti)、銅(Cu)等金屬形成。第2導電膜57既可為包含上述金屬之合金，亦可含有上述金屬之氮化物。此處，例如，使鈦堆積而形成第2導電膜57，並將第2導電膜57圖案化，藉此形成第1源極電極17s、第1汲極電極17d及第3閘極電極27。第1源極電極17s、第1汲極電極17d及第3閘極電極27之厚度分別為例如100nm~600nm。
其次，如圖5(b)所示般，形成第1平坦化層18及第2平坦化層28。第1平坦化層18及第2平坦化層28係由例如將絕緣性材料堆積於基板11之整面而形成之平坦化膜58形成。平坦化膜58含有例如無機絕緣材料(例如二氧化矽、氮化矽、氮氧化矽、或氧氮化矽)或有機絕緣材料。
其次，設置第2接觸孔72。第2接觸孔72係例如設置於第2平坦化層28及第2絕緣層26之開口部，且到達至第2汲極電極24d。
繼而，形成像素電極60。像素電極60係由例如具有可見光透過性之導電性材料(例如氧化物半導體)形成。像素電極60通過第2接觸孔72與第2汲極電極24電性連接。
藉由以上步驟，而製造半導體裝置110。
半導體裝置100之製造方法係除了形成第3閘極電極27之步驟以 外，其他可與半導體裝置110之製造方法相同。半導體裝置120之製造方法係除了第2閘極電極22之電性連接以外，其他可與半導體裝置110之製造方法相同。
其次，參照圖6(a)及圖6(b)，對本發明之又一實施形態之半導體裝置130進行說明。圖6(a)及圖6(b)係半導體裝置130之模式圖，圖6(a)係沿著圖6(b)中之6Aa-6Aa'線及6Ab-6Ab'線之半導體裝置130之模式性剖視圖，圖6(b)係半導體裝置130之模式性俯視圖。
如圖6(a)及圖6(b)所示般，半導體裝置130與半導體裝置100不同之處在於進而具有第3TFT30a。半導體裝置130除了進而具有第3TFT30a以外，其他部分可與半導體裝置110相同。
第3TFT30a具有：第4閘極電極32，其被基板11支持；第3半導體層35，其係以介隔第3閘極絕緣層33與第4閘極電極32重疊之方式形成，且含有氧化物半導體；以及第3源極電極34s及第3汲極電極34d，其等形成於第3閘極絕緣層33與第3半導體層35之間。第3汲極電極34d與第1TFT10之第1汲極電極17d電性連接。第3汲極電極34d及第1汲極電極17d係經由例如第6接觸孔76而電性連接。
第1TFT及第3TFT30a形成CMOS(Complementary Metal Oxide Semiconductor，互補金氧半導體)反相器電路。於半導體裝置130中，例如，第1TFT10為p通道型之TFT，第3TFT30a為n通道型之TFT。藉由將形成CMOS反相器電路之第1TFT10及第3TFT30a用於半導體裝置130之驅動電路，可降低驅動電路之消耗電力。又，藉由使驅動電路之消耗電力降低，可使供設置驅動電路之區域之面積窄小化。因此，可實現半導體裝置130之消耗電力之降低及/或窄邊框化。
半導體裝置130之第2TFT20a係第2半導體層25之下表面與第2源極電極24s及第2汲極電極24d相接之底部接觸型TFT。於形成第2TFT20a之步驟中，無需對含有氧化物半導體之第2半導體層25形成 蝕刻終止層。半導體裝置130可不增加製造步驟數(例如光罩數)而抑制第2TFT20a之特性之變動。半導體裝置130不使製造步驟數增加，便可實現消耗電力之降低及/或窄邊框化。
如圖6(a)及圖6(b)所示般，第3TFT30a進而具有第5閘極電極37，該第5閘極電極37介隔第3絕緣層36與第3半導體層35重疊。第3TFT30a例如具有雙閘極構造，該雙閘極構造係將第4閘極電極32及第5閘極電極37配置於第3半導體層35之兩側。第3TFT30a例如具有與第2TFT20a相同之構造。第3TFT30a所具有之層及膜可由例如與對應之第2TFT20a之層或膜相同之材料形成，且以相同之步驟形成。半導體裝置130無需為了設置第3TFT30a而增加製造步驟數。半導體裝置130藉由第3TFT30a具有雙閘極構造，可有效地降低消耗電力。半導體裝置130不使製造步驟數增加，便可實現消耗電力之降低及/或窄邊框化。如圖6(a)及圖6(b)所示般，第4閘極電極32例如經由第5接觸孔75與第5閘極電極37電性連接。
如圖6(a)及圖6(b)所示般，第4閘極電極32係由例如半導體膜52形成。第3閘極絕緣層33係由例如第1絕緣膜53形成。含有氧化物半導體之第3半導體層35係由例如與第2半導體層25共通之氧化物半導體膜55形成。第3源極電極34s及第3汲極電極34d係由例如第1導電膜54形成。第3絕緣層36係由例如第2絕緣膜56形成。第5閘極電極37係由例如第2導電膜57形成。第3TFT30a進而具有覆蓋例如第3絕緣層36之第3平坦化層38。第3平坦化層38係由例如平坦化膜58形成。
半導體裝置130之第2TFT20a亦可不具有第3閘極電極27。半導體裝置130之第2TFT亦可與半導體裝置100之第2TFT20相同。半導體裝置130之第2TFT亦可與半導體裝置120之第2TFT20b相同。
半導體裝置130之第3TFT30a亦可不具有第5閘極電極37。半導體裝置130之第3TFT係例如底閘極型且底部接觸型之TFT，亦可具有與 半導體裝置100之第2TFT20相同之構造。
其次，參照圖7(a)及圖7(b)，對本發明之又一實施形態之半導體裝置140進行說明。圖7(a)及圖7(b)係半導體裝置140之模式圖，圖7(a)係沿著圖7(b)中之7Aa-7Aa'線及7Ab-7Ab'線之半導體裝置140之模式性剖視圖，圖7(b)係半導體裝置140之模式性俯視圖。
如圖7(a)及圖7(b)所示般，半導體裝置140與半導體裝置130不同之處在於第4閘極電極32與第3源極電極34s電性連接。半導體裝置140除了第4閘極電極32之電性連接以外，其他部分可與半導體裝置130相同。第4閘極電極32係經由例如第7接觸孔77與第3源極電極34s電性連接。
半導體裝置140之第2TFT20a係第2半導體層25之下表面與第2源極電極24s及第2汲極電極24d相接之底部接觸型之TFT。於形成第2TFT20a之步驟中，無需對含有氧化物半導體之第2半導體層25形成蝕刻終止層。半導體裝置140可不增加製造步驟數(例如光罩數)而抑制第2TFT20a之特性之變動。半導體裝置140不使製造步驟數增加，便可實現消耗電力之降低及/或窄邊框化。
半導體裝置140之第3TFT30b進而具有例如第5閘極電極37，該第5閘極電極37介隔第3絕緣層36與第3半導體層35重疊。第3TFT30b具有例如雙閘極構造，該雙閘極構造係將第4閘極電極32及第5閘極電極37配置於第3半導體層35之兩側。第3TFT30b具有例如與半導體裝置120之第2TFT20b相同之構造。
第3TFT30b所具有之層及膜可由例如與對應之第2TFT20a之層或膜相同之材料形成，且以相同之步驟形成。半導體裝置140無需為了設置第3TFT30b而增加製造步驟數。半導體裝置140藉由第3TFT30b具有雙閘極構造，而能夠有效地降低消耗電力。半導體裝置140不使製造步驟數增加，便可實現消耗電力之降低及/或窄邊框化。
於上述實施形態中，對TFT(包含第1TFT、第2TFT、第3TFT)之源極電極及汲極電極係由共通之導電膜(或半導體膜)形成，閘極電極係由與該膜不同之導電膜形成之例進行了表示，但本發明之實施形態並不限定於此。源極電極及/或汲極電極亦可由與閘極電極共通之導電膜形成。就抑制製造步驟數之增加之觀點而言，較佳為TFT(包含第1TFT、第2TFT、第3TFT)之源極電極、汲極電極及閘極電極分別由半導體膜52、第1導電膜54及第2導電膜57中之任一者形成。
[產業上之可利用性]
本發明之實施形態之半導體裝置可廣泛應用於例如液晶顯示裝置、有機EL顯示裝置、或電泳顯示裝置等各種驅動單一積體電路型顯示裝置。
10‧‧‧第1TFT
11‧‧‧基板
12‧‧‧第1半導體層
12d‧‧‧汲極區域
12i‧‧‧通道區域
12s‧‧‧源極區域
13‧‧‧第1閘極絕緣層
14‧‧‧第1閘極電極
16‧‧‧第1絕緣層
17d‧‧‧第1汲極電極
17s‧‧‧第1源極電極
18‧‧‧第1平坦化層
20‧‧‧第2TFT
22‧‧‧第2閘極電極
23‧‧‧第2閘極絕緣層
24d‧‧‧第2汲極電極
24s‧‧‧第2源極電極
25‧‧‧第2半導體層
26‧‧‧第2絕緣層
28‧‧‧第2平坦化層
52‧‧‧半導體膜
53‧‧‧第1絕緣膜
54‧‧‧第1導電膜
56‧‧‧第2絕緣膜
58‧‧‧平坦化膜
60‧‧‧像素電極
71d‧‧‧第1接觸孔
71s‧‧‧第1接觸孔
72‧‧‧第2接觸孔
100‧‧‧半導體裝置

Claims (13)

  1. 一種半導體裝置，其包括：基板；第1TFT，其具有：第1半導體層，其被上述基板支持；第1閘極電極，其係以介隔第1閘極絕緣層與上述第1半導體層重疊之方式形成於上述第1半導體層上；第1絕緣層，其覆蓋上述第1閘極電極；以及第1源極電極及第1汲極電極，其等形成於上述第1絕緣層上，且連接於上述第1半導體層；以及第2TFT，其具有：第2閘極電極，其被上述基板支持；第2半導體層，其係以介隔第2閘極絕緣層與上述第2閘極電極重疊之方式形成於上述第2閘極電極，且含有氧化物半導體；以及第2源極電極及第2汲極電極，其等形成於上述第2閘極絕緣層與上述第2半導體層之間；且上述第1半導體層及上述第2閘極電極係由共通之半導體膜形成。
  2. 如請求項1之半導體裝置，其中上述第1閘極絕緣層及上述第2閘極絕緣層係由共通之第1絕緣膜形成。
  3. 如請求項1或2之半導體裝置，其中上述第1閘極電極、上述第2源極電極及上述第2汲極電極係由共通之第1導電膜形成。
  4. 如請求項1至3中任一項之半導體裝置，其進而具有覆蓋上述第2半導體層之第2絕緣層；且上述第1絕緣層及上述第2絕緣層係由共通之第2絕緣膜形成。
  5. 如請求項4之半導體裝置，其進而具有第3閘極電極，該第3閘極電極介隔上述第2絕緣層與上述第2半導體層重疊。
  6. 如請求項5之半導體裝置，其中上述第1源極電極、上述第1汲極 電極及上述第3閘極電極係由共通之第2導電膜形成。
  7. 如請求項5或6之半導體裝置，其中上述第2閘極電極與上述第3閘極電極電性連接。
  8. 如請求項5或6之半導體裝置，其中上述第2閘極電極與上述第2源極電極電性連接。
  9. 如請求項1至8中任一項之半導體裝置，其中上述第2半導體層包含In-Ga-Zn-O系半導體。
  10. 如請求項9之半導體裝置，其中上述In-Ga-Zn-O系半導體包含晶質部分。
  11. 如請求項1至10中任一項之半導體裝置，其進而包括第3TFT，該第3TFT具有：第4閘極電極，其被上述基板支持；第3半導體層，其係以介隔第3閘極絕緣層與上述第4閘極電極重疊之方式形成於上述第4閘極電極，且含有氧化物半導體；以及第3源極電極及第3汲極電極，其等形成於上述第3閘極絕緣層與上述第3半導體層之間；且上述第3汲極電極與上述第1汲極電極電性連接。
  12. 如請求項11之半導體裝置，其中上述第3半導體層包含In-Ga-Zn-O系半導體。
  13. 如請求項12之半導體裝置，其中上述第3半導體層之上述In-Ga-Zn-O系半導體包含晶質部分。
TW104119459A 2014-06-17 2015-06-16 半導體裝置 TW201606988A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014124185 2014-06-17

Publications (1)

Publication Number Publication Date
TW201606988A true TW201606988A (zh) 2016-02-16

Family

ID=54935404

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104119459A TW201606988A (zh) 2014-06-17 2015-06-16 半導體裝置

Country Status (3)

Country Link
US (1) US20170125452A1 (zh)
TW (1) TW201606988A (zh)
WO (1) WO2015194417A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107346083A (zh) * 2016-05-06 2017-11-14 株式会社日本显示器 显示装置
CN108155195A (zh) * 2016-12-02 2018-06-12 群创光电股份有限公司 显示设备
CN112038358A (zh) * 2016-05-17 2020-12-04 群创光电股份有限公司 显示设备

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108292684B (zh) * 2015-11-20 2022-06-21 株式会社半导体能源研究所 半导体装置、该半导体装置的制造方法或包括该半导体装置的显示装置
JP2017174946A (ja) * 2016-03-23 2017-09-28 株式会社ジャパンディスプレイ 半導体装置の製造方法
KR102359245B1 (ko) 2016-07-08 2022-02-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 전자 기기
JP2018013567A (ja) * 2016-07-20 2018-01-25 株式会社ジャパンディスプレイ 表示装置
CN107818987B (zh) * 2016-09-14 2024-01-16 天马微电子股份有限公司 半导体装置及其制造方法和显示设备及其制造方法
JP6878173B2 (ja) * 2017-06-26 2021-05-26 株式会社ジャパンディスプレイ 半導体装置
CN107818989B (zh) 2017-10-20 2020-08-04 武汉华星光电技术有限公司 阵列基板及其制作方法
TWI651765B (zh) * 2018-03-29 2019-02-21 友達光電股份有限公司 結晶金屬氧化物層的製造方法、主動元件基板的製造方法及主動元件基板
JP6799123B2 (ja) * 2018-09-19 2020-12-09 シャープ株式会社 アクティブマトリクス基板およびその製造方法
KR20200046213A (ko) * 2018-10-23 2020-05-07 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
CN109920800A (zh) * 2019-02-28 2019-06-21 武汉华星光电半导体显示技术有限公司 一种显示装置及其制作方法
US11476363B2 (en) 2019-04-10 2022-10-18 United Microelectronics Corp. Semiconductor device and method of fabricating the same
US11296023B2 (en) 2019-04-10 2022-04-05 United Microelectronics Corp. Semiconductor device and method of fabricating the same
CN111816710A (zh) * 2019-04-10 2020-10-23 联华电子股份有限公司 半导体装置
EP3806151A1 (en) * 2019-10-08 2021-04-14 Imec VZW Thin-film transistor architecture for high resolution displays
CN111179742A (zh) * 2020-02-12 2020-05-19 武汉华星光电技术有限公司 一种显示面板、栅极驱动电路及电子装置
CN111384070B (zh) * 2020-03-25 2023-05-19 京东方科技集团股份有限公司 一种像素结构、阵列基板、显示装置和制作方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4622532B2 (ja) * 2005-01-18 2011-02-02 三菱電機株式会社 表示装置および表示装置の欠陥修復方法
JP5264197B2 (ja) * 2008-01-23 2013-08-14 キヤノン株式会社 薄膜トランジスタ
US8902210B2 (en) * 2008-10-10 2014-12-02 Lg Display Co., Ltd. Liquid crystal display device
KR101065407B1 (ko) * 2009-08-25 2011-09-16 삼성모바일디스플레이주식회사 유기 발광 표시 장치 및 그 제조 방법
KR101073542B1 (ko) * 2009-09-03 2011-10-17 삼성모바일디스플레이주식회사 유기 발광 표시 장치 및 그 제조 방법
WO2012032749A1 (ja) * 2010-09-09 2012-03-15 シャープ株式会社 薄膜トランジスタ基板及びその製造方法、表示装置
KR101770969B1 (ko) * 2011-01-21 2017-08-25 삼성디스플레이 주식회사 터치 센싱 기판 및 이의 제조 방법
KR102108248B1 (ko) * 2012-03-14 2020-05-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 산화물 반도체막, 트랜지스터, 및 반도체 장치
KR102227474B1 (ko) * 2013-11-05 2021-03-15 삼성디스플레이 주식회사 박막트랜지스터 어레이 기판, 유기발광표시장치 및 박막트랜지스터 어레이 기판의 제조 방법

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107346083A (zh) * 2016-05-06 2017-11-14 株式会社日本显示器 显示装置
CN107346083B (zh) * 2016-05-06 2020-10-30 株式会社日本显示器 显示装置
CN112038358A (zh) * 2016-05-17 2020-12-04 群创光电股份有限公司 显示设备
CN108155195A (zh) * 2016-12-02 2018-06-12 群创光电股份有限公司 显示设备
CN108155194A (zh) * 2016-12-02 2018-06-12 群创光电股份有限公司 显示装置
US10861879B2 (en) 2016-12-02 2020-12-08 Innolux Corporation Display device
CN108155195B (zh) * 2016-12-02 2021-06-04 群创光电股份有限公司 显示设备
CN113257839A (zh) * 2016-12-02 2021-08-13 群创光电股份有限公司 显示设备
CN113257840A (zh) * 2016-12-02 2021-08-13 群创光电股份有限公司 显示设备

Also Published As

Publication number Publication date
US20170125452A1 (en) 2017-05-04
WO2015194417A1 (ja) 2015-12-23

Similar Documents

Publication Publication Date Title
TW201606988A (zh) 半導體裝置
JP6215053B2 (ja) 表示装置及びその製造方法
CN109273404B (zh) 一种阵列基板及其制备方法、显示面板、显示装置
JP5670028B2 (ja) トランジスタとこれを含む半導体素子及びそれらの製造方法
US9236496B2 (en) Thin film transistor and display device
US10297694B2 (en) Semiconductor device and method for manufacturing same
TWI623101B (zh) 半導體裝置及其製造方法
TWI538210B (zh) 半導體裝置及其製造方法
TWI550877B (zh) 半導體裝置之製造方法
TWI543371B (zh) 半導體裝置及其製造方法
KR20100027377A (ko) 박막 트랜지스터 기판 및 이의 제조 방법
KR102188690B1 (ko) 박막트랜지스터, 그의 제조방법 및 박막트랜지스터를 구비하는 평판 표시장치
TW201411855A (zh) 半導體裝置及其製造方法
TW201310646A (zh) 半導體裝置及其製造方法
WO2015186602A1 (ja) 半導体装置およびその製造方法
US8842229B2 (en) Thin film transistor substrate, method for producing same, and display device
US20190243194A1 (en) Active matrix substrate and method for manufacturing same
TWI497689B (zh) 半導體元件及其製造方法
US20190296050A1 (en) Active matrix substrate and method for manufacturing same
US10991725B2 (en) Active matrix substrate and method for producing same
TW201342617A (zh) 半導體裝置及其之製造方法
WO2016104253A1 (ja) 半導体装置
US8866141B2 (en) Thin film transistor and method for fabricating the same
TWI559554B (zh) 半導體裝置及其製造方法
TWI546965B (zh) 半導體裝置及其製造方法