CN113257840A - 显示设备 - Google Patents

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Publication number
CN113257840A
CN113257840A CN202110533113.8A CN202110533113A CN113257840A CN 113257840 A CN113257840 A CN 113257840A CN 202110533113 A CN202110533113 A CN 202110533113A CN 113257840 A CN113257840 A CN 113257840A
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China
Prior art keywords
display device
transistor
channel
ratio
channel layer
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Pending
Application number
CN202110533113.8A
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English (en)
Inventor
刘敏钻
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Innolux Corp
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Innolux Corp
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Publication of CN113257840A publication Critical patent/CN113257840A/zh
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    • G—PHYSICS
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    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • G06F3/047—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using sets of wires, e.g. crossed wires
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract

本公开是关于一种显示设备，包括：一基板，具有显示区和与该显示区相邻之一周边区；一第一晶体管，设置于该显示区之上并且包括一第一通道层，其中该第一通道层包括一氧化物半导体层；以及一第二晶体管，设置于该周边区之上并且包括一第二通道层，其中该第二通道层包括一硅半导体层。本公开中，该第一通道层的第一通道宽度与其第一通道长度的比值为第一比值，该第一比值是大于或等于0.4并且小于或等于4.5；以及该第二通道层的第二通道宽度与其第二通道长度的比值为第二比值，该第二比值是大于或等于0.05并且小于或等于0.8。

Description

显示设备
本申请为分案申请，母案申请号为201711209703.5，申请日为2017年11月27日，发明名称为：显示设备。
技术领域
本公开是关于一种显示设备，尤指一种包括低温多晶硅薄膜晶体管以及金属氧化物薄膜晶体管的显示设备。
背景技术
随者显示设备的技术进步，显示面板朝向更多功能、更轻薄的方向发展。薄膜显示器，例如液晶显示面板、有机发光二极管(OLED)显示面板、和无机发光二极管显示面板等，已取代阴极射线管而成为主导市场的显示设备。薄膜显示器的应用广泛，多数日常电子产品均使用薄膜显示面板，例如移动电话、笔记本电脑、摄影机、照相机、播音器、移动导航、电视等。
市面上常见液晶显示设备和OLED显示设备，其中LCD显示设备的技术更加成熟，且制造商更加致力于改良显示设备的显示质量，以因应显示设备的技术进展以及消费者需求。
薄膜晶体管(Thin film transistor，TFT)结构可为多晶硅薄膜晶体管，其具有高载子移动率的特征；或可为金属氧化物薄膜晶体管，其具有低漏电流的特征。虽然多晶硅薄膜晶体管和金属氧化物薄膜晶体管的部分特征彼此互补，但因为两者制造过程不兼容，使得此类晶体管显示设备制造过程总体而言非常复杂，例如需要多次化学气相沉积，故目前并无结合前述两个类型的晶体管的显示设备。
基于以上理由，有必要改良并且简化薄膜晶体管基板的制备方法，使其同时具有多晶硅薄膜晶体管和金属氧化物薄膜晶体管。
发明内容
本公开的目的是提供一种显示设备，其同时具有低温多晶硅(LTPS)薄膜晶体管和金属氧化物薄膜晶体管。
本公开的显示设备包括：一第一基板；一第一晶体管，设置于该第一基板之上并且包括一第一通道层，其中该第一通道层包括一氧化物半导体层；以及一第二晶体管，设置于该第一基板之上并且包括一第二通道层，其中该第二通道层包括一硅半导体层；其中，该第一通道层的第一通道宽度与该第一通道层的该第一通道长度的比值为第一比值，以及该第二通道层的第二通道宽度与该第二通道层的该第二通道长度的比值为第二比值；其中，该第一比值是大于或等于0.4并且小于或等于4.5，以及该第二比值是大于或等于0.09并且小于或等于0.45；其中，该第一晶体管包括一第一源极和一第一漏极，以及该第一通道长度定义为该第一源极和该第一漏极间的最小距离；其中，该第二晶体管包括一第二源极和一第二漏极，该第二源极和该第二漏极各自通过一接触孔与该第二通道层电性连接，该第二通道宽度是该等接触孔的最大宽度，以及该第二通道长度是该等接触孔间的最小距离。
本公开的显示设备中，包括氧化物半导体层的该第一晶体管是设置于该显示区之上。若第一通道层的第一通道宽度与第一通道长度的第一比值落于上述范围内，可达成较佳分辨率、较佳开口率、亮度一致性、和/或高架构速率。此外，本公开的显示设备中，包括硅半导体层的该第二晶体管是设置于该周边区之上。若第二通道层的第二通道宽度与第二通道长度的第二比值落于上述范围内，可达成较佳充电效率，以及可进一步缩小该周边区。此外，若该第一比值和该第二比值落于前述范围内，该第一晶体管的电性和该第二晶体管的充电能力可更加相容。
其他目的、优势、新颖特征将于下文详述之，并参照图式，以明确表示本公开。
附图说明
图1是本公开实施例1的显示设备的剖面示意图。
图2是本公开实施例1的显示设备的上方视图。
图3是本公开实施例1的发光二极管显示设备的像素的等效电路图。
图4是本公开实施例1的液晶显示设备的像素的等效电路图。
图5是本公开实施例1的第一基板上的第一晶体管的上方视图。
图6是图5中第一晶体管的沿剖面线I-I’的剖面示意图。
图7是本公开实施例1的第一基板上的第二晶体管的上方视图。
图8是图7中第二晶体管的沿剖面线II-II’的剖面示意图。
图9是本公开实施例2的第一晶体管的剖面示意图。
图10是本公开实施例3的第二晶体管的剖面示意图。
具体实施方式
以下参照图式说明本公开的实施方式，以明确阐释前述和其他技术内容、特征、和功效。通过特定实施例的说明，本领域的技术人员可进一步明了本公开采取的技术手段和功效，以达成前述公开目的。另，本说明书所公开的技术可为本领域的技术人员理解并且实施，在不悖离本公开概念的前提下，任何变更或改良均可被权利要求所涵盖。
此外，本说明书和权利要求所提及的序数，例如“第一”、“第二”等，仅用于说明主张的组件；而非意指、或表示主张的组件具有任何执行次序，也非于一主张的组件和另一主张的组件之间的次序、或制成方法的步骤次序。该些序数的使用仅用来使具有某命名的一请求组件得以和另一具有相同命名的请求组件能作出清楚区分。
此外，本说明书和权利要求所提及的位置，例如“之上”、“上”、或“上方”，可指直接与另一基板或膜接触，或可指非直接与另一基板或膜接触。
实施例1
图1是本实施例的显示设备的剖面示意图。其中，该显示设备包括：一第一基板1；一第二基板2，与该第一基板1相对设置；以及一显示介质层3，设置于该第一基板1和该第二基板2之间。于本实施例中，该第一基板1和该第二基板2可使用玻璃、塑料、可挠性材料、或薄膜制备；但本公开的基板材料不限于此。若第一基板1和第二基板2以塑料、可挠性材料或薄膜制备，则该显示设备可为可挠式显示设备。本实施例中，该显示介质3可包括一液晶层、或一发光二极管(例如有机或无机发光二极管)；但本公开的显示介质不限于此。此外，本公开的其他实施例中，若该显示介质3为发光二极管，该显示设备可选择性地具有或不具有第二基板2。
图2是本实施例的显示设备的上方视图。如图1和图2所示，本实施例的显示设备包括：一显示区AA和一外围区B，并且该周边区B和该显示区AA相邻。如图2所示，本实施例的显示设备包括：一印刷电路板11，部分设置于该周边区B之上；一集成电路12，设置于该周边区B之上，并且与该印刷电路板11电性连接；一多任务解讯器13，设置于该周边区B之上，并且与该集成电路12电性连接；一驱动电路14，设置于该周边区B之上，并且与该集成电路12电性连接；以及多个像素单元15，设置于该显示区AA之上，其中该些像素单元15自该驱动电路14和该多任务解讯器13接收信号。
本实施例的显示设备中，该第一基板具有多个像素单元15。若该显示介质3为发光二极管(例如，无机发光二极管或有机发光二极管)，该些像素单元其中之一可设计为，例如，图3所公开的等效电路图。图3的等效电路图中，该像素单元包括：一驱动薄膜晶体管T1；一开关薄膜晶体管T2，其中扫描信号Sn和数据信号Data可被传输至该开关薄膜晶体管T2；一重置薄膜晶体管T3，其中启动电压Vini和重置信号Rst可被传输至该重置薄膜晶体管T3，以启动该驱动薄膜晶体管T1；一发光薄膜晶体管T4，其中发光控制信号En可被传输至该发光薄膜晶体管T4；一第一电容C1；以及一第二电容Cst。故，图3所公开的等效电路图是一4T2C电路。此外，一驱动电压VSS传输至一有机发光二极管OLED；以及该有机发光二极管OLED的阴极连接至一公共电压VSS。该有机发光二极管显示设备例示如上，但本公开公开的显示设备不限于此，前述等效电路图也可应用于无机发光显示设备，例如微发光二极管显示设备。
若该显示介质3为液晶层，该些像素其中之一可设计为，例如，图4所公开的等效电路图。图4的等效电路图中，该像素单元包括：一薄膜晶体管TFT，其中扫描信号Sn和数据信号Data传输至该薄膜晶体管TFT；一电容Cst；以及液晶层所形成的一液晶电容Clc。
图3的等效电路图中，该晶体管其中至少一者包括一氧化物半导体层(例如IGZO薄膜晶体管、ITZO薄膜晶体管、或IGTZO薄膜晶体管)。图4的等效电路图中，该薄膜晶体管TFT包括一氧化物半导体层。下文实施例中，使用IGZO薄膜晶体管作为例示。相较于LTPS薄膜晶体管，IGZO薄膜晶体管具有较高工艺一致性，因此具有较佳临界电压一置性以及低电漏；故，IGZO薄膜晶体管较适合做为设置于显示区的晶体管。
进一步地，图3和图4所公开的显示设备的等效电路图中，该驱动电路14和该多任务解讯器13也可包括多个晶体管。用于该驱动电路14和该多任务解讯器13的晶体管可包括一硅半导体层(例如低温多晶硅(LTPS)薄膜晶体管)，以缩减周边区。此外，LTPS薄膜晶体管可用于较小区域并且提供较佳晶体管效能一致性。相较于IGZO薄膜晶体管，LTPS薄膜晶体管具有较高充电能力，并且较适合用于窄边框设计。
图5是本实施例的第一基板上的第一晶体管的上方视图，其为IGZO薄膜晶体管；以及图6是图5中第一晶体管的沿剖面线I-I’的剖面示意图。下文简述该IGZO薄膜晶体管的制备流程。
首先，提供一第一基板1，再于该第一基板1之上形成一第一缓冲层21和一第二缓冲层22。接着，于该第二缓冲层22之上形成一第一栅极23，再于该第一栅极23之上形成一第一栅绝缘层24。而后，于该第一栅绝缘层24之上形成一第一通道层25，其为氧化半导体层，再于该第一通道层25之上形成一第一源极26和一第一漏极27。最后，于该第一源极26和该第一漏极27之上形成一钝化层28，可得到本实施例的IGZO薄膜晶体管。
图7是本实施例的第一基板上的第二晶体管的上方视图，其为低温多晶硅晶体管；以及图8是图7中第二晶体管的沿剖面线II-II’的剖面示意图。下文简述该低温多晶硅薄膜晶体管的制备流程。
首先，提供一第一基板1，再于该第一基板1之上形成一第三缓冲层31。接着，于该第三缓冲层31之上形成一非晶硅层，再于该非晶硅层上进行退火以得到一第二通道层32。该第二通道层32为一硅半导体层，且为低温多晶硅层。于此，一第二源极36和一第二漏极37形成于该第二通道层32上的区域具有掺杂。形成该第二通道层32之后，形成一第二栅绝缘层33。而后，于该第二栅绝缘层33之上形成一第二栅电极34，再形成一层间介电层35。一第二源极36和一第二漏极37形成于该层间介电层35之上，并且通过接触孔361，371与该第二通道层32电性连接。最后，于该第二源极36和该第二漏极37之上形成一钝化层38，可得到本实施例的低温多晶硅薄膜晶体管。
于此，该第一基板1的材料如前文所述，不另说明。该第一缓冲层21、该第二缓冲层22、该第一栅绝缘层24、该钝化层28、该第三缓冲层31、该第二栅绝缘层33、该层间介电层35、和该钝化层38可以绝缘材料制备，例如氧化硅、氮化硅、氮氧化硅、或其任意的组合，但本公开使用的绝缘材料不限于此。此外，该第一栅极23、该第一源极26、该第一漏极27、该第二栅极34、该第二源极36、和该第二漏极37可以金属(例如Cu、Al、Ti、Cr、Mo、或其合金)、或其他电极材料(例如透明导电氧化物，如ITO、IZO、ITZO等)制备，但本公开的电极材料不限于此。
本实施例中，即使于说明书中分别公开，图5和图6公开的IGZO薄膜晶体管、和图7和图8公开的低温多晶硅薄膜晶体管可同时制备。
此外，本实施例中，制备图5和图6所提供的IGZO薄膜晶体管时，同时形成扫描线231和该第一栅极23。制备图7和图8所提供的低温多晶硅薄膜晶体管时，同时形成扫描线341和该第二栅极34。即便未公开于图式，特定实施例中，该扫描线231可与该扫描线341电性连接；故该第一晶体管TFT1可与该第二晶体管TFT2电性连接。
完成前述流程后，可得到本实施例的显示设备。如图1、图2、和图5-8所示，该显示设备包括：一第一基板1，具有一显示区AA和与该显示区AA相邻的一周边区；一第一晶体管TFT1，设置于该显示区AA之上并且包括一第一通道层25，其中该第一通道层25包括一氧化物半导体层(本实施例中是IGZO层)；以及一第二晶体管TFT2，设置于该周边区B之上并且包括一第二通道层32，其中该第二通道层32包括一硅半导体层(本实施例中是低温多晶硅层)。
本实施例的显示设备中，该第二晶体管TFT2包括一硅半导体层，以及该第二晶体管TFT2是低温多晶硅薄膜晶体管。若设置于该周边区B上的晶体管为低温多晶硅薄膜晶体管，多个用于闸驱动单元的低温多晶硅薄膜晶体管可串联，以提供大量电流，并且可达成良好充电能力和/或良好的可靠度。此外，为达成窄周边区的目的，该周边区B的面积必须缩减并且增加该显示区AA的面积。若设置于该周边区B上的晶体管为低温多晶硅薄膜晶体管，该低温多晶硅薄膜晶体管可具有较小通道宽度和通道长度，以有效率地使用该周边区B。故，可将低温多晶硅薄膜晶体管以一有限面积设置于该周边区B上，以达成窄周边区的目的。
另一方面，本实施例的显示设备中，该第一晶体管TFT1包括一氧化物半导体层，以及该第一晶体管TFT1为氧化物薄膜晶体管。若设置于该显示区AA上的晶体管为氧化物薄膜晶体管，可达成良好的临界电压一致性、低漏电流、和/或较佳显示质量。
如图5所示，本实施例的显示设备进一步包括：一扫描线231，与该第一晶体管TFT电性连接，其中该扫描线231依第一方向X延伸。此外，该第一晶体管TFT1另包括一第一源极26和一第一漏极27。本说明书中，第一通道长度L1定义如下：该第一源极26和该第一漏极27沿第一方向X间的最小距离。进一步地，该第一源极26沿第二方向Y具有一第一源极宽度W11，其中该第二方向Y实质垂直于第一方向X；而该第一漏极27沿第二方向Y具有一第一漏极宽度W12。在此，第一通道宽度W1的定义为该第一源极宽度W11和该第一漏极宽度W12的平均，即W1＝(W11+W12)/2。在此，第一方向X与第二方向Y实质垂直，意即该第一方向X和第二方向Y之间夹角可介于85至90度。
如图7所示，该第二晶体管TFT2进一步包括一第二源极36和一第二漏极37，并且该第二源极36和该第二漏极37通过接触孔361，371电性连接至该第二通道层32。在此，第二通道宽度W2的定义为接触孔361，371的最大宽度。此外，第二通道长度L2的定义为接触孔361和接触孔371间的最小距离。本说明书中，该第二通道宽度W2和该第二通道长度L2实质垂直，意即该第二通道宽度W2和该第二通道长度L2之间夹角介于85至90度。
已知漏极电流与晶体管的通道宽度和通道长度相关；其关连如式I所不：
式I
漏极电流＝W/L×μ×Cox×(Vgs-Vth)
W：通道宽度
L：通道长度
Cox：每单位面积电容
Vgs：栅极至源极的电压
Vth：临界电压
如图5所示，对于该第一晶体管TFT1而言，该第一通道层25的第一通道宽度W1与该第一通道层25的第一通道长度L1的比值为第一比值。本实施例中，该第一比值大于或等于0.4并且小于或等于4.5，即0.4≤W1/L1≤4.5。若该第一比值落入前述范围，该显示设备可具有高分辨率、高开口率、良好的亮度一致性、和/或高架构速率。若该第一比值小于0.4(例如该第一通道长度L1太长)，第一晶体管TFT1的充电能力不足，其充电时间便增加，并且架构速率降低。此外，该显示设备的开口率也降低。若该第一比值大于4.5(例如该第一通道宽度W1过长)，栅极和源/漏极之间寄生电容Cgs增加，导致馈通(feed-through)效应增加。
于另一实施例中，该第一比值是大于或等于0.75且小于或等于2.5，即0.75≤W1/L1≤2.5。具有第一晶体管TFT1的显示设备，且W1/L1落于前述范围中，可具有较高分辨率、高充电能力、良好显示质量、和高开口率，可进一步降低显示设备耗电。
若该第一比值的下限提高至1，该第一晶体管TFT1的充电能力可进一步改善。若该第一比值的上限下降至1.5，该显示设备的分辨率可进一步增加，和/或降低寄生电容Cgs和馈通效应。因此，于进一步实施例，该第一比值是大于或等于1且小于或等于1.5，即1≤W1/L1≤1.5。
如图7所示，对于该第二晶体管TFT2而言，该第二通道层32的第二通道宽度W2与该第二通道层32的第二通道长度L2的比值为第二比值。本实施例中，该第二比值大于或等于0.05且小于或等于0.8，即0.05≤W2/L2≤0.8。若该第二比值落于前述范围，该第二晶体管TFT2可具有高充电能力和低电漏，以及/或该显示设备可具有窄周边区。此外，IGZO薄膜晶体管(第一晶体管TFT1)设置于显示区而低温多晶硅薄膜晶体管(第二晶体管TFT2)设置于周边区时，若IGZO薄膜晶体管自低温多晶硅薄膜晶体管输入的电流过大，该IGZO薄膜晶体管(第一晶体管TFT1)的漏电流会增加。此外，若第二晶体管TFT2的第二比值过大，寄生电容Cgs或Cgd则增加。在此，若该第二比值小于0.05(例如，第二通道宽度W2过小)，该第二晶体管TFT2的充电能力不足，造成其充电时间增加。若有更多的低温多晶硅薄膜晶体管彼此串联，该显示设备的周边区面积则会增加，即显示设备的边框和周边较大。若该第二比值大于0.8(例如，该第二通道长度L2过短)，可能产生严重漏电流，且正偏温压(positive biastemperature stress)较差。
另一实施例中，该第二比值大于或等于0.09并且小于或等于0.45，即0.09≤W2/L2≤0.45。当该第二晶体管TFT2的第二比值(W2/L2)落于前述范围，可改善该第二晶体管TFT2的充电能力，并且/或保有窄周边区。进一步地，若该第二比值的上限大于0.45，该第二晶体管TFT2的漏电流会太大，造成充电能力不佳以及较差的正偏温压可靠度。
另一实施例中，该第二比值大于或等于0.3且小于或等于0.45，0.3≤W2/L2≤0.45。该第二比值的下限提高至0.3，可确保该第二晶体管TFT2于周边区的整体充电能力可更加一致且提高。此外，可减少晶体管串联数量，以进一步减少周边区面积。
如图5和图7所示，该第一晶体管TFT1进一步包括一第一栅极23，该第一栅极23包括一第一重迭区232，并且该第一重迭区232与该第一通道层25重迭。该第二晶体管TFT2进一步包括一第二栅极34，该第二栅极34包括一第二重迭区342，并且该第二重迭区342与该第二通道层32重迭。本说明书中，该第一重迭区232大于该第二重迭区342。
如图6和图8所示，该第一晶体管TFT1中，该第一栅极23设置于该第一通道层25之下，因此该第一晶体管TFT1是底部栅极薄膜晶体管。于该第二晶体管TFT2中，该第二栅极34是设置于该第二通道层32之上，因此该第二晶体管TFT2是顶部栅极薄膜晶体管。若该第二晶体管TFT2具有顶部栅极结构，可达成低漏电流，并可降低该第二栅极34和该第二源极36/该第二漏极37之间电容耦合所产生的寄生电容等功效。此外，前述低漏电流的特性可增强闸驱动电路的低温多晶硅薄膜晶体管的效能，并且改善其充电能力。
实施例2
图9是本实施例的第一晶体管的剖面示意图。
本实施例的显示设备与实施例1的显示设备相似，相异之处在于，本实施例缩减该第一栅极23和该第一漏极27之间的重迭区域。因此，可进一步降低寄生电容Cgd。
实施例3
图10是本实施例的第二晶体管的剖面示意图。
本实施例的显示设备与实施例1的显示设备相似，相异之处在于，本实施例缩减于该第二栅极34外的该层间介电层35的厚度。
其他实施例
前述本公开的任一实施例的显示设备可应用于触控面板，形成触控显示设备。此外，前述本公开的任一实施例制备的显示设备或触控显示设备可应用于本领域其他使用显示屏幕的电子装置，例如显示器、移动电话、笔记本电脑、摄影机、照相机、播音器、移动导航、电视等任何显示图像的电子装置。
虽于本说明书中，本公开以前述实施例公开，但在不悖离本公开概念和权利要求范围的前提下，均可进行任何变更或改良。

Claims (10)

1.一种显示设备，其特征在于，包括：
一第一基板；
一第一晶体管，设置于该第一基板之上并且包括一第一通道层，其中该第一通道层包括一氧化物半导体层；以及
一第二晶体管，设置于该第一基板之上并且包括一第二通道层，其中该第二通道层包括一硅半导体层；
其中，该第一通道层的第一通道宽度与该第一通道层的该第一通道长度的比值为第一比值，该第二通道层的第二通道宽度与该第二通道层的该第二通道长度的比值为第二比值；
其中，该第一比值大于或等于0.4并且小于或等于4.5，该第二比值大于或等于0.09并且小于或等于0.45；
其中，该第一晶体管包括一第一源极和一第一漏极，以及该第一通道长度定义为该第一源极和该第一漏极间的最小距离；
其中，该第二晶体管包括一第二源极和一第二漏极，该第二源极和该第二漏极各自通过一接触孔与该第二通道层电性连接，该第二通道宽度是该等接触孔的最大宽度，以及该第二通道长度是该等接触孔间的最小距离。
2.如权利要求1所述的显示设备，其特征在于，该第一基板具有一显示区以及与该显示区相邻的一周边区。
3.如权利要求2所述的显示设备，其特征在于，该第一晶体管设置于该显示区之上并且该第二晶体管设置于该周边区之上。
4.如权利要求1所述的显示设备，其特征在于，该第一比值大于或等于0.75并且小于或等于2.5。
5.如权利要求4所述的显示设备，其特征在于，该第一比值大于或等于1并且小于或等于2.5。
6.如权利要求4所述的显示设备，其特征在于，该第一比值大于或等于0.75并且小于或等于1.5，以及该第二比值大于或等于0.3。
7.如权利要求1所述的显示设备，其特征在于，该第一晶体管包括一第一栅极，该第一栅极包括一第一重迭区，该第一重迭区与该第一通道层重迭；该第二晶体管包括一第二栅极，该第二栅极包括一第二重迭区，该第二重迭区与该第二通道层重迭；以及，该第一重迭区大于该第二重迭区。
8.如权利要求1所述的显示设备，其特征在于，该第一晶体管包括一第一栅极，该第一栅极设置于该第一通道层之下。
9.如权利要求1所述的显示设备，其特征在于，该第二晶体管包括一第二栅极，该第二栅极设置于该第二通道层之上。
10.如权利要求1所述的显示设备，其特征在于，该第一源极具有一第一源极宽度，该第一漏极具有一第一漏极宽度；以及该第一通道宽度是该第一源极宽度和该第一漏极宽度的平均值。
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