WO2015186602A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- WO2015186602A1 WO2015186602A1 PCT/JP2015/065419 JP2015065419W WO2015186602A1 WO 2015186602 A1 WO2015186602 A1 WO 2015186602A1 JP 2015065419 W JP2015065419 W JP 2015065419W WO 2015186602 A1 WO2015186602 A1 WO 2015186602A1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/772—Field effect transistors
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- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
Definitions
- the present invention relates to a semiconductor device using an oxide semiconductor and a manufacturing method thereof.
- An active matrix substrate used for a liquid crystal display device or the like includes a switching element such as a thin film transistor (hereinafter, “TFT”) for each pixel.
- a switching element such as a thin film transistor (hereinafter, “TFT”) for each pixel.
- TFT thin film transistor
- amorphous silicon TFT a TFT having an amorphous silicon film as an active layer
- polycrystalline silicon TFT a TFT having a polycrystalline silicon film as an active layer
- Patent Document 1 describes a liquid crystal display device in which an active layer of a TFT is formed using an oxide semiconductor film such as InGaZnO (oxide composed of indium, gallium, and zinc). Such a TFT is referred to as an “oxide semiconductor TFT”.
- An oxide semiconductor TFT can be operated at a higher speed than an amorphous silicon TFT.
- the oxide semiconductor film is formed by a simpler process than the polycrystalline silicon film, the oxide semiconductor film can be applied to a device that requires a large area. For this reason, oxide semiconductor TFTs are being used for display devices and the like as high-performance active elements that can be manufactured at low manufacturing costs.
- the pixel aperture ratio is an area ratio of an area (area excluding non-display areas such as wiring and TFT) that can be used for display in one pixel area.
- the higher the pixel aperture ratio the higher the aperture ratio from the backlight. Light utilization efficiency can be increased. By improving the pixel aperture ratio, bright display can be achieved and power consumption can be reduced.
- the pixel aperture ratio can be improved by using the oxide semiconductor TFT described above. This is because the mobility of an oxide semiconductor is high, and even if the size of the oxide semiconductor TFT is reduced, performance equal to or higher than that of an amorphous silicon TFT can be obtained.
- the region where the TFT is provided is light-shielded by a light-shielding layer (for example, a gate electrode or a black matrix) because it is a region that is difficult to use for display or to prevent light irradiation to the channel. If the size of is small, the pixel aperture ratio can be improved accordingly.
- Patent Document 2 describes a configuration in which a non-display area is reduced by providing a TFT on a gate wiring. If the downsizing of the TFT is realized in this manner, the area available for display in the pixel area can be increased, and the aperture ratio can be improved.
- JP 2003-86808 A International Publication No. 2013/073619 JP 2009-278115 A JP 2008-40343 A
- a gate-source parasitic capacitance Cgs whose size is determined by the overlap area and the thickness of the insulating layer is formed in a portion where the gate electrode (or gate wiring) and the source electrode overlap with each other through the insulating layer. Is done. Further, in a portion where the gate electrode and the drain wiring overlap with each other through the insulating layer, a gate-drain parasitic capacitance Cgd whose size is determined by the overlapping area and the thickness of the insulating layer is formed.
- FIGS. 11A and 11B show the configuration of a conventional bottom gate type oxide semiconductor TFT 90.
- the oxide semiconductor TFT 90 includes a gate electrode 92, a gate insulating layer 93 covering the gate electrode 92, and a gate electrode 92 on the gate insulating layer 93.
- an island-shaped oxide semiconductor layer 94 provided so as to overlap with each other, and a source electrode 95 and a drain electrode 96 respectively connected to both side ends of the island-shaped oxide semiconductor layer 94.
- the source electrode 95 and the drain electrode 96 are arranged so as to be separated from each other, and a portion of the oxide semiconductor layer 94 between the source electrode 95 and the drain electrode 96 is a channel of the oxide semiconductor TFT 90. It functions as 94C.
- the gate electrode 92 is provided to be large so as to overlap the entire oxide semiconductor layer 94. This is because the oxide semiconductor layer 94 has a relatively large electric resistance, and in order to obtain a high on-current, it is preferable to activate the entire oxide semiconductor layer 94 by an on-voltage applied to the gate electrode 92. .
- the parasitic capacitances Cgs and Cgd formed between the gate electrode 92 and the source / drain electrodes 95 and 96 reduce the operating speed of the oxide semiconductor TFT 90. If the parasitic capacitances Cgs and Cgd are large, when the oxide semiconductor TFT 90 is turned on, it takes a long time to apply a desired voltage to the liquid crystal layer, and a high-speed response may not be obtained.
- the TFT substrate is used for a liquid crystal display device
- the pixel voltage is lowered by the gate-drain parasitic capacitance Cgd.
- Such a decrease in the pixel voltage is called a feedthrough voltage (pull-in voltage), and its magnitude is roughly determined by the magnitude of the gate-drain parasitic capacitance Cgd (depending on the overlapping area between the gate electrode and the drain electrode). Often proportional.
- the oxide semiconductor TFT 90 since it is necessary to provide an overlapping region 95A between the gate electrode 92 and the source electrode 95 and an overlapping region 96A between the gate electrode 92 and the drain electrode 96 in a relatively large area, the size of the element can be reduced. There is a problem that it is difficult to make it. In addition, since the overlapping areas 95A and 96A are areas that cannot be used as display areas, the pixel aperture ratio is reduced.
- Patent Document 3 discloses a structure in which a spacer (hereinafter referred to as a sidewall) made of an insulating material is provided on a side surface of a gate electrode in a top gate type transistor.
- a spacer hereinafter referred to as a sidewall
- a conductive region is formed in a self-aligned manner in a semiconductor layer using a gate electrode and a sidewall as a mask, and thereby, between a channel region and a conductive region immediately below the gate electrode.
- an offset region is formed. If such a configuration in which an offset region is provided is adopted, the parasitic capacitances Cgs and Cgd can be easily reduced.
- the oxide semiconductor TFT has excellent off-leakage characteristics, but the resistance of the oxide semiconductor layer is often high. Therefore, if the distance between the gate electrode and the drain electrode is long, sufficient on-characteristics cannot be obtained. There was a fear.
- the TFT structure described in Patent Document 3 has a problem that it is difficult to realize a high aperture ratio because a region covered with the source electrode and the drain electrode becomes large. Further, since a step of providing a sidewall is necessary, there is a problem that the manufacturing process becomes complicated and the throughput of the product is lowered.
- the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device including an oxide semiconductor TFT with reduced parasitic capacitance and excellent operating characteristics, and a manufacturing method thereof.
- a semiconductor device includes a substrate, a thin film transistor provided on the substrate, a gate electrode, a gate insulating layer in contact with the gate electrode, and the gate electrode via the gate insulating layer.
- a thin film transistor having an oxide semiconductor layer disposed so as to partially overlap, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, the source electrode and the drain electrode being a substrate.
- the oxide semiconductor layer is provided apart from the gate electrode when viewed from a normal direction, and the oxide semiconductor layer overlaps the gate electrode when viewed from the substrate normal direction, and the gate At least one offset region provided adjacent to the opposing region, the gate electrode and the source electrode when viewed from the normal direction of the substrate And, and a one and do not overlap the offset region of the drain electrode, the carrier concentration of the gate opposing region is 1 ⁇ 10 17 / cm 3 to 1 ⁇ 10 19 / cm 3 or less.
- the carrier concentration of the at least one offset region is 1 ⁇ 10 17 / cm 3 or more.
- the semiconductor device includes a source connection region and a drain connection region that are provided adjacent to the offset region and are in contact with the source electrode and the drain electrode, and carriers in the source connection region and the drain connection region concentration is 1 ⁇ 10 17 / cm 3 or more.
- the carrier concentration in the at least one offset region is higher than the carrier concentration in the gate facing region.
- the thin film transistor is a depletion type.
- the gate electrode is provided below the oxide semiconductor layer with the gate insulating layer interposed therebetween.
- an etch stop layer is further provided above the oxide semiconductor layer so as to at least partially overlap the gate facing region of the oxide semiconductor layer.
- the gate electrode is provided above the oxide semiconductor layer with the gate insulating layer interposed therebetween.
- the semiconductor device includes a plurality of pixel regions arranged in a matrix having a row direction and a column direction on the substrate, and a plurality of pixel regions each extending substantially parallel to the row direction.
- a gate bus line and a plurality of source bus lines each extending substantially parallel to the column direction, and each of the plurality of pixel regions includes the thin film transistor and a pixel electrode connected to the thin film transistor.
- the at least one offset region of the oxide semiconductor layer extends from the source electrode formed in the source bus line to the gate bus line, and the drain electrode sandwiches the gate bus line And located on the opposite side of the source electrode.
- the oxide semiconductor layer contains at least one metal element of In, Ga, and Zn.
- the oxide semiconductor layer includes a crystalline part.
- a method of manufacturing a semiconductor device includes a step of preparing a substrate, and a step of providing a thin film transistor on the substrate, the gate electrode, a gate insulating layer in contact with the gate electrode, and the gate insulation. Forming an oxide semiconductor layer disposed so as to partially overlap the gate electrode through a layer, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, In the step of providing the thin film transistor, after forming the oxide semiconductor layer, the carrier concentration of the oxide semiconductor layer is changed, whereby the carrier concentration of the gate facing region in the oxide semiconductor layer is changed to 1 ⁇ 10 17 / and a step of adjusting to not less than cm 3 and not more than 1 ⁇ 10 19 / cm 3 .
- a semiconductor device including a TFT with reduced parasitic capacitance and improved operation speed and a method for manufacturing the same are provided.
- FIG. 1 It is a figure which shows the TFT substrate by Embodiment 1 of this invention, (a) is a top view, (b) is sectional drawing.
- (A) is a graph showing a graph X1 (solid line) showing the Vg-Id characteristics of the TFT according to Embodiment 1 of the present invention and a graph Y1 (broken line) showing the Vg-Id characteristics of the TFT of the reference example.
- (B) is a graph X2 showing the relationship between the carrier concentration of the oxide semiconductor layer and the on / off ratio for the TFT according to Embodiment 1 of the present invention.
- (A) to (d) is a cross-sectional view showing a TFT manufacturing process in the TFT substrate according to Embodiment 1 of the present invention, and (a ′) and (b ′) correspond to (a) and (b). It is a top view.
- (A) is a top view which shows the structural example in case the TFT substrate by Embodiment 1 is used for a liquid crystal display device
- (b) is a top view which shows the structural example of the TFT substrate of a reference example. It is a figure which shows the TFT substrate by Embodiment 2 of this invention, (a) is a top view, (b) is sectional drawing.
- (A) to (d) is a sectional view showing a TFT manufacturing process in a TFT substrate according to Embodiment 2 of the present invention, and (a ′) and (c ′) correspond to (a) and (c). It is a top view. It is a top view which shows the structural example in the case of using the TFT substrate by Embodiment 2 for a liquid crystal display device. It is a figure which shows the TFT substrate by Embodiment 3 of this invention, (a) is a top view, (b) is sectional drawing.
- FIG. 1 to (d) are cross-sectional views showing a TFT manufacturing process in a TFT substrate according to Embodiment 3 of the present invention, and (b ′) and (d ′) correspond to (b) and (d). It is a top view. It is a top view which shows the structural example in the case of using the TFT substrate by Embodiment 3 for a liquid crystal display device. It is a figure which shows the conventional TFT substrate, (a) is a top view, (b) is sectional drawing.
- the “semiconductor device” may be a device including a TFT, and includes a TFT substrate, a display device having the TFT substrate, and the like.
- FIG. 1A is a plan view showing the semiconductor device (TFT substrate) 100 according to the first embodiment, and FIG. 1B is a cross-sectional view taken along line AB in FIG. 1A. is there.
- the TFT substrate 100 is used in, for example, a liquid crystal display device that performs display in a VA (Vertical Alignment) mode.
- the TFT substrate 100 may be used in a liquid crystal display device that performs display in a horizontal electric field mode such as IPS (In-Plane Switching) and FFS (Fringe Field Switching). Further, the TFT substrate 100 may be used in an organic EL display device including a selection transistor. A more specific configuration when the TFT substrate 100 is used in a liquid crystal display device will be described later as a TFT substrate 110 with reference to FIG.
- the TFT substrate 100 includes a TFT 5 provided on the substrate 10. 1A and 1B show only one TFT 5, it goes without saying that a plurality of TFTs 5 may be provided on the TFT substrate 100. As will be described later, when used in a liquid crystal display device, the TFT substrate 100 includes a plurality of TFTs 5 provided corresponding to a plurality of pixels. In addition, when a driving circuit (a gate driver or the like) is provided monolithically outside the display region, the TFT substrate 100 may include a plurality of TFTs 5 for configuring the driving circuit.
- a driving circuit a gate driver or the like
- the TFT 5 has a bottom gate structure, and is provided on the gate electrode 12 provided on the insulating substrate 10, the gate insulating layer 20 covering the gate electrode 12, and the gate insulating layer 20.
- the island-shaped oxide semiconductor layer 18 is typically included.
- the oxide semiconductor layer 18 includes a gate facing region 18g (which may be referred to as an activation region or a channel region) that overlaps the gate electrode 12 when viewed from the substrate normal direction, and the gate facing region. And a pair of outer regions located on both outer sides (source side and drain side) of 18g. The pair of outer regions are regions that do not overlap with the gate electrode 12 in the oxide semiconductor layer 18.
- a gate facing region 18g (which may be referred to as an activation region or a channel region) that overlaps the gate electrode 12 when viewed from the substrate normal direction, and the gate facing region.
- a pair of outer regions located on both outer sides (source side and drain side) of 18g. The pair of outer regions are regions that do not overlap with the gate electrode 12 in the oxide semiconductor layer 18.
- the source electrode 14 and the drain electrode 16 are connected to a pair of outer regions located on both sides of the gate facing region 18g.
- the source electrode 14 and the drain electrode 16 are provided apart from the gate electrode 12 when viewed from the substrate normal direction.
- a region overlapping (in contact with) the source electrode 14 is referred to as a source connection region 18s
- a region overlapping (in contact with) the drain electrode 16 is referred to as a drain connection region 18d.
- a region 18os that does not overlap the gate electrode 12 or the source electrode 14 is formed between the gate facing region 18g and the source connection region 18s.
- a region 18od that does not overlap the gate electrode 12 or the drain electrode 16 is formed between the gate facing region 18g and the drain connection region 18d.
- these regions may be referred to as a source-side offset region 18os and a drain-side offset region 18od (collectively, offset regions 18os and 18od).
- the gate facing region 18g and the offset regions 18os and 18od of the oxide semiconductor layer 18 have substantially the same carrier concentration.
- the gate facing region 18g and the offset regions 18os and 18od are formed of the same oxide semiconductor film and are subjected to the same carrier concentration control process (for example, plasma treatment).
- the semiconductor region located between the source electrode 14 and the drain electrode 16 the gate facing region 18g and the offset regions 18os and 18od may be collectively referred to as a channel formation region.
- the carrier concentration in the offset regions 18os and 18od may be higher in the vicinity of the source electrode 14 and the drain electrode 16. This is because hydrogen diffused from the source electrode 14 and the drain electrode 16 causes a reducing action in the offset regions 18os and 18od.
- the regions formed of the same oxide semiconductor film and subjected to the same carrier concentration control process including the case where the carrier concentrations of the offset regions 18os and 18od are not completely uniform, It may be expressed as “having substantially the same carrier concentration”.
- the oxide semiconductor layer 18 may contain, for example, at least one metal element of In, Ga, and Zn.
- the oxide semiconductor layer 18 includes, for example, an In—Ga—Zn—O-based oxide.
- the oxide semiconductor layer 18 can be formed of an oxide semiconductor film containing an In—Ga—Zn—O-based semiconductor.
- the In—Ga—Zn—O-based semiconductor may be either amorphous or crystalline.
- As the crystalline In—Ga—Zn—O-based semiconductor a crystalline In—Ga—Zn—O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable. Note that the crystal structure of a crystalline In—Ga—Zn—O-based semiconductor is disclosed in, for example, Japanese Patent Application Laid-Open No. 2012-134475. For reference, the entire disclosure of Japanese Patent Application Laid-Open No. 2012-134475 is incorporated herein by reference.
- a TFT having an In—Ga—Zn—O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one hundredth of that of an a-Si TFT). It is suitably used as a drive TFT and a pixel TFT.
- the oxide semiconductor layer 18 may contain another oxide instead of the In—Ga—Zn—O-based oxide.
- Zn—O (ZnO), In—Zn—O (IZO), Zn—Ti—O (ZTO), Cd—Ge—O, Cd—Pb—O, In—Sn—Zn—O It may also contain a system (eg, In 2 O 3 —SnO 2 —ZnO), an In—Ga—Sn—O-based oxide, or the like.
- the gate facing region 18g and the offset regions 18os and 18od formed from an In—Ga—Zn—O-based semiconductor are in the on period of the TFT 5 (the period in which the on voltage Vgh is applied to the gate electrode 12).
- the source electrode 14 and the drain electrode 16 are formed to be conductive.
- the gate facing region 18g is a main region that does not exhibit an active state when the off voltage Vgl is applied and exhibits an active state when the on voltage Vgh is applied. Is a region where the value rises significantly.
- the offset regions 18 os and 18 od are regions where the conductivity does not substantially change when the off voltage Vgl is applied or when the on voltage Vgh is applied.
- the offset regions 18 os and 18 od originally have relatively high carrier concentrations.
- the conductivity is high regardless of whether the TFT is on or off. Therefore, the offset regions 18os and 18od function as a source-drain channel together with the gate facing region 18g when the TFT is on. Note that the conductivity of the portions near the gate electrode 12 in the offset regions 18os and 18od may be improved when the on-voltage Vgh is applied.
- the carrier concentration in the gate facing region 18g and the offset regions 18os and 18od is set to be relatively high. Specifically, the carrier concentration of the gate facing region 18g and the offset regions 18os and 18od is set to 1 ⁇ 10 17 / cm 3 or more and 1 ⁇ 10 19 / cm 3 or less.
- the carrier concentration is set in the above range is that when the carrier concentration is less than 1 ⁇ 10 17 / cm 3 , it is difficult to increase the on-current because the resistance of the oxide semiconductor layer is too high. . Further, when the carrier concentration exceeds 1 ⁇ 10 19 / cm 3 , the resistance of the oxide semiconductor layer becomes low, but the threshold voltage Vth of the TFT also becomes low, and sufficient off performance cannot be obtained in the voltage range for driving the TFT. Off-leakage current increases. For this reason, when the carrier concentration is less than 1 ⁇ 10 17 / cm 3 or more than 1 ⁇ 10 19 / cm 3 , the on / off ratio of the TFT (drain current value when TFT is on / drain current when TFT is off) Value).
- a more preferable range of the carrier concentration in the region is 3 ⁇ 10 17 / cm 3 or more and 3 ⁇ 10 18 / cm 3 or less, and thus the carrier concentration of the oxide semiconductor layer is set to an appropriate range.
- the off-leak current can be suppressed while securing a sufficient on-current.
- a better on / off ratio (for example, 6.7 or more) can be realized.
- the carrier concentration is not uniform, and a concentration profile that is not constant along the channel length direction may be formed.
- the carrier concentration may exceed 1 ⁇ 10 19 / cm 3 in a part of the offset regions 18 os and 18 od.
- the carrier concentration of the oxide semiconductor layer can be measured using, for example, a Hall element. More specifically, a Hall element including an oxide semiconductor layer formed by employing a manufacturing process similar to that of the oxide semiconductor layer included in the TFT is manufactured, and the carrier of the oxide semiconductor layer is determined based on the element characteristics. Measure the concentration. At this time, by obtaining the relationship between the characteristics (for example, on / off ratio) of the TFT including the oxide semiconductor layer manufactured by the same process and the carrier concentration obtained from the corresponding Hall element, the oxidation in the TFT is performed. It is possible to know the relationship between the carrier concentration of the physical semiconductor layer and the TFT characteristics.
- the channel width and channel length in the TFT 5 will be described.
- the channel width is the same as the width of the gate facing region 18 g (here, the width of the oxide semiconductor layer 18) defined in a direction orthogonal to the source / drain direction (channel length direction), for example, 2 ⁇ m. ⁇ 10 ⁇ m.
- the channel length is equivalent to the length of the gate facing region 18g (here, equivalent to the width of the gate electrode 12) defined in a direction parallel to the source / drain direction (channel length direction), for example, 2 ⁇ m. ⁇ 10 ⁇ m.
- the length of the offset regions 18os and 18od in the channel length direction is, for example, 0.5 ⁇ m to 15 ⁇ m. In particular, it is preferable to make the length of the offset regions 18os and 18od within three times the channel width in order to realize a high on / off ratio.
- the operating speed of the TFT can be increased and the feedthrough voltage can be extremely reduced.
- the source and drain can be appropriately conducted when the TFT is on. it can. For example, it was confirmed that a sufficient on / off ratio can be ensured even when the length of the offset regions 18os and 18od is 15 ⁇ m and the channel width is 5 ⁇ m.
- the TFT 5 of this embodiment has a bottom-gate configuration, and the gate electrode 12 functions as a light-shielding layer, whereby light to the activation region (gate facing region 18g) of the oxide semiconductor layer 18 is transmitted. Since irradiation is prevented, there is an advantage that it is not necessary to separately provide a light shielding layer in order to stabilize TFT characteristics.
- the depletion type TFT is a TFT in which the drain current Id has a substantial magnitude (an inversion layer is formed) when the gate-source voltage Vgs (here, the gate voltage Vg) is 0V. is there.
- Vgs gate-source voltage
- the voltage Vgl applied to the gate electrode 12 during the off period is usually negative. The voltage is controlled (for example, ⁇ 10V to ⁇ 15V).
- FIG. 2A shows the case where the TFT 5 is used and the case where the TFT of the reference example in which the carrier concentration of the oxide semiconductor layer is set relatively low (less than 1 ⁇ 10 17 / cm 3 ) is used.
- Vg [V] gate voltage
- Id drain current
- the carrier concentration in the channel is set to 1 ⁇ 10 17 / cm 3 or more and 1 ⁇ 10 19 / cm 3 or less. As described above, it was found that the on / off ratio can be sufficiently increased to 6 or more even if the offset regions 18os and 18od are included in order to reduce the parasitic capacitance.
- the TFT of the present embodiment is configured with the source electrode 14 and the drain electrode 16.
- a bottom contact type in which the oxide semiconductor layer 18 is provided as an upper layer may be employed.
- the source electrode 14 and the drain electrode 16 are provided apart from the gate electrode 12 when viewed from the normal direction of the substrate, and the oxide semiconductor layer 18 includes a region overlapping with the gate electrode 12, A region (offset region) that does not overlap any of the electrode 12, the source electrode 14, and the drain electrode 16.
- FIGS. 3A to 3D and (a ′) and (b ′).
- 3A and 3B correspond to the plan views of FIGS. 3A and 3B.
- a gate metal film is formed on a transparent insulating substrate 10 such as a glass substrate or a plastic substrate shown in FIG.
- a film containing a metal such as Mo, Ti, Al, Ta, Cr, Au, W, Cu or an alloy thereof can be used as appropriate.
- the gate metal film may be formed with a thickness of, for example, 100 nm to 500 nm using a sputtering apparatus.
- the gate metal film may have a laminated structure (for example, Ti / Al / Ti). Thereafter, this is patterned by a known photolithography process, and an etching process by a known dry method or wet method is performed.
- a gate wiring layer including the gate electrode 12 and the gate bus line (not shown) is formed as shown in FIG.
- a gate insulating layer 20 is formed so as to cover the gate wiring layer including the gate electrode 12.
- the gate insulating layer 20 for example, a silicon oxide (SiO 2 ) layer or a silicon nitride (SiN x ) layer can be used.
- the gate insulating layer 20 can be formed with a thickness of 300 nm to 400 nm at a temperature of 300 ° C. to 400 ° C. using a plasma CVD apparatus.
- an oxide semiconductor film is formed on the gate insulating layer 20 by sputtering, for example, at a temperature of 200 ° C. to 400 ° C. to a thickness of 20 nm to 100 nm.
- the island-shaped oxide semiconductor layer 18 is typically obtained by patterning the formed oxide semiconductor film by a photolithography process. Note that the oxide semiconductor film may be formed by a coating process.
- the oxide semiconductor layer 18 is provided so that a part thereof overlaps the gate electrode 12 and a part thereof does not overlap the gate electrode 12 with the gate insulating layer 20 interposed therebetween.
- the oxide semiconductor film may be, for example, an In—Ga—Zn—O-based semiconductor film.
- other various oxide semiconductor films such as IZO and ZnO may be used.
- a metal film for forming a source / drain layer including source / drain electrodes (a film including a metal such as Mo, Ti, Al, Ta, Cr, Au, W, Cu, or an alloy thereof, or a metal nitride thereof)
- the source / drain layer including the source electrode 14 and the drain electrode 16 is formed by patterning by a photolithography technique using a sputtering apparatus. obtain.
- the metal film may have a laminated structure (for example, Ti / Al / Ti).
- the source electrode 14 and the drain electrode 16 are in contact with a part (end portion) of a region of the oxide semiconductor layer 18 that does not overlap with the gate electrode 12 as shown in FIG. Formed as follows.
- the source electrode 14 and the drain electrode 16 are provided at positions separated from the gate electrode 12 by a predetermined distance.
- the source-side offset region 18 os that does not overlap the gate electrode 12 and the source electrode 14, and the gate electrode 12 and the drain electrode 16 do not overlap on both sides of the gate facing region 18 g that overlaps with the gate electrode 12 in the oxide semiconductor layer 18.
- a drain side offset region 18od is formed.
- the present invention is not limited thereto.
- the source electrode 14 and the drain electrode 16 may be electrically connected to the oxide semiconductor layer 18.
- a part of the lateral edge of the oxide semiconductor layer 18 and the edges of the source electrode 14 and the drain electrode 16 are The form which touches may be sufficient.
- plasma treatment for controlling the carrier concentration of the oxide semiconductor layer 18 is performed.
- the plasma treatment can be realized, for example, by plasma irradiation using a reducing gas such as hydrogen gas or argon gas in a plasma CVD apparatus.
- a reducing gas such as hydrogen gas or argon gas in a plasma CVD apparatus.
- the carrier concentration in the gate facing region 18g and the offset regions 18os and 18od in the oxide semiconductor layer 18 is controlled in the range of 1 ⁇ 10 17 / cm 3 to 1 ⁇ 10 19 / cm 3 .
- the hydrogen gas flow rate is set to 100 to 1000 sccm
- the substrate temperature is set to 200 to 300 ° C.
- the RF power is set to 100 to 200 W
- the pressure is set to 50 to 200 Pa.
- the plasma treatment is performed for 30 s to 200 s. Just do it.
- the carrier concentration of the oxide semiconductor layer 18 can be set in the above range by performing an annealing treatment at a temperature of 200 to 300 ° C. in an air atmosphere for 0.5 to 2 hours. Note that in the case where plasma treatment is not performed, the carrier concentration of the oxide semiconductor layer is usually 1 ⁇ 10 16 / cm 3 or less.
- the plasma treatment Besides, ion doping gate facing region by implanting hydrogen ions through the device 18g and the offset region 18os, 1 ⁇ carrier concentration of 18od 10 17 / cm 3 ⁇ 1 ⁇ 10 19 / It can be controlled within the range of cm 3 .
- Patent Document 4 describes a specific method for reducing the resistance of an oxide semiconductor (plasma treatment) and a mechanism for reducing the electrical resistance of the oxide semiconductor. Also in this embodiment, the process described in Patent Document 4 can be used to control the carrier concentration. For reference, the entire disclosure of Patent Document 4 is incorporated herein by reference.
- the oxide semiconductor TFT 5 including the oxide semiconductor layer 18 including the gate facing region 18g and the offset regions 18os and 18od as an active layer is manufactured.
- a passivation layer 22 as a protective layer is provided so as to cover the oxide semiconductor TFT 5.
- the passivation layer 22 is obtained, for example, by forming a silicon oxide film SiO 2 or a silicon nitride film SiN x at a temperature of 200 ° C. to 300 ° C. and a thickness of 200 nm to 500 nm using a plasma CVD apparatus.
- the passivation layer 22 may have a laminated structure of a SiO 2 film and a SiN x film. When the SiO 2 film is disposed on the lower layer side in contact with the oxide semiconductor layer 18 in the stacked structure, oxygen deficiency in the oxide semiconductor layer 18 can be prevented.
- a heat treatment step may be performed in dry air or in the atmosphere, for example, at a temperature of 200 ° C. to 400 ° C. for 1 to 2 hours.
- the carrier concentration may be controlled by performing plasma treatment.
- the carrier concentration in the source connection region 18s and the drain connection region 18d shown in FIG. 3C is also controlled in the same manner as other regions.
- FIG. 4A shows an enlarged view of the vicinity of the region where the TFT 5 is formed in one pixel of the TFT substrate 110 used in the liquid crystal display device.
- the liquid crystal display device has a plurality of pixels arranged in a matrix having a row direction and a column direction.
- the TFT substrate 110 has a plurality of regions (hereinafter referred to as “pixel regions”) corresponding to a plurality of pixels of the display device.
- the TFT substrate 110 is provided with a plurality of source bus lines 4 extending substantially in parallel in the column direction and a plurality of gate bus lines 2 extending substantially in parallel in the row direction.
- the row direction and the column direction may be orthogonal to each other.
- the row direction and the column direction may be a horizontal direction and a vertical direction on the display surface of the liquid crystal display device, respectively.
- each of the pixel regions of the TFT substrate 110 is provided with a TFT 5 and a pixel electrode 19 connected to the gate bus line 2 and the source bus line 4.
- the pixel electrode 19 is made of a transparent conductive material, for example, ITO (indium tin oxide).
- the pixel electrode 19 is connected to the drain electrode 16 of the TFT 5 in a pixel contact hole CH formed in an insulating layer (for example, the above-described passivation layer and organic interlayer insulating layer) covering the TFT 5.
- FIG. 4A shows pixel electrodes 19 of two pixels adjacent to each other with the gate bus line 2 interposed therebetween.
- the pixel electrode 19 of the lower pixel of the gate bus line 2 is arranged so as to overlap the source-side offset region 18os of the oxide semiconductor layer 18 included in the TFT 5 of the upper pixel. Yes.
- the liquid crystal display device of this embodiment may be provided with an auxiliary capacitor that is electrically connected in parallel with the liquid crystal capacitor via an interlayer insulating layer.
- the pixel configuration in the present embodiment may be the same as the configuration of a known liquid crystal display device.
- the gate electrode 12 may be formed by patterning from the same conductive film as the gate bus line 2.
- the gate electrode 12 only needs to be electrically connected to the gate bus line 2 and may be a part of the gate bus line 2 as shown in FIG. In this configuration, a portion of the gate bus line 2 that overlaps with the oxide semiconductor layer 18 of the TFT 5 functions as the gate electrode 12.
- the source electrode 14 and the drain electrode 16 may be formed by patterning from the same conductive film as the source bus line 4.
- the source electrode 14 only needs to be electrically connected to the source bus line 4, and may be a part of the source bus line 4, for example, as shown in FIG. In this configuration, a portion of the source bus line 4 that is in contact with the oxide semiconductor layer 18 of the TFT 5 functions as the source electrode 14.
- the drain electrode 16 is formed so as to be in contact with the oxide semiconductor layer 18 and at least partially overlap the inner region of the contact hole CH.
- the channel region of the TFT 5 and the source / drain connection region can be arranged apart from each other, the parasitic capacitance of the TFT 5 can be reduced.
- the oxide semiconductor layer 18 has a light-transmitting property, the offset regions 18os and 18od can be used as a display region (for example, a region where the pixel electrode 19 and the offset region 18os overlap is also used as a display region. Can do). For this reason, the light shielding region can be made relatively small in the region where the TFT 5 is formed, and the aperture ratio can be further increased.
- FIG. 4B shows the configuration of the TFT 5B of the reference example.
- the TFT 5B is provided at the intersection of the gate bus line 2B and the source bus line 4B.
- the gate electrode 12B connected to the gate bus line 2B is formed so as to overlap the entire oxide semiconductor layer 18B.
- the aperture ratio decreases.
- a contact region between the drain electrode 16B and the pixel electrode 19B is provided at a location apart from the channel. As a result, the area of the light shielding portion that can be placed in the pixel region is increased. Therefore, it has been difficult to improve the aperture ratio.
- the display area can be enlarged while reducing the parasitic capacitances Cgs and Cgd.
- the TFT substrates 100 and 110 according to the first embodiment of the present invention have been described.
- the offset region 18os of the oxide semiconductor layer 18 in which the gate electrode 12 and the source and drain electrodes 14 and 16 are sufficiently reduced in resistance are provided. Since it is a configuration separated by 18 od, the parasitic capacitance can be reduced while increasing the on / off ratio. Further, when used in a liquid crystal display device, the aperture ratio can be improved, and a decrease in pixel voltage due to a feedthrough voltage can be suppressed.
- FIG. 5A is a plan view showing the TFT substrate 200 of Embodiment 2
- FIG. 5B is a cross-sectional view taken along the line AB in FIG. 5A.
- the TFT substrate 200 of the second embodiment includes a TFT 52 provided on the substrate 10.
- 5A and 5B show only one TFT 52, it goes without saying that a plurality of TFTs 52 may be provided on the TFT substrate 200.
- the main difference between the TFT substrate 200 of this embodiment and the TFT substrate 100 of Embodiment 1 is that an etch stop layer 24 is provided so as to cover the gate facing region 18 g of the oxide semiconductor layer 18. .
- the etch stop layer 24 is provided to protect the gate facing region 18g in the etching process of the source / drain layer. Since the other configuration of the TFT substrate 200 is the same as that of the TFT substrate 100 of the first embodiment, the same reference numerals are given and detailed description may be omitted.
- the TFT 52 has a bottom gate structure, and includes a gate electrode 12 provided on the insulating substrate 10, a gate insulating layer 20 covering the gate electrode 12, and the gate insulating layer 20.
- a typical island-shaped oxide semiconductor layer 18 is provided.
- the source electrode 14 and the drain electrode 16 of the TFT 52 are provided apart from the gate electrode 12 when viewed from the substrate normal direction.
- the oxide semiconductor layer 18 may include, for example, an In—Ga—Zn—O-based oxide, or may include other various oxide semiconductors described above. .
- the oxide semiconductor layer 18 includes the gate facing region 18g, which is a region overlapping with the gate electrode 12 when viewed from the substrate normal direction, and the source electrode 14.
- the source side offset region 18os located between the source connection region 18s and the gate facing region 18g, and the drain side offset region located between the drain connection region 18d and the gate facing region 18g. 18 od.
- the offset regions 18 os and 18 od are regions that do not overlap the gate electrode 12, the source electrode 14, and the drain electrode 16.
- the carrier concentration of the entire oxide semiconductor layer 18 may be substantially the same.
- the entire oxide semiconductor layer 18 is formed of the same oxide semiconductor film and is subjected to the same carrier concentration control process (for example, plasma treatment).
- the resistance of the source connection region 18s and the drain connection region 18d may be reduced due to the influence of the source electrode 14 and the drain electrode 16 that are in contact with each other.
- the carrier concentration in the gate facing region 18g of the oxide semiconductor layer 18 and the carrier concentration in other regions differ depending on the addition of a low resistance process performed excluding the gate facing region 18g. It may be a thing.
- the carrier concentration in the gate facing region 18g and the offset regions 18os and 18od is set to 1 ⁇ 10 17 / cm 3 or more and 1 ⁇ 10 19 / cm 3 or less in order to obtain a sufficient on-current.
- it is sufficient carrier concentration of at least the gate facing region 18g is set to the above range, the offset region 18Os, the carrier concentration of 18od may not exceed the 1 ⁇ 10 19 / cm 3. That is, the carrier concentration in the offset regions 18os and 18od may be 1 ⁇ 10 17 / cm 3 or more.
- the carrier concentration of the source connection region 18s and the drain connection region 18d may also be 1 ⁇ 10 17 / cm 3 or more.
- the carrier concentration in the offset regions 18os and 18od and the source / drain connection regions 18s and 18d may be higher than 1 ⁇ 10 19 / cm 3 as described above, but a normal low resistance process is used. in the case, for example, it may be set below 1 ⁇ 10 21 / cm 3.
- the carrier concentration of the oxide semiconductor layer 18 within an appropriate range, it is possible to suppress the off-leak current while securing a sufficient on-current. Thereby, a favorable on / off ratio can be obtained.
- an island-shaped etch stop layer 24 made of an insulating material such as SiO 2 or SiN x is provided Yes.
- the etch stop layer 24 functions so as not to cause etching damage to the gate facing region 18g which is a channel region of the oxide semiconductor layer in the step of forming the source electrode 14 and the drain electrode 16.
- the etch stop layer 24 is provided so as not to cover the offset regions 18os and 18od.
- the present invention is not limited to this, and the etch stop layer 24 is provided so as to cover the offset regions 18os and 18od. It may be.
- the carrier concentration of the gate facing region 18g of the oxide semiconductor layer 18 and the offset regions 18os and 18od are different. Therefore, the conductivity of the offset regions 18os and 18od can be further increased.
- the island-shaped etch stop layer 24 is provided at a position corresponding to the gate facing region 18g (or the gate electrode 12).
- the etch stop layer 24 may be provided so as to cover the entire TFT 52.
- a contact hole is formed in the etch stop layer 24 in a region corresponding to the source connection region 18 s and the drain connection region 18 d of the oxide semiconductor layer 18, and the source electrode 14 and the drain electrode 16 pass through the contact hole. Are connected to the source connection region 18s and the drain connection region 18d.
- the TFT 52 is also typically a depletion type, and the drain current Id has a substantial magnitude when the gate-source voltage Vgs is 0V.
- the TFT 52 may also be controlled so that the off electrode Vgl applied to the gate electrode 12 becomes a negative voltage during the TFT off period.
- 6A and 6C correspond to the plan views of FIGS. 6A and 6C.
- a gate metal film is formed on a transparent insulating substrate 10 such as a glass substrate or a plastic substrate shown in FIG. 6A, and is patterned by a known photolithography method to form the gate electrode 12 (FIG. 6 ( A gate wiring layer including a) and (a ′)) is formed. Thereafter, a gate insulating layer 20 is formed so as to cover the gate wiring layer as shown in FIG.
- a transparent insulating substrate 10 such as a glass substrate or a plastic substrate shown in FIG. 6A
- an oxide semiconductor film is formed on the gate insulating layer 20 with a thickness of, for example, 20 to 100 nm by a sputtering apparatus or the like, this is patterned by photolithography.
- an island-shaped oxide semiconductor layer 18 is formed.
- plasma treatment for controlling the carrier concentration of the formed oxide semiconductor layer 18 is performed.
- the plasma treatment can be realized by, for example, plasma irradiation using a reducing gas such as hydrogen gas or argon gas in a plasma CVD apparatus.
- the carrier concentration of the entire oxide semiconductor layer 18 is controlled in the range of 1 ⁇ 10 17 / cm 3 to 1 ⁇ 10 19 / cm 3 .
- the oxide semiconductor layer forming process and the carrier concentration control process may be the same as the manufacturing process of the TFT substrate 100 of Embodiment 1 described with reference to FIG.
- a silicon oxide film SiO 2 is formed at a temperature of 300 ° C. to 400 ° C. by using, for example, a plasma CVD apparatus.
- An island-like etch stop layer 24 is provided by patterning using a photolithography method. At this time, the etch stop layer 24 is preferably provided so as to cover at least most of the gate facing region 18g (channel region) of the oxide semiconductor layer.
- a source film including the source electrode 14 and the drain electrode 16 is formed by forming a metal film for forming the source / drain layer including the source / drain electrode by using, for example, a sputtering apparatus and patterning the metal film by a photolithography method. -Obtain a drain layer. This process may be the same as the manufacturing process of the TFT substrate 100 of Embodiment 1 described with reference to FIG.
- a portion where the source electrode 14 and the drain electrode 16 are formed (that is, a portion overlapping the source connection region 18s and the drain connection region 18d of the oxide semiconductor layer 18) is covered with a photoresist with respect to the metal film.
- Etching is performed in a broken state.
- the metal film removed by etching includes a portion of the metal film that overlaps the gate facing region 18g of the oxide semiconductor layer 18 and a portion that overlaps the offset regions 18os and 18od.
- the etch stop layer 24 covers the gate facing region 18g of the oxide semiconductor layer 18, damage in the etching process is prevented from reaching the gate facing region 18g. Therefore, in the gate facing region 18g, the carrier concentration controlled by the plasma processing in the previous process is maintained substantially as it is.
- the carrier concentration of the offset regions 18 os and 18 od that are not covered with the etch stop layer 24 can be changed by etching.
- the carrier concentration in the offset regions 18os and 18od increases due to plasma damage to the oxide semiconductor layer. This is considered to be caused by plasma damage increasing oxygen defects in the offset regions 18os and 18od.
- the carrier concentration in the offset regions 18os and 18od becomes larger than the carrier concentration in the gate facing region 18g.
- a passivation layer 22 as a protective layer is provided so as to cover the oxide semiconductor TFT 52.
- This process may also be the same as the manufacturing process of the TFT substrate 100 of Embodiment 1 described with reference to FIG.
- a heat treatment step of about 1 to 2 hours at a temperature of about 200 ° C. to 400 ° C., for example, may be performed in dry air or air. Good.
- the manufacturing process of the TFT substrate 200 of Embodiment 2 was demonstrated, another aspect may be sufficient.
- additional plasma treatment may be performed.
- the carrier concentration of the offset regions 18os, 18od, the source connection region 18s, and the drain connection region 18d is further improved to reduce the resistance. be able to.
- an additional plasma treatment may be performed after the source electrode 14 and the drain electrode 16 are formed.
- FIG. 7 shows an area corresponding to approximately one pixel in the TFT substrate 210 used in the liquid crystal display device.
- the liquid crystal display device includes a plurality of pixels arranged in a matrix having a row direction and a column direction
- the TFT substrate 210 includes a plurality of pixel regions corresponding to the plurality of pixels of the display device. have.
- the TFT substrate 210 is provided with a plurality of source bus lines 4 extending substantially parallel to the column direction and a plurality of gate bus lines 2 extending substantially parallel to the row direction.
- a TFT 52 and a pixel electrode (not shown) connected to the gate bus line 2 and the source bus line 4 are provided.
- the pixel electrode is electrically connected to the drain electrode 16 of the TFT 52 in a pixel contact hole CH formed in an insulating layer (for example, the above-described passivation layer and organic interlayer insulating layer) covering the TFT 52.
- the gate electrode of the TFT 52 may be a part of the gate bus line 2. In this configuration, a portion of the gate bus line 2 that overlaps with the oxide semiconductor layer 18 of the TFT 52 functions as a gate electrode.
- the source electrode 14 of the TFT 52 may be a part of the source bus line 4.
- a portion of the source bus line 4 that is in contact with the oxide semiconductor layer 18 of the TFT 52 functions as the source electrode 14.
- the drain electrode 16 is in contact with the oxide semiconductor layer 18 and at least partially overlaps the inner region of the contact hole CH.
- the channel region of the TFT 52 and the source / drain connection region can be arranged apart from each other, the parasitic capacitance of the TFT 52 can be reduced. Since the oxide semiconductor layer 18 is typically transparent, the offset regions 18os and 18od can be used for display. For this reason, since the light shielding region can be made relatively small in the region where the TFT 52 is formed, the aperture ratio can be further increased.
- the TFT substrates 200 and 210 according to the second embodiment of the present invention have been described.
- the offset region 18os of the oxide semiconductor layer 18 in which the gate electrode 12 and the source and drain electrodes 14 and 16 are sufficiently reduced in resistance are provided. Since it is a configuration separated by 18 od, the parasitic capacitance can be reduced while increasing the on / off ratio. Further, when used in a liquid crystal display device, the aperture ratio can be improved, and a decrease in pixel voltage due to a feedthrough voltage can be suppressed.
- the carrier concentration in the gate facing region 18g can be easily controlled appropriately. Furthermore, in this embodiment, it is relatively easy to make the resistance lower by setting the carrier concentration in the offset regions 18os and 18od higher than the carrier concentration in the gate facing region 18g. For this reason, the on-current can be easily increased, and the on / off ratio can be improved.
- FIG. 8A is a plan view showing the TFT substrate 300 of the third embodiment
- FIG. 8B is a cross-sectional view taken along the line AB in FIG. 8A.
- the TFT substrate 300 of Embodiment 3 includes a TFT 53 provided on the substrate 10.
- 8A and 8B show only one TFT 53, it goes without saying that a plurality of TFTs 53 may be provided on the TFT substrate 300.
- the TFT 53 has a top gate type structure.
- the gate electrode 12 is formed of the oxide semiconductor layer 18. It is provided in the upper layer.
- the top gate TFT 53 provided on the TFT substrate 300 includes an oxide semiconductor layer 18 provided on the insulating substrate 10, a gate insulating layer 20 covering the oxide semiconductor layer 18, and gate insulation.
- the gate electrode 12 is provided over the layer 20 so as to overlap with at least part of the oxide semiconductor layer 18.
- the oxide semiconductor layer 18 may include, for example, an In—Ga—Zn—O-based oxide, or may include other various oxide semiconductors described above. .
- An interlayer insulating layer 22 ′ is provided on the gate electrode 12. Further, a source electrode 14 and a drain electrode 16 are provided on the interlayer insulating layer 22 ′. The source electrode 14 and the drain electrode 16 are connected to the source connection region 18s and the drain of the oxide semiconductor layer 18 through contact holes CH1 and CH2 provided so as to penetrate the interlayer insulating layer 22 ′ and the gate insulating layer 20, respectively. Each is connected to the connection area 18d. Further, the source electrode 14 and the drain electrode 16 are provided away from the gate electrode 12 when viewed from the normal direction of the substrate.
- the oxide semiconductor layer 18 includes a gate facing region 18g that overlaps the gate electrode 12 when viewed from the substrate normal direction, and the source electrode 14.
- the source side offset region 18os located between the source connection region 18s and the gate facing region 18g, and the drain side offset region located between the drain connection region 18d and the gate facing region 18g. 18 od.
- the offset regions 18 os and 18 od are regions that do not overlap the gate electrode 12, the source electrode 14, and the drain electrode 16.
- the carrier concentration of the entire oxide semiconductor layer 18 may be substantially the same.
- the entire oxide semiconductor layer 18 is formed of the same oxide semiconductor film and is subjected to the same carrier concentration control process (for example, plasma treatment).
- the resistance of the source connection region 18s and the drain connection region 18d may be reduced due to the influence of the source electrode 14 and the drain electrode 16 that are in contact with each other.
- the carrier concentration in the gate facing region 18g of the oxide semiconductor layer 18 and the carrier concentration in other regions differ depending on the addition of a low resistance process performed excluding the gate facing region 18g. It may be a thing.
- the carrier concentration of the gate facing region 18g and the offset regions 18os and 18od is set to 1 ⁇ 10 17 / cm 3 or more and 1 ⁇ 10 19 / cm 3 or less.
- the carrier concentration of at least the gate facing region 18g is only to be set in the above range, the offset region 18Os, the carrier concentration of 18od may not exceed the 1 ⁇ 10 19 / cm 3. That is, the carrier concentration in the offset regions 18os and 18od may be 1 ⁇ 10 17 / cm 3 or more.
- the carrier concentration of the oxide semiconductor layer 18 within an appropriate range, it is possible to suppress the off-leak current while securing a sufficient on-current. Thereby, a favorable on / off ratio can be obtained.
- the TFT 53 is also typically a depletion type TFT, and the drain current Id has a substantial magnitude when the gate-source voltage Vgs is 0V. Also in the TFT 53, the off electrode Vgl applied to the gate electrode 12 during the TFT off period may be controlled to be a negative voltage.
- FIGS. 9A to 9D, 9B, and 9D an example of a manufacturing method of the TFT substrate 300 according to the present embodiment will be described with reference to FIGS. 9A to 9D, 9B, and 9D.
- 9B 'and 9D' correspond to the plan views of FIGS. 9B and 9D.
- an oxide semiconductor film is typically formed on a transparent insulating substrate 10 such as a glass substrate or a plastic substrate, and is patterned by a photolithography method, thereby typically forming an island shape.
- the oxide semiconductor layer 18 is formed.
- a base coat layer (not shown) made of SiN x or the like is formed on the insulating substrate 10 and then the oxide semiconductor film is formed. It may be formed.
- plasma treatment for controlling the carrier concentration of the formed oxide semiconductor layer 18 is performed.
- the plasma treatment can be realized by, for example, plasma irradiation using a reducing gas such as hydrogen gas or argon gas in a plasma CVD apparatus.
- a reducing gas such as hydrogen gas or argon gas
- the carrier concentration of the entire oxide semiconductor layer 18 is controlled in the range of 1 ⁇ 10 17 / cm 3 to 1 ⁇ 10 19 / cm 3 .
- the oxide semiconductor layer forming process and the carrier concentration control process may be the same as the manufacturing process of the TFT substrate 100 of Embodiment 1 described with reference to FIG.
- the present invention is not limited thereto, and the plasma treatment is performed after the oxide semiconductor film is formed and before the patterning is performed.
- the oxide semiconductor layer 18 may be formed after the carrier concentration is controlled by the above.
- a gate insulating layer 20 is formed so as to cover the oxide semiconductor layer 18, and a gate metal film is further formed on the gate insulating layer 20.
- a gate wiring layer including the gate electrode 12 is formed by patterning this by a known photolithography method.
- the step of forming the gate insulating layer 20 and the step of forming the gate wiring layer may be the same as the manufacturing steps of the TFT substrate 100 of the first embodiment described with reference to FIG.
- gate electrode 12 overlaps only part of the oxide semiconductor layer 18.
- the gate electrode 12 is typically formed so as to cross the central portion of the oxide semiconductor layer 18, and regions of the oxide semiconductor layer 18 that are not covered with the gate electrode 12 are formed on both sides of the gate electrode 12. .
- an interlayer insulating layer 22 ′ is provided so as to cover the gate wiring layer including the gate electrode 12.
- the interlayer insulating layer 22 ′ is obtained, for example, by forming a silicon oxide film SiO 2 or a silicon nitride film SiN x at a temperature of 300 ° C. to 400 ° C. and a thickness of 200 nm to 500 nm using a plasma CVD apparatus.
- the interlayer insulating layer 22 ′ may have a stacked structure of a SiO 2 film and a SiN x film.
- the source-side contact hole CH1 and the drain-side contact hole CH2 that penetrate the interlayer insulating layer 22 ′ and the gate insulating layer 20 and reach the oxide semiconductor layer 18 are formed as the gate electrode 12. It is formed on both sides across These contact holes CH1 and CH2 can be formed by a photolithography method. In this step, the contact holes CH1 and CH2 are formed so as to overlap a part of the oxide semiconductor layer 18 at a position separated from the gate electrode 12 by a predetermined distance.
- a metal film for forming the source / drain layer is formed using, for example, a sputtering apparatus, and is patterned by a photolithography method, thereby forming the source / drain layer including the source electrode 14 and the drain electrode 16. .
- This process may be the same as the manufacturing process of the TFT substrate 100 of Embodiment 1 described with reference to FIG.
- the source electrode 14 and the drain electrode 16 are connected to the oxide semiconductor layer 18 through the source side contact hole CH1 and the drain side contact hole CH2, respectively.
- the top gate type oxide semiconductor TFT 53 is completed.
- a passivation layer as a protective layer is provided so as to cover the oxide semiconductor TFT 53.
- This process may also be the same as the manufacturing process of the TFT substrate 100 of Embodiment 1 described with reference to FIG.
- a heat treatment step of, for example, 200 ° C. to 400 ° C. for 1 to 2 hours may be performed in dry air or air.
- FIG. 10 shows a region corresponding to approximately one pixel in the TFT substrate 310 used in the liquid crystal display device.
- the liquid crystal display device includes a plurality of pixels arranged in a matrix having a row direction and a column direction
- the TFT substrate 310 includes a plurality of pixel regions corresponding to the plurality of pixels of the display device. have.
- the TFT substrate 310 is provided with a plurality of source bus lines 4 extending substantially in parallel in the column direction and a plurality of gate bus lines 2 extending substantially in parallel in the row direction.
- each of the pixel regions of the TFT substrate 310 is provided with a TFT 53 and a pixel electrode (not shown) connected to the gate bus line 2 and the source bus line 4.
- the pixel electrode is electrically connected to the drain electrode 16 of the TFT 53 in a pixel contact hole CH formed in an insulating layer (for example, the above-described passivation layer and organic interlayer insulating layer) covering the TFT 53.
- the gate electrode may be a part of the gate bus line 2 as shown in FIG. In this configuration, a portion of the gate bus line 2 that overlaps with the oxide semiconductor layer 18 of the TFT 53 functions as a gate electrode.
- the source electrode 14 may be a part of the source bus line 4 as shown in FIG. In this configuration, a portion of the source bus line 4 that is in contact with the oxide semiconductor layer 18 through the source-side contact hole functions as the source electrode 14. In this case, the source bus line 4 may be arranged so as to cover the source side contact hole reaching the oxide semiconductor layer 18.
- the drain electrode 16 is provided so as to be in contact with the oxide semiconductor layer 18 through the drain side contact hole.
- the channel region and the contact region of the TFT 53 can be arranged apart from each other, the parasitic capacitance of the TFT 53 can be reduced. Since the oxide semiconductor layer 18 is typically transparent, the offset regions 18os and 18od can be used for display. For this reason, since the light shielding region can be made relatively small in the region where the TFT 53 is formed, the aperture ratio can be further increased.
- the TFT substrates 300 and 310 have been described.
- the offset region 18os of the oxide semiconductor layer 18 in which the gate electrode 12 and the source and drain electrodes 14 and 16 are sufficiently reduced in resistance are provided. Since it is a configuration separated by 18 od, the parasitic capacitance can be reduced while increasing the on / off ratio. Further, when used in a liquid crystal display device, the aperture ratio can be improved, and a decrease in pixel voltage due to a feedthrough voltage can be suppressed.
- the gate facing region 18g is covered with the gate electrode 12, and the carrier concentration in the gate facing region 18g is unlikely to fluctuate in the formation process of the interlayer insulating layer 22 '. Therefore, there is an advantage that the carrier concentration in the gate facing region 18g can be appropriately controlled.
- the liquid crystal display device includes the TFT substrate described in the first to third embodiments, a counter substrate (for example, a glass substrate), and a liquid crystal layer held between the TFT substrate and the counter substrate.
- a counter electrode is formed on the liquid crystal layer side of the counter substrate, and a voltage is applied to the liquid crystal layer existing between the pixel electrode and the counter electrode of the TFT substrate.
- the An alignment film (for example, a vertical alignment film) may be formed on the liquid crystal layer side of the pixel electrode and the counter electrode as necessary.
- the liquid crystal display device is not limited to the vertical alignment mode (VA mode) liquid crystal display device as described above.
- the liquid crystal display device has a pixel electrode and a counter electrode on a TFT substrate, such as an IPS mode or an FFS mode. It may be a horizontal electric field mode liquid crystal display device. Since the structure of the TFT of the IPS mode or FFS mode liquid crystal display device is well known, description thereof is omitted.
- the TFT substrate described as the first to third embodiments is another display device such as an organic electroluminescence (EL) display device, an inorganic electroluminescence display device, and a MEMS display device. Can also be used.
- EL organic electroluminescence
- MEMS MEMS display device
- a semiconductor device includes a circuit board such as an active matrix substrate, a liquid crystal display device, a display device such as an organic electroluminescence (EL) display device and an inorganic electroluminescence display device, an imaging device such as an image sensor,
- a circuit board such as an active matrix substrate
- a liquid crystal display device such as an organic electroluminescence (EL) display device and an inorganic electroluminescence display device
- an imaging device such as an image sensor
- Gate bus line 4 Source bus line 5 TFT DESCRIPTION OF SYMBOLS 10 Insulating substrate 12 Gate electrode 14 Source electrode 16 Drain electrode 18 Oxide semiconductor layer 18g Gate opposing area
- Gate insulating layer 22 Passivation layer 22 'interlayer insulating layer 24 etch stop layer
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Abstract
Description
図1(a)は、本実施形態1の半導体装置(TFT基板)100を示す平面図であり、図1(b)は、図1(a)中のA-B線に沿った断面図である。
図5(a)は、実施形態2のTFT基板200を示す平面図であり、図5(b)は、図5(a)中のA-B線に沿った断面図である。
図8(a)は、本実施形態3のTFT基板300を示す平面図であり、図8(b)は、図8(a)中のA-B線に沿った断面図である。
4 ソースバスライン
5 TFT
10 絶縁性基板
12 ゲート電極
14 ソース電極
16 ドレイン電極
18 酸化物半導体層
18g ゲート対向領域
18os ソース側オフセット領域
18od ドレイン側オフセット領域
18s ソース接続領域
18d ドレイン接続領域
19 画素電極
20 ゲート絶縁層
22 パッシベーション層
22’ 層間絶縁層
24 エッチストップ層
Claims (12)
- 基板と、
前記基板上に設けられた薄膜トランジスタであって、ゲート電極と、前記ゲート電極に接するゲート絶縁層と、前記ゲート絶縁層を介して前記ゲート電極に部分的に重なるように配置された酸化物半導体層と、前記酸化物半導体層に電気的に接続されたソース電極およびドレイン電極とを有する、薄膜トランジスタと
を備え、
前記ソース電極およびドレイン電極は、基板法線方向から見たときに、前記ゲート電極と離間して設けられており、
前記酸化物半導体層は、
基板法線方向から見たときに、前記ゲート電極と重なるゲート対向領域と、
前記ゲート対向領域に隣接して設けられた少なくとも1つのオフセット領域であって、基板法線方向から見たときに、前記ゲート電極、前記ソース電極、および、前記ドレイン電極のいずれとも重ならないオフセット領域と
を含み、
前記ゲート対向領域のキャリア濃度が、1×1017/cm3以上1×1019/cm3以下である、半導体装置。 - 前記少なくとも1つのオフセット領域のキャリア濃度が、1×1017/cm3以上である、請求項1に記載の半導体装置。
- 前記オフセット領域に隣接して設けられ、前記ソース電極および前記ドレイン電極と接するソース接続領域およびドレイン接続領域を含み、
前記ソース接続領域およびドレイン接続領域のキャリア濃度が、1×1017/cm3以上である、請求項1または2に記載の半導体装置。 - 前記ゲート対向領域のキャリア濃度よりも、前記少なくとも1つのオフセット領域のキャリア濃度の方が高い、請求項1から3のいずれかに記載の半導体装置。
- 前記薄膜トランジスタは、デプレッション型である、請求項1から4のいずれかに記載の半導体装置。
- 前記ゲート電極は、前記ゲート絶縁層を介して、前記酸化物半導体層の下層に設けられている、請求項1から5のいずれかに記載の半導体装置。
- 前記酸化物半導体層の上層において、前記酸化物半導体層の前記ゲート対向領域と少なくとも部分的に重なるように設けられたエッチストップ層をさらに備える、請求項1から6のいずれかに記載の半導体装置。
- 前記ゲート電極は、前記ゲート絶縁層を介して、前記酸化物半導体層の上層に設けられている、請求項1から5のいずれかに記載の半導体装置。
- 前記基板上に、行方向および列方向を有するマトリクス状に配列された複数の画素領域と、それぞれが前記行方向に略平行に延設された複数のゲートバスラインと、それぞれが前記列方向に略平行に延設された複数のソースバスラインとを備え、
前記複数の画素領域のそれぞれは、
前記薄膜トランジスタと、
前記薄膜トランジスタに接続された画素電極とを有し、
前記酸化物半導体層の前記少なくとも1つのオフセット領域は、前記ソースバスラインにおいて形成された前記ソース電極から前記ゲートバスラインまでの間を延び、前記ドレイン電極は、前記ゲートバスラインを挟んで前記ソース電極とは反対側に位置している、請求項1から8のいずれかに記載の半導体装置。 - 前記酸化物半導体層は、In、GaおよびZnのうち少なくとも1種の金属元素を含む、請求項1から9のいずれかに記載の半導体装置。
- 前記酸化物半導体層は、結晶質部分を含む、請求項10に記載の半導体装置。
- 基板を用意する工程と、
前記基板上に、薄膜トランジスタを設ける工程であって、ゲート電極と、前記ゲート電極に接するゲート絶縁層と、前記ゲート絶縁層を介して前記ゲート電極に部分的に重なるように配置された酸化物半導体層と、前記酸化物半導体層に電気的に接続されたソース電極およびドレイン電極とを形成する工程と
を包含し、
前記薄膜トランジスタを設ける工程は、前記酸化物半導体層を形成した後、前記酸化物半導体層のキャリア濃度を変化させ、これによって、前記酸化物半導体層におけるゲート対向領域のキャリア濃度を1×1017/cm3以上1×1019/cm3以下に調整する工程を含む、半導体装置の製造方法。
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JP2013175648A (ja) * | 2012-02-27 | 2013-09-05 | Panasonic Corp | 電界効果トランジスタおよびその製造方法 |
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JP2015109315A (ja) * | 2013-12-03 | 2015-06-11 | 出光興産株式会社 | 薄膜トランジスタ、その製造方法、酸化物半導体層、表示装置及び半導体装置 |
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CN110291644B (zh) * | 2017-02-15 | 2022-11-01 | 夏普株式会社 | 有源矩阵基板 |
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WO2020165698A1 (ja) * | 2019-02-15 | 2020-08-20 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP7487119B2 (ja) | 2019-02-15 | 2024-05-20 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP2021036567A (ja) * | 2019-08-30 | 2021-03-04 | 株式会社ジャパンディスプレイ | 半導体装置 |
WO2021039268A1 (ja) * | 2019-08-30 | 2021-03-04 | 株式会社ジャパンディスプレイ | 半導体装置 |
JP7201556B2 (ja) | 2019-08-30 | 2023-01-10 | 株式会社ジャパンディスプレイ | 半導体装置 |
Also Published As
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US10158027B2 (en) | 2018-12-18 |
CN106415801A (zh) | 2017-02-15 |
JP6416899B2 (ja) | 2018-10-31 |
US20170200827A1 (en) | 2017-07-13 |
CN106415801B (zh) | 2019-12-13 |
JPWO2015186602A1 (ja) | 2017-04-20 |
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