JPWO2015186602A1 - 半導体装置およびその製造方法 - Google Patents
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Abstract
Description
図1(a)は、本実施形態1の半導体装置(TFT基板)100を示す平面図であり、図1(b)は、図1(a)中のA−B線に沿った断面図である。
図5(a)は、実施形態2のTFT基板200を示す平面図であり、図5(b)は、図5(a)中のA−B線に沿った断面図である。
図8(a)は、本実施形態3のTFT基板300を示す平面図であり、図8(b)は、図8(a)中のA−B線に沿った断面図である。
4 ソースバスライン
5 TFT
10 絶縁性基板
12 ゲート電極
14 ソース電極
16 ドレイン電極
18 酸化物半導体層
18g ゲート対向領域
18os ソース側オフセット領域
18od ドレイン側オフセット領域
18s ソース接続領域
18d ドレイン接続領域
19 画素電極
20 ゲート絶縁層
22 パッシベーション層
22’ 層間絶縁層
24 エッチストップ層
Claims (12)
- 基板と、
前記基板上に設けられた薄膜トランジスタであって、ゲート電極と、前記ゲート電極に接するゲート絶縁層と、前記ゲート絶縁層を介して前記ゲート電極に部分的に重なるように配置された酸化物半導体層と、前記酸化物半導体層に電気的に接続されたソース電極およびドレイン電極とを有する、薄膜トランジスタと
を備え、
前記ソース電極およびドレイン電極は、基板法線方向から見たときに、前記ゲート電極と離間して設けられており、
前記酸化物半導体層は、
基板法線方向から見たときに、前記ゲート電極と重なるゲート対向領域と、
前記ゲート対向領域に隣接して設けられた少なくとも1つのオフセット領域であって、基板法線方向から見たときに、前記ゲート電極、前記ソース電極、および、前記ドレイン電極のいずれとも重ならないオフセット領域と
を含み、
前記ゲート対向領域のキャリア濃度が、1×1017/cm3以上1×1019/cm3以下である、半導体装置。 - 前記少なくとも1つのオフセット領域のキャリア濃度が、1×1017/cm3以上である、請求項1に記載の半導体装置。
- 前記オフセット領域に隣接して設けられ、前記ソース電極および前記ドレイン電極と接するソース接続領域およびドレイン接続領域を含み、
前記ソース接続領域およびドレイン接続領域のキャリア濃度が、1×1017/cm3以上である、請求項1または2に記載の半導体装置。 - 前記ゲート対向領域のキャリア濃度よりも、前記少なくとも1つのオフセット領域のキャリア濃度の方が高い、請求項1から3のいずれかに記載の半導体装置。
- 前記薄膜トランジスタは、デプレッション型である、請求項1から4のいずれかに記載の半導体装置。
- 前記ゲート電極は、前記ゲート絶縁層を介して、前記酸化物半導体層の下層に設けられている、請求項1から5のいずれかに記載の半導体装置。
- 前記酸化物半導体層の上層において、前記酸化物半導体層の前記ゲート対向領域と少なくとも部分的に重なるように設けられたエッチストップ層をさらに備える、請求項1から6のいずれかに記載の半導体装置。
- 前記ゲート電極は、前記ゲート絶縁層を介して、前記酸化物半導体層の上層に設けられている、請求項1から5のいずれかに記載の半導体装置。
- 前記基板上に、行方向および列方向を有するマトリクス状に配列された複数の画素領域と、それぞれが前記行方向に略平行に延設された複数のゲートバスラインと、それぞれが前記列方向に略平行に延設された複数のソースバスラインとを備え、
前記複数の画素領域のそれぞれは、
前記薄膜トランジスタと、
前記薄膜トランジスタに接続された画素電極とを有し、
前記酸化物半導体層の前記少なくとも1つのオフセット領域は、前記ソースバスラインにおいて形成された前記ソース電極から前記ゲートバスラインまでの間を延び、前記ドレイン電極は、前記ゲートバスラインを挟んで前記ソース電極とは反対側に位置している、請求項1から8のいずれかに記載の半導体装置。 - 前記酸化物半導体層は、In、GaおよびZnのうち少なくとも1種の金属元素を含む、請求項1から9のいずれかに記載の半導体装置。
- 前記酸化物半導体層は、結晶質部分を含む、請求項10に記載の半導体装置。
- 基板を用意する工程と、
前記基板上に、薄膜トランジスタを設ける工程であって、ゲート電極と、前記ゲート電極に接するゲート絶縁層と、前記ゲート絶縁層を介して前記ゲート電極に部分的に重なるように配置された酸化物半導体層と、前記酸化物半導体層に電気的に接続されたソース電極およびドレイン電極とを形成する工程と
を包含し、
前記薄膜トランジスタを設ける工程は、前記酸化物半導体層を形成した後、前記酸化物半導体層のキャリア濃度を変化させ、これによって、前記酸化物半導体層におけるゲート対向領域のキャリア濃度を1×1017/cm3以上1×1019/cm3以下に調整する工程を含む、半導体装置の製造方法。
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PCT/JP2015/065419 WO2015186602A1 (ja) | 2014-06-03 | 2015-05-28 | 半導体装置およびその製造方法 |
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US10950705B2 (en) * | 2017-02-15 | 2021-03-16 | Sharp Kabushiki Kaisha | Active matrix substrate |
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CN108417580B (zh) * | 2018-01-30 | 2020-12-18 | 上海天马有机发光显示技术有限公司 | 阵列基板及其制作方法和显示面板 |
CN108682693A (zh) * | 2018-05-28 | 2018-10-19 | 深圳市华星光电半导体显示技术有限公司 | 薄膜晶体管 |
JP7199174B2 (ja) * | 2018-07-26 | 2023-01-05 | 東京エレクトロン株式会社 | エッチング方法 |
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