CN102646683B - Array substrate and manufacturing method thereof - Google Patents
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- CN102646683B CN102646683B CN201210022961.3A CN201210022961A CN102646683B CN 102646683 B CN102646683 B CN 102646683B CN 201210022961 A CN201210022961 A CN 201210022961A CN 102646683 B CN102646683 B CN 102646683B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
Abstract
The invention discloses an array substrate and a manufacturing method of the array substrate. The array substrate comprises a substrate plate, a first TFT (thin film transistor) and a second TFT, wherein the first TFT and the second TFT are respectively arranged on the substrate plate, the first TFT is an enhancement type, and the second TFT is a depletion type. The array substrate plate is provided with the enhancement-type first TFT and the depletion-type second TFT at the same time at preset positions so as to exert the functional characteristics; and compared with a single depletion-type TFT or a single enhancement-type TFT of an array substrate in the prior art, the array substrate disclosed by the invention has the advantages of being capable of reducing the set number of TFTs and simplifying circuit wires so as to largely simplify a structure of the whole array substrate, largely improve the stability of the structure and further increase the effective pixel area of the array substrate.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and manufacture method thereof.
Background technology
Thin-film transistor (Thin Film Transistor is called for short TFT) is one of kind of field-effect transistor, is mainly used in panel display apparatus.Thin Film Transistor-LCD (Thin Film TransistorLiquid Crystal Display, be called for short TFT-LCD) have that volume is little, low in energy consumption, manufacturing cost is relatively low and the feature such as radiationless, in current flat panel display market, occupied leading position.AMOLED (Active Matrix Organic Light Emitting Diode, active matrix organic light-emitting diode, is called for short AMOLED) panel, be called as Display Technique of future generation, compare traditional TFT-LCD panel, there is the features such as reaction speed is fast, contrast is high, visual angle is wide.
Oxide semiconductor indium gallium zinc oxygen (InGaZnO4:IGZO) because its mobility is high, good uniformity and the feature such as can at room temperature prepare studied widely, to substituting low temperature polycrystalline silicon (LowTemperature Poly-silicon is called for short LTPS), as the active layer of array base palte, realize the industrialization of large scale AMOLED panel.
Yet, in the middle of prior art, no matter be TFT-LCD display, or AMOLED panel, IGZO semiconductor is as the active layer channel material of array base palte, the characteristic of common its depletion type of single utilization or enhancement mode, this makes the structure (such as sequential control circuit, static electricity prevention and curing circuit etc.) of array base palte comparatively complicated, less stable, and, also can and then have influence on the effective pixel area of array base palte.
Summary of the invention
The invention provides a kind of array base palte and manufacture method thereof, in order to solve in prior art IGZO semiconductor as the active layer channel material of array base palte, can only its depletion type of single utilization or the characteristic of enhancement mode, the structure of array base palte is comparatively complicated, less stable, the technical problem that effective pixel area can not further increase.
Array base palte of the present invention, comprising: underboarding and lay respectively at the first film transistor and the second thin-film transistor on underboarding, and wherein, the first film transistor is enhancement mode, the second thin-film transistor is depletion type.
Wherein, the active layer material of the transistorized active layer of the first film and the second thin-film transistor comprises oxide semiconductor.
Preferably, described oxide semiconductor is indium gallium zinc oxide or hafnium indium-zinc oxide.
Optionally, described array base palte is top gate type or bottom gate type.
Optionally, described array base palte is applied to TFT-LCD panel or AMOLED panel.
The manufacture method of array base palte of the present invention, comprising:
Desired location on underboarding forms the first film transistor and the second thin-film transistor, and wherein, the first film transistor is enhancement mode, and the second thin-film transistor is depletion type.
Described desired location on underboarding forms the first film transistor and the second thin-film transistor comprises:
A, formation material comprise the active layer figure of oxide semiconductor;
B, to forming the substrate of active layer pattern, carry out mask, adjust the oxygen content of the active layer of substrate desired location, form and there is the transistorized active layer of the first film of higher oxygen content and have compared with the active layer of the second thin-film transistor of low oxygen content.
Preferably, described oxide semiconductor is indium gallium zinc oxide or hafnium indium-zinc oxide.
The oxygen content of the active layer of described adjustment substrate desired location comprises atmosphere processing, and described atmosphere is processed the gas adopting and comprised reducibility gas or oxidizing gas, and processing mode comprises thermal annealing or plasma bombardment.
The oxygen content of the active layer of described adjustment substrate desired location comprises the processing of liquid atmosphere, and described liquid atmosphere is processed the liquid adopting and comprised reducing liquid or oxidizing liquid, and processing mode comprises chemical reaction or Elements Diffusion.
The oxygen content of the active layer of described adjustment substrate desired location comprises the processing of solid atmosphere, and described solid atmosphere is processed the solid adopting and comprised reproducibility solid or oxidizability solid, and processing mode comprises chemical reaction or Elements Diffusion.
In technical solution of the present invention, because array base palte has the first film transistor of enhancement mode and the second thin-film transistor of depletion type simultaneously, this thin-film transistor of two types is designed respectively to the desired location in array base palte, bring into play its functional characteristic, in contrast to single depletion type thin-film transistor or the single reinforced membranes transistor of prior art array base palte, can reduce thin-film transistor magnitude setting, simplify circuit trace, the structure of whole array base palte is greatly simplified, structural stability improves greatly, array base palte effective pixel area is also able to further increase.
Accompanying drawing explanation
Fig. 1 is array base-plate structure schematic diagram of the present invention;
Fig. 2 is manufacture method schematic flow sheet of the present invention;
Fig. 3 is array base palte one example structure schematic diagram of the present invention;
Fig. 4 is the manufacture process schematic diagram of the array base palte shown in Fig. 3;
Fig. 5 is the transfer characteristic curve figure of the thin-film transistor of different oxygen on array base palte.
Reference numeral:
10-underboarding 11-grid 12-gate insulator
13a-elevated oxygen level active layer 13b-low oxygen content active layer 14-etching barrier layer
15-source electrode 16-drain electrode 201a-the first film transistor
201b-the second thin-film transistor
Embodiment
In order to solve in prior art IGZO semiconductor as the active layer channel material of array base palte, can only its depletion type of single utilization or the characteristic of enhancement mode, the structure of array base palte is comparatively complicated, less stable, the technical problem that effective pixel area can not further increase, the invention provides a kind of array base palte and manufacture method thereof.
As shown in Figure 1, array base palte of the present invention, comprising: underboarding 10 and lay respectively at the first film transistor 201a and the second thin-film transistor 201b on underboarding 10, wherein, the first film transistor 201a is enhancement mode, and the second thin-film transistor 201b is depletion type.
The active layer material of the active layer of the first film transistor 201a and the second thin-film transistor 201b comprises oxide semiconductor, for example indium gallium zinc oxide (InGaZnO
4) or hafnium indium-zinc oxide (HfInZnO) etc., can do corresponding doping to active layer, to improve the performance of thin-film transistor.In an embodiment of the present invention, oxide semiconductor is preferably indium gallium zinc oxide, has that mobility is high, a good uniformity and the advantage such as can at room temperature prepare.
Array base palte can be top gate type structure or bottom gate type structure, can be coplanar type or anti-communism surface structure for the folded type structure of overlapping type or reciprocal cross, also can prepare high reflection layer at the back side of underboarding, is prepared into top ballistic device.
The material of underboarding 10 can be glass or quartz etc., but is not limited to these transparent materials, also can adopt pottery, metal etc. with preparation top ballistic device.
Array base palte of the present invention can be applicable to TFT-LCD panel or AMOLED panel.
The manufacture method of array base palte of the present invention, comprising:
Desired location on underboarding forms the first film transistor and the second thin-film transistor, and wherein, the first film transistor is enhancement mode, and the second thin-film transistor is depletion type.
Wherein, the desired location that forms the first film transistor and the second thin-film transistor need to design according to function, structure separately, for example, when designing in pixel region and sub-pix district makes driving transistors, can be used for controlling luminosity, but the present invention is never limited to this, for example, can also be for sequential control circuit, or for scan drive circuit and data drive circuit, or for array base palte test section, or for array substrate peripheral static electricity prevention and curing circuit etc.
As shown in Figure 2, when the desired location on underboarding forms the first film transistor and the second thin-film transistor, form active layer and comprise:
Step 101, formation material comprise the active layer figure of oxide semiconductor;
Step 102, to forming the substrate of active layer pattern, carry out mask, adjust the oxygen content of the active layer of substrate desired location, form and there is the transistorized active layer of the first film of higher oxygen content and have compared with the active layer of the second thin-film transistor of low oxygen content.
Oxide semiconductor is preferably indium gallium zinc oxide or hafnium indium-zinc oxide.
The oxygen content of adjusting the active layer of substrate desired location can adopt the mode that atmosphere is processed, liquid atmosphere is processed or solid atmosphere is processed.Atmosphere is processed the gas adopting and is comprised reducibility gas or oxidizing gas, for example H
2, O
2, CH
4deng, processing mode comprises thermal annealing or plasma bombardment etc.Liquid atmosphere is processed the liquid adopting and is comprised reducing liquid or oxidizing liquid, and processing mode comprises chemical reaction or Elements Diffusion, for example, and by the chemical reaction corrosion treatment of watery hydrochloric acid or hydrofluoric acid.Solid atmosphere is processed the solid adopt and is comprised reproducibility solid or oxidizability solid, and processing mode comprises chemical reaction or Elements Diffusion, for example, and by the part of grid pole insulating barrier that contacts with active layer or the heat diffusion treatment of passivation layer.
For example,, when adopting O
2when atmosphere is processed the oxygen content of the active layer of adjusting substrate desired location, concrete steps can be: the substrate of mask is sent into O
2in the annealing furnace of atmosphere, carry out thermal anneal process, annealing temperature is 130 ℃, and annealing time is 1 hour, finally at desired location, forms elevated oxygen level active layer.When adopting H
2when atmosphere is processed the oxygen content of the active layer of adjusting substrate desired location, concrete steps can be: the substrate of mask is sent into H
2in the reactive ion etching equipment of atmosphere, carry out plasma bombardment processing, watt level 2～8kW, in 180 seconds processing times, finally forms low oxygen content active layer at desired location.
In step 101, described formation material comprises the active layer figure of oxide semiconductor, be specially: adopt sputtering method to deposit active tunic layer (for example low oxygen content active layer rete or elevated oxygen level active layer rete), in sputter procedure, the oxygen content of atmosphere is 10%～80%, the deposit thickness of active layer rete is 50 nanometers, then by mask etch process, forms active layer pattern.
As shown in Figure 3, in this embodiment, array base palte adopts bottom gate type structure to one embodiment of array base palte of the present invention, can be used for preparing the array base palte of AMOLED panel or the array base palte of TFT-LCD panel.As shown in Figure 4, the forming process of this array base palte comprises: on transparent substrates plate 10, form successively: buffer insulation layer (not shown), grid 11, gate insulator 12, two kinds of IGZO active layers (being elevated oxygen level active layer 13a and low oxygen content active layer 13b), etching barrier layer 14, source electrode 15 and drain electrode 16, passivation layer (not shown), transparency electrode (not shown) and pixel that after atmosphere is processed, oxygen content is different define a layer (not shown).
It should be noted that, Fig. 3 and Fig. 4 are only for the structure of enhancement mode TFT and depletion type TFT is described, and are not used in the position relationship that limits enhancement mode TFT and depletion type TFT.On actual array base palte, the enhancement mode TFT that comprises elevated oxygen level active layer 13a and the depletion type TFT that comprises low oxygen content active layer 13b might not be adjacent settings; Such as, at the pixel region of liquid crystal indicator, mainly use depletion type TFT, at peripheral circuit area, be that enhancement mode TFT and depletion type TFT collocation are used.
Wherein, the material of transparent substrates plate can be glass or quartz etc.; Grid can adopt the metals such as molybdenum, copper; Gate insulator material can be silicon dioxide, silicon nitride etc.; IGZO active layer is divided into elevated oxygen level and two kinds of active layer regions of low oxygen content; Etching barrier layer can adopt the materials such as silicon dioxide, for preventing that source electrode and drain electrode from causing damage to established IGZO active layer raceway groove when the wet etching; Source electrode and drain electrode can adopt identical material, metals such as molybdenum, aluminium, titanium, copper, or the composite bed of these metals, or the alloy of these metals etc.
The transfer characteristic of the thin-film transistor of different oxygen on array base palte is (when the drain electrode of thin-film transistor and the voltage between source electrode remain unchanged, voltage between grid and source electrode and the relation of drain current are called transfer characteristic, its description be voltage between grid and the source electrode control action to drain current) as shown in Figure 5, wherein, (a) figure is corresponding to the thin-film transistor of the IGZO active layer compared with low oxygen content, this thin-film transistor is depletion type (when input voltage is zero, existing certain drain current exists); (b) figure is corresponding to the thin-film transistor of the IGZO active layer of normal oxygen content, and this thin-film transistor is weak depletion type; (c) figure is corresponding to the thin-film transistor of the IGZO active layer of higher oxygen content, and this thin-film transistor is enhancement mode (when input voltage is zero, drain current is almost nil, needs input voltage to reach certain value and could produce certain drain current).
Manufacture method first embodiment of application array base palte of the present invention prepares the array base palte shown in Fig. 3, and concrete grammar is as follows:
Transparent substrates plate adopts standard method (decomposing ablution, liquid spray ablution or ultrasonic cleaning process etc. such as UV) to clean, and adopts afterwards chemical gaseous phase depositing process cvd silicon dioxide film as buffer insulation layer, and deposit thickness is 200 nanometers;
Adopt afterwards sputtering method deposition gate metal layer, material is molybdenum, and deposit thickness is 200 nanometers, and chemical wet etching goes out required gate patterns;
Adopt chemical gaseous phase depositing process to deposit gate insulator at 370 ℃, material is silicon dioxide again, and deposit thickness is 150 nanometers;
Adopt afterwards sputtering method deposition low oxygen content IGZO active layer rete, in sputter procedure, the oxygen content of atmosphere is 10%～80%, and deposit thickness is about 50 nanometers, and chemical wet etching goes out required active layer figure;
Again by photoetching process, substrate is carried out to mask, substrate is sent into O
2in the annealing furnace of atmosphere, carry out annealing process to change the oxygen content of the IGZO active layer of desired location, annealing temperature is 130 ℃, and annealing time 1 hour finally forms elevated oxygen level active layer at desired location;
And then go out etching barrier layer at desired zone deposition, chemical wet etching, and material is silicon dioxide, thickness is about 50 nanometers;
Adopt afterwards sputtering method sedimentary origin, drain electrode metal level, material is molybdenum or aluminium, and thickness is 200 nanometers, and chemical wet etching goes out required source electrode, drain electrode figure;
Adopt afterwards chemical gaseous phase depositing process to prepare passivation layer, material is silicon dioxide again, and thickness is about 100～500 nanometers, and and then chemical wet etching go out connecting hole;
Sputtering sedimentation transparent electrode layer on passivation layer, and chemical wet etching again goes out pixel region or sub-pix district transparency electrode figure;
Finally spin-on deposition acrylic based material photoetching on backboard, solidify pixel and define layer, thickness is about 1.5 microns, and final formation comprises the array base palte of reinforced membranes transistor and depletion type thin-film transistor simultaneously.
After prepared by array base palte, can be used for continuing preparation AMOLED panel or TFT-LCD panel, take and prepare AMOLED panel as example, follow-up detailed process is: adopt O
2plasma treatment array base palte is surperficial, further promotes the surface work function of transparency electrode, the substrate surface of passivation simultaneously layer; Organic material and anode metal thin layer be thermal evaporation evaporation in organic metal thin film deposition high vacuum system; At 1x10
-5thermal evaporation evaporation hole transmission layer (approximately 170 ℃), organic luminous layer and electron transfer layer (approximately 190 ℃) and negative electrode (approximately 900 ℃) successively under the vacuum of Pa, wherein, hole transmission layer adopts the NPB (N of 50 nanometer thickness, N '-diphenyl-N-N ' two (1-naphthyl)-1,1 ' diphenyl-4,4 '-diamines); Organic luminous layer adopts minute pixel region mask evaporation technique to carry out, and green glow, blue light and ruddiness pixel region adopt respectively Doping Phosphorus luminescent material, and material of main part is the CBP:(ppy of 25 nanometer thickness)
2ir (acac) (4,4 '-N, two (2-phenylpyridine) acetylacetone,2,4-pentanedione iridium), CBP:FIrpic (4,4 '-N, N '-bis-carbazole-biphenyl: two (4 N '-bis-carbazole-biphenyl:, 6-difluorophenyl pyridine-N, C2) pyridine formyl closes iridium) and CBP:Btp2Ir (acac) (4,4 '-N, N '-bis-carbazole-biphenyl: two (2-(2 '-benzos [4,5-a] thienyl) pyridine-N, C30) iridium (acetylacetone,2,4-pentanedione)); Electron transfer layer adopts the Bphen (4,7-diphenyl-1,10-ferrosin) of 25 nanometer thickness; Samarium/the aluminium lamination of approximately 200 nanometer thickness for negative electrode.
This AMOLED panel is full-color light-emitting, and bright dipping mode is end bright dipping.In the array base palte of this AMOLED panel, peripheral circuit and anti-static circuit etc. can be set to dimorphism (comprising enhancement mode and depletion type) thin-film transistor; In sub-pix district, because ruddiness, blue light OLED device luminous efficiency are lower, corresponding driving thin-film transistor adopts low oxygen content IGZO active layer; Green glow OLED device luminous efficiency is higher, and corresponding driving thin-film transistor adopts elevated oxygen level IGZO active layer.
Similar with the first embodiment, manufacture method second embodiment of application array base palte of the present invention prepares the array base palte shown in Fig. 3, and concrete grammar is as follows:
Transparent substrates plate adopts standard method to clean, and adopts afterwards chemical gaseous phase depositing process cvd silicon dioxide film as buffer insulation layer, and deposit thickness is 200 nanometers;
Adopt afterwards sputtering method deposition gate metal layer, material is molybdenum, and deposit thickness is 200 nanometers, and chemical wet etching goes out required gate patterns;
Adopt chemical gaseous phase depositing process to deposit gate insulator at 370 ℃, material is silicon dioxide again, and deposit thickness is 150 nanometers;
Adopt afterwards sputtering method deposition elevated oxygen level IGZO active layer rete, in sputter procedure, the oxygen content of atmosphere is 10%～80%, and deposit thickness is about 50 nanometers, and chemical wet etching goes out required active layer figure;
Again by photoetching process, substrate is carried out to mask, substrate is sent into H
2in the reactive ion etching equipment of atmosphere, carry out plasma-treating technology to change the oxygen content of the IGZO active layer of desired location, watt level 2～8kW, in 180 seconds processing times, finally forms low oxygen content active layer at desired location;
And then go out etching barrier layer at desired zone deposition, chemical wet etching, and material is silicon dioxide, thickness is about 50 nanometers;
Adopt afterwards sputtering method sedimentary origin, drain electrode metal level, material is molybdenum or aluminium, and thickness is 200 nanometers, and chemical wet etching goes out required source electrode, drain electrode figure;
Adopt afterwards chemical gaseous phase depositing process to prepare passivation layer, material is silicon dioxide again, and thickness is about 100～500 nanometers, and and then chemical wet etching go out connecting hole;
Sputtering sedimentation transparent electrode layer on passivation layer, and chemical wet etching again goes out pixel region or sub-pix district transparency electrode figure, and final formation comprises the array base palte of reinforced membranes transistor and depletion type thin-film transistor simultaneously.
Said process is slightly different from process shown in Fig. 4; In the method, first deposition forms elevated oxygen level active layer 13a, by plasma-treating technology, the elevated oxygen level active layer of part is changed into low oxygen content active layer 13b more afterwards.
After prepared by array base palte, can be used for continuing preparation AMOLED panel or TFT-LCD panel, take and prepare TFT-LCD panel as example, subsequent technique is oriented layer coating and impression orientation, and the preparation of parting pad and the preparation of corresponding color membrane substrates, and carry out core, cutting, irrigation crystal and sealing adhesive process.
This TFT-LCD panel is full-color light-emitting.Pixel region and peripheral circuit part can be set to respectively dimorphism (comprising enhancement mode and depletion type) thin-film transistor as required.
In technical solution of the present invention, because array base palte has the first film transistor of enhancement mode and the second thin-film transistor of depletion type simultaneously, this thin-film transistor of two types is designed respectively to the desired location in array base palte, bring into play its functional characteristic, in contrast to single depletion type thin-film transistor or the single reinforced membranes transistor of prior art array base palte, can reduce thin-film transistor magnitude setting, simplify circuit trace, the structure of whole array base palte is greatly simplified, structural stability improves greatly, array base palte effective pixel area is also able to further increase.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (10)
1. an array base palte, it is characterized in that, described array base palte is applied to AMOLED panel, comprise: underboarding and lay respectively at driving the first film transistor of green glow OLED device and driving the second thin-film transistor of ruddiness OLED device and blue light OLED device for correspondence for correspondence on underboarding, wherein, the first film transistor is enhancement mode, and the second thin-film transistor is depletion type.
2. array base palte as claimed in claim 1, is characterized in that, the active layer material of the transistorized active layer of the first film and the second thin-film transistor comprises oxide semiconductor.
3. array base palte as claimed in claim 2, is characterized in that, described oxide semiconductor is indium gallium zinc oxide or hafnium indium-zinc oxide.
4. array base palte as claimed in claim 1, is characterized in that, described array base palte is top gate type or bottom gate type.
5. a manufacture method for array base palte, is characterized in that, described array base palte is applied to AMOLED panel, comprising:
Desired location on underboarding is formed for corresponding the second thin-film transistor that drives the first film transistor of green glow OLED device and drive ruddiness OLED device and blue light OLED device for correspondence, wherein, the first film transistor is enhancement mode, and the second thin-film transistor is depletion type.
6. manufacture method as claimed in claim 5, is characterized in that, described desired location on underboarding forms the first film transistor and the second thin-film transistor comprises:
A, formation material comprise the active layer figure of oxide semiconductor;
B, to forming the substrate of active layer pattern, carry out mask, adjust the oxygen content of the active layer of substrate desired location, form and there is the transistorized active layer of the first film of higher oxygen content and have compared with the active layer of the second thin-film transistor of low oxygen content.
7. manufacture method as claimed in claim 6, is characterized in that, described oxide semiconductor is indium gallium zinc oxide or hafnium indium-zinc oxide.
8. manufacture method as claimed in claim 7, it is characterized in that, the oxygen content of the active layer of described adjustment substrate desired location comprises atmosphere processing, described atmosphere is processed the gas adopting and is comprised reducibility gas or oxidizing gas, and processing mode comprises thermal annealing or plasma bombardment.
9. manufacture method as claimed in claim 7, it is characterized in that, the oxygen content of the active layer of described adjustment substrate desired location comprises the processing of liquid atmosphere, and described liquid atmosphere is processed the liquid adopting and comprised reducing liquid or oxidizing liquid, and processing mode comprises chemical reaction or Elements Diffusion.
10. manufacture method as claimed in claim 7, it is characterized in that, the oxygen content of the active layer of described adjustment substrate desired location comprises the processing of solid atmosphere, described solid atmosphere is processed the solid adopting and is comprised reproducibility solid or oxidizability solid, and processing mode comprises chemical reaction or Elements Diffusion.
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| CN201210022961.3A CN102646683B (en) | 2012-02-02 | 2012-02-02 | Array substrate and manufacturing method thereof |
| PCT/CN2012/084880 WO2013113232A1 (en) | 2012-02-02 | 2012-11-20 | Array substrate and manufacturing method therefor |
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Families Citing this family (8)
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| CN102646683B (en) * | 2012-02-02 | 2014-09-24 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof |
| CN102891108B (en) * | 2012-10-24 | 2015-12-02 | 京东方科技集团股份有限公司 | A kind of manufacture method of array base palte |
| CN103117224A (en) * | 2013-01-21 | 2013-05-22 | 京东方科技集团股份有限公司 | Manufacturing method of thin film transistor and array substrate |
| CN103715196B (en) | 2013-12-27 | 2015-03-25 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN106415801B (en) * | 2014-06-03 | 2019-12-13 | 夏普株式会社 | Semiconductor device and method for manufacturing the same |
| WO2017071662A1 (en) * | 2015-10-29 | 2017-05-04 | 陆磊 | Thin film transistor, manufacturing method therefore, and display panel |
| CN107968095A (en) * | 2017-11-21 | 2018-04-27 | 深圳市华星光电半导体显示技术有限公司 | Carry on the back channel etch type TFT substrate and preparation method thereof |
| CN113257841B (en) * | 2021-07-19 | 2021-11-16 | 深圳市柔宇科技股份有限公司 | TFT substrate and preparation method thereof, display and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101794737A (en) * | 2008-12-26 | 2010-08-04 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
| CN102197490A (en) * | 2008-10-24 | 2011-09-21 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing the same |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4598305A (en) * | 1984-06-18 | 1986-07-01 | Xerox Corporation | Depletion mode thin film semiconductor photodetectors |
| US6613620B2 (en) * | 2000-07-31 | 2003-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US20060138403A1 (en) * | 2004-12-29 | 2006-06-29 | Gang Yu | Organic electronic devices including pixels |
| KR101490112B1 (en) * | 2008-03-28 | 2015-02-05 | 삼성전자주식회사 | Inverter and logic circuit comprising the same |
| CN101609838B (en) * | 2008-06-20 | 2011-12-07 | 群康科技(深圳)有限公司 | Organic light-emitting diode display device and manufacturing method thereof |
| JP5361651B2 (en) * | 2008-10-22 | 2013-12-04 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| CN102646683B (en) * | 2012-02-02 | 2014-09-24 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof |
-
2012
- 2012-02-02 CN CN201210022961.3A patent/CN102646683B/en active Active
- 2012-11-20 WO PCT/CN2012/084880 patent/WO2013113232A1/en active Application Filing
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102197490A (en) * | 2008-10-24 | 2011-09-21 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing the same |
| CN101794737A (en) * | 2008-12-26 | 2010-08-04 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
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| CN102646683A (en) | 2012-08-22 |
| WO2013113232A1 (en) | 2013-08-08 |
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