CN102651343A - Manufacturing method of array substrate, array substrate and display device - Google Patents

Manufacturing method of array substrate, array substrate and display device Download PDF

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CN102651343A
CN102651343A CN2012100718253A CN201210071825A CN102651343A CN 102651343 A CN102651343 A CN 102651343A CN 2012100718253 A CN2012100718253 A CN 2012100718253A CN 201210071825 A CN201210071825 A CN 201210071825A CN 102651343 A CN102651343 A CN 102651343A
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photoresist
film
active layer
substrate
electrode
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CN102651343B (en
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宁策
刘翔
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BOE Technology Group Co Ltd
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Priority to PCT/CN2012/085702 priority patent/WO2013135075A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process

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Abstract

The invention provides a manufacturing method of an array substrate. The manufacturing method comprises the following steps: patterns of a gate electrode (1), an active layer (3), a source electrode (5a), a drain electrode (5b) and a pixel electrode (4) are respectively formed through layout process, wherein the patterns of the source electrode (5a), the drain electrode (5b) and the pixel electrode (4) are formed through once layout process. Correspondingly, the invention provides an array substrate manufactured by the manufacturing method and a display device comprising the array substrate. When the manufacturing method and the array substrate manufactured by the manufacturing method are compared with the prior art, the layout process times is further reduced, i.e. only three times of layout process are adopted, and meanwhile, the deposition process for preparing a transparent conductive film of the pixel electrode is also omitted, so that the production efficiency is improved, and the production cost is reduced.

Description

A kind of manufacture method of array base palte, array base palte and display unit
Technical field
The invention belongs to the display fabrication techniques field, be specifically related to a kind of array base palte manufacture method, adopt array base palte that this method processes and the display unit that comprises said array base palte.
Background technology
Along with the development of display fabrication techniques, LCD Technology development has replaced traditional crt display unit gradually and has become the main flow of following flat-panel monitor rapidly.At present; Most LCDs all are active matrix-type liquid crystal display device (AM-LCD; Active Matrix Liquid Crystal Display), wherein, Thin Film Transistor-LCD (TFT-LCD; Thin Film Transistor LCD) because of having characteristics such as volume is little, low in energy consumption, radiationless, in current flat panel display market, occupied leading position.
Because amorphous silicon (a-Si) is easy to large-area preparation, technology maturation at low temperatures, be the technology of extensive use among the present TFT-LCD, also make the amorphous silicon film transistor LCD become the main flow of present TFT-LCD.But the band gap of amorphous silicon material has only 1.7V; Opaque to visible light; And in visible-range, have light sensitivity, need to increase opaque metal mask plate (black matrix) and stop light, therefore increased the process complexity of TFT-LCD; Improve production cost, reduced the aperture opening ratio of product reliability and unit pixel; Simultaneously,, also need increase the light intensity of backlight, thereby increase the power consumption of product in order to obtain enough brightness.With respect to non-crystalline silicon tft, also have polysilicon (poly-Si) TFT and amorphous silicon hydride (a-Si:H) TFT on the market.Though the polysilicon superior performance, its complicated process of preparation, cost is higher, and is also opaque to visible light simultaneously; And along with the improving constantly of TFT performance, the technology of amorphous silicon hydride is ripe, and its semi-conductive mobility generally is no more than 1cm 2V -1S -1, being difficult to has breakthrough raising again, and existing amorphous silicon hydride TFT has been difficult to satisfy the continuous LCD TV that increases of size and the demand of more high performance drive circuit.
Ohtomo research group reported first in 1997 on Sapphire Substrate, prepare the ZnO film of high crystalline quality, from then on the and phenomenon of this film ultraviolet stimulated emission more and more receives people's attention to the research of this wide band gap semiconducter of ZnO.The ZnO material price is cheap, raw material is sufficient, all harmless and preparation is simple to the environment human body.Theoretical research shows that the wide bandgap semiconductor materials of II～VI family is the hexagonal wurtzite crystal structure under normal conditions, and fusing point height, Heat stability is good, dielectric constant is low, the photoelectricity coupling coefficient is big, energy gap E=3.37eV under the room temperature, exciton bundle 60meV.Wherein the ZnO nano structure membrane exists very strong ultraviolet and blue emission, and this makes it in fields such as ultraviolet detector device, ultra-violet light-emitting device, piezoelectricity transparent film transistor, surface acoustic wave device and solar cells important application prospects arranged.In addition, ZnO also has high breakdown strength and saturated drift velocity, and is stronger than the anti-irradiation ability of most of semi-conducting materials such as Si, GaAs, CdS, GaN, can be applied in high speed device and device aspect, space.Based on these advantages, ZnO TFT has the trend that replaces conventional a-Si TFT among the AM-LCD.
In the prior art, the zno-based thin-film transistor array base-plate generally adopts 4mask～6mask, and promptly four times～six times composition technology is accomplished.Wherein, said four composition technologies comprise: through composition technology form gate electrode and the figure of grid line step, through composition technology form the figure of gate insulation layer, active layer and source-drain electrode step, through composition technology form the step of the figure of protective layer, through a composition technology formation pixel electrode figure.
Because each composition technology all need be the mask plate figure transfer to film pattern, and each layer pattern all need cover on another layer film figure accurately, and in the manufacturing process of zno-based thin-film transistor array base-plate; The number of times of used mask plate is few more, and then production efficiency is high more, and production cost is low more; Therefore; How further to reduce the number of times of composition technology, enhance productivity, reducing production costs is problem demanding prompt solution in the industry.
Summary of the invention
Technical problem to be solved by this invention is to the problems referred to above that exist in the prior art, a kind of manufacture method that can further reduce the array base palte of composition technology number of times is provided, adopts array base palte that this method processes and the display unit that comprises said array base palte.
It is following to solve the technical scheme that technical problem of the present invention adopted:
The manufacture method of said array base palte may further comprise the steps:
Form gate electrode, active layer, source electrode, drain electrode and pattern of pixel electrodes respectively through composition technology, it is characterized in that, the figure of said source electrode, drain electrode and pattern of pixel electrodes form through a composition technology.
Preferably, said manufacture method also includes the step that forms gate insulation layer, protective layer, data wire and grid line;
Said manufacture method is specially:
1) figure of formation gate electrode and grid line on substrate;
2) completing steps 1) substrate on form the figure of gate insulation layer, active layer, pixel electrode, source electrode, drain electrode and data wire successively;
3) at completing steps 2) substrate on form the figure of protective layer.
Further preferably, said step 2) be specially:
21) on said substrate, form grid insulating film and active layer film successively;
22) at completing steps 21) substrate on form transparent conductive film and source successively and leak metallic film;
23) at completing steps 22) substrate on form one deck photoresist; After adopting half-tone mask plate or gray mask plate that said photoresist is made public, develops; Form the complete reserve area of photoresist, photoresist part reserve area and photoresist on the said substrate and remove the zone fully; The complete reserve area of said photoresist is corresponding to the figure that forms drain electrode; Said photoresist part reserve area is corresponding to forming pattern of pixel electrodes, and said photoresist is removed the zone fully corresponding to the figure that forms gate insulation layer, active layer, source electrode, data wire and TFT raceway groove;
24) to completing steps 23) substrate carry out etching, form gate insulation layer, active layer, source electrode, data wire, TFT raceway groove and pattern of pixel electrodes;
25) to completing steps 24) substrate carry out ashing treatment, ash melts the photoresist of said photoresist part reserve area, then said substrate is carried out etching once more, forms the figure of drain electrode.
Further preferably, said step 22) comprising:
Said transparent conductive film and source are leaked metallic film and are adopted identical materials to process; Its formation method comprises: adopt method that ion injects to step 21) the active layer film that forms carries out surface treatment, makes said active layer film surface form transparent conductive film and metallic film is leaked in the source;
Perhaps; Said transparent conductive film and source are leaked metallic film and are adopted material different to process; Its formation method is: adopt method that ion injects to step 21) the active layer film that forms carries out surface treatment; Make said active layer film surface form transparent conductive film, metallic film is leaked in the formation source on said transparent conductive film.
Preferably, said active layer film adopts ZnO or In 2O 3Process; Said ion injects and is included in active layer film surface doping In, Sn, Al, B or the Ga that ZnO processes, perhaps at In 2O 3The active layer film surface doping of Zn or the Sn that process.
Preferably, the thickness range of said grid insulating film is 300nm-400nm, and it adopts the plasma reinforced chemical vapour deposition method and adopts SiN xOr SiO xProcess, perhaps adopt magnetron sputtering method and adopt Al 2O 3Or AIN processes; The thickness range of said active layer film does
Figure BDA0000144290280000041
It adopts magnetron sputtering method to process; The thickness range of said transparent conductive film does
Figure BDA0000144290280000042
The thickness range that metallic film is leaked in said source is 200nm-300nm.
Preferably; Said step 1) comprises: on substrate, form the grid film, form one deck photoresist then above that, adopt mask plate that said photoresist is made public, develops; Said photoresist reserve area is corresponding to the zone of the figure that forms gate electrode and grid line; Again the grid film that comes out is carried out etching,, form the figure of gate electrode and grid line at last with said photoresist lift off.
Further preferably, said grid film adopts the monofilm of Mo, Al or Cu to process, and the duplicature that perhaps adopts AlNd alloy and Mo to form is processed; Said grid film adopts the method for sputter to form.
Preferably; Said step 3) comprises: at completing steps 2) substrate on form the protective layer film, form one deck photoresist then above that, adopt mask plate that said photoresist is made public, develops; Said photoresist reserve area is corresponding to the zone of the figure that forms protective layer; Again the protective layer film that comes out is carried out etching,, form the figure of protective layer at last with said photoresist lift off; The thickness range of said protective layer film is 250nm-300nm, and it adopts the plasma reinforced chemical vapour deposition method and adopts SiN xOr SiO xProcess, perhaps adopt magnetron sputtering method and adopt Al 2O 3Or AIN processes.
The present invention provides a kind of array base palte simultaneously, and said array base palte adopts above-mentioned manufacture method to process.
The present invention also provides a kind of display unit simultaneously, and said display unit comprises above-mentioned array base palte.
Beneficial effect:
1) in the prior art; The zno-based thin-film transistor array base-plate all adopts the normal masks plate in each time composition technology; Make the figure and the pattern of pixel electrodes of source, drain electrode in a composition technology, to form; Also making needs four composition technologies could form array base palte at least; And the manufacture method of array base palte according to the invention and adopt the array base palte that this method processes to adopt halftoning or gray mask plate in the composition technology in the second time; Make the figure and the pattern of pixel electrodes of source, drain electrode in a composition technology, form; Therefore the manufacture method of array base palte according to the invention and the array base palte that adopts this method to process only need adopt three composition technologies to accomplish, and compared with prior art further reduced composition technology number of times, have simplified the manufacture craft of array base palte, improved production efficiency, shortened Production Time, have reduced production cost.
2) prior art generally adopts the mode of deposition to form transparent conductive film; And the method that the present invention adopts ion to inject with innovating is carried out surface treatment to the active layer film; Surface at said active layer film forms the more superior transparent conductive film of performance; Thereby saved the transparent conductive film depositing operation, further shortened the manufacturing time and the production cost of array base palte.
3) figure of the source in the array base palte according to the invention, drain electrode and pattern of pixel electrodes adopt with a composition technology and form, and being connected of pixel electrode and drain electrode need not via hole, and connectivity is good, and electric property is good.
Description of drawings
Fig. 1 is the schematic flow sheet of the manufacture method of array base palte in the embodiment of the invention 1;
Fig. 2 is for carrying out the structural representation of the array base palte in the composition technical process first time in the embodiment of the invention 1;
Wherein: Fig. 2 (a) is for having deposited the sectional view of the array base palte after the grid film on substrate;
Fig. 2 (b) is for accomplishing the sectional view of composition technology array base palte afterwards for the first time;
Fig. 3 is for carrying out the structural representation of the array base palte in the composition technical process second time in the embodiment of the invention 1;
Wherein: Fig. 3 (a) is for having deposited the sectional view of the array base palte after grid insulating film, the active layer film on substrate shown in Fig. 2 (b);
Fig. 3 (b) is for carrying out forming after the surface treatment sectional view of the array base palte after the transparent conductive film to the active layer film shown in Fig. 3 (a);
Fig. 3 (c) leaks the sectional view of the array base palte after the metallic film on substrate shown in Fig. 3 (b), having deposited the source;
Fig. 3 (d) has been for having deposited photoresist on substrate shown in Fig. 3 (c), and to said photoresist make public, the develop sectional view of array base palte afterwards;
Fig. 3 (e) is a sectional view of substrate shown in Fig. 3 (d) being accomplished etching array base palte afterwards;
Fig. 3 (f) is a sectional view of substrate shown in Fig. 3 (e) being accomplished ashing treatment array base palte afterwards;
Fig. 3 (g) is a sectional view of substrate shown in Fig. 3 (f) being accomplished etching array base palte afterwards;
Fig. 3 (h) is the sectional view with the array base palte after the photoresist lift off on the substrate shown in Fig. 3 (g);
Fig. 4 is for accomplishing the structural representation of composition technology array base palte afterwards for the third time in the embodiment of the invention 1;
Wherein: Fig. 4 (a) is for accomplishing the planar structure sketch map of composition technology array base palte afterwards for the third time;
Fig. 4 (b) is that the A-A of Fig. 4 (a) is to sectional view.
Among the figure: the 1-gate electrode; The 2-gate insulation layer; The 3-active layer; The 4-pixel electrode; 5a-source electrode; The 5b-drain electrode; The 6-protective layer; The 7-photoresist; The 8-data wire; The 9-grid line.
Embodiment
For making those skilled in the art understand technical scheme of the present invention better, the manufacture method of array base palte of the present invention and the array base palte that adopts this method to process are described in further detail below in conjunction with accompanying drawing and embodiment.
Among the present invention; The manufacture method of said array base palte may further comprise the steps: the figure that forms gate electrode 1, active layer 3, source electrode 5a, drain electrode 5b and pixel electrode 4 through composition technology respectively; It is characterized in that the figure of said source electrode 5a, drain electrode 5b and the figure of pixel electrode 4 form through a composition technology.
Embodiment 1:
As shown in Figure 1, in the present embodiment, the manufacture method of said array base palte adopts three composition technologies based on the slit photoetching technique, makes the figure of source electrode 5a, drain electrode 5b and the figure of pixel electrode 4 form through a composition technology.The principle of said slit photoetching technique is the slit that specific dimensions is set on mask plate, controls the transmitance of light through producing optical diffraction, thereby controls the thickness of photoresist selectively.Said photoresist preferably adopts the method for spin coating to form.
The manufacture method of said array base palte specifically comprises the steps:
S101. on substrate, pass through the figure of gate electrode 1 of composition technology formation for the first time and grid line 9.
Concrete, shown in Fig. 2 (a), 2 (b), deposition grid film on substrate; Apply one deck photoresist then above that, adopt mask plate that said photoresist is made public, develops, wherein; The photoresist reserve area is corresponding to forming the zone of gate electrode 1 with the figure of grid line 9; Again the grid film that comes out is carried out etching, pass through photoresist stripping process at last, form the figure of gate electrode 1 and grid line 9 said photoresist lift off.
In the present embodiment; The thickness range of said grid film is 200nm-400nm; It adopts metal or ITO (Indium Tin Oxide, indium tin oxide) to process, and preferably adopts the monofilm of Mo, Al or Cu to process; The duplicature that perhaps adopts AlNd alloy and Mo to form is processed, and said grid film adopts the method for sputter to form.
S102. on the substrate of completing steps s101 through the second time composition technology form the figure of gate insulation layer 2, active layer 3, pixel electrode 4, source electrode 5a, drain electrode 5b and data wire 8 successively.In this step, the figure of said gate insulation layer 2, active layer 3, pixel electrode 4, source electrode 5a, drain electrode 5b and data wire 8 is to adopt multistep etching technics (one of core process of slit photoetching process) in a composition technology, to form.
Concrete, said step s102 comprises the steps:
S102-1. shown in Fig. 3 (a), on the substrate of completing steps s101, deposit grid insulating film and active layer film successively.
Wherein, the thickness range of said grid insulating film is 300nm-400nm, and it adopts plasma reinforced chemical vapour deposition method (PECVD, Plasma Enhanced Chemical Vapor Deposition) and adopts SiN xOr SiO xProcess, perhaps adopt magnetron sputtering method and adopt Al 2O 3Or AlN (ammonification aluminium) processes; The thickness range of said active layer film does
Figure BDA0000144290280000081
It adopts magnetron sputtering method and adopts ZnO to process.
S102-2. shown in Fig. 3 (b), on the substrate of completing steps s102-1, form transparent conductive film.
Wherein, The thickness range of said transparent conductive film is preferably said transparent conductive film for
Figure BDA0000144290280000082
formation method is: the method that adopts ion to inject is carried out surface treatment to the active layer film that step s102-1 forms; Make said active layer film surface form transparent conductive film, and said transparent conductive film all standing and being formed uniformly on the surface of active layer film.The method that preferred said ion injects is specially: the active layer film surface doping In, Sn, Al, B or the Ga that process at ZnO.
S102-3. shown in Fig. 3 (c), sedimentary origin leaks metallic film on the substrate of completing steps s102-2.The thickness range that metallic film is leaked in said source is 200nm-300nm, and it adopts magnetron sputtering method and adopts the monofilm of Cu, Mo, Al, AlNd alloy or Ti to process.
S102-4. on the substrate of completing steps s102-3, apply one deck photoresist 7.
S102-5. shown in Fig. 3 (d); Adopt half-tone mask plate or gray mask plate that said photoresist is made public, develops; Said half-tone mask plate or gray mask plate are provided with non-regional transmission, part regional transmission and regional transmission; If said photoresist 7 is a positive photoresist, then above-mentioned three zones complete reserve area NP of corresponding respectively formation photoresist, photoresist part reserve area HP and photoresist on said photoresist are removed regional WP fully; If said photoresist 7 is a negative photoresist, then above-mentioned zone corresponding respectively formation photoresist on said photoresist is removed regional WP, photoresist part reserve area HP and the complete reserve area NP of photoresist fully; The photoresist of the complete reserve area NP of said photoresist is all kept; It is corresponding to the figure that forms drain electrode 5b; The thickness of the photoresist of said photoresist part reserve area HP is than the thin thickness of the photoresist of the complete reserve area NP of photoresist; It is corresponding to the figure that forms pixel electrode 4, and said photoresist is removed the photoresist of regional WP fully and all removed, and it is corresponding to the figure that forms gate insulation layer 2, active layer 3, source electrode 5a, data wire 8 and TFT raceway groove.
Wherein, The principle that forms photoresist part reserve area HP is: because exposure is respectively the part regional transmission that has slit on halftoning or the gray mask plate; No matter said photoresist 7 is positive photoresist or negative photoresist; The diffraction effect of said slit and interference effect make exposure a little less than the luminous intensity of light strength ratio exposure at regional transmission of this part regional transmission; Therefore the photoresist of said part regional transmission is serious not as the resist exposure of regional transmission, makes the thickness of photoresist of photoresist part reserve area HP than the thin thickness of the photoresist of the complete reserve area NP of photoresist.
S102-6. shown in Fig. 3 (e), the substrate of completing steps s102-5 is carried out etching, form the figure of gate insulation layer 2, active layer 3, source electrode 5a, data wire 8, TFT raceway groove and pixel electrode 4.
Here; Because source-drain electrode is different with the material that pixel electrode adopts; In order to obtain better etching effect, preferably the substrate to completing steps s102-5 carries out twice etching to form above-mentioned figure, wherein; Through the figure of etching formation first time gate insulation layer 2, active layer 3, source electrode 5a, data wire 8 and TFT raceway groove, through the figure of etching formation second time pixel electrode 4.
S102-8. shown in Fig. 3 (f), the substrate of completing steps s102-7 is carried out ashing treatment, ash melts the photoresist of said photoresist part reserve area HP.
S102-9. shown in Fig. 3 (g), the substrate of completing steps s102-8 is carried out etching, form the figure of drain electrode 5b.
S102-10. shown in Fig. 3 (h), remaining photoresist (photoresist of the complete reserve area NP of photoresist) is peeled off through photoresist stripping process.
S103. on the substrate of completing steps s102, pass through the figure of the protective layer 6 of composition technology formation for the third time.
Concrete, shown in Fig. 4 (a), 4 (b), deposition protective layer film on the substrate of completing steps s102; Apply one deck photoresist then above that; Adopt mask plate that said photoresist is made public, develops, said photoresist reserve area carries out etching to the protective layer film that comes out again corresponding to the zone of the figure that forms protective layer 6; With said photoresist lift off, form the figure of protective layer 6 at last.
In the present embodiment, the thickness range of said protective layer film is 250nm-300nm, and it adopts the plasma reinforced chemical vapour deposition method and adopts SiN xOr SiO xProcess, perhaps adopt magnetron sputtering method and adopt Al 2O 3Or AIN processes.
Shown in Fig. 4 (a), Fig. 4 (b); Present embodiment provides a kind of array base palte that adopts above-mentioned manufacture method to process simultaneously; It comprises substrate, grid line 9, data wire 8 and grid line 9 and data wire 8 pixel regions that limit intersected with each other; Be formed with said comprising at said infall: be formed on the gate electrode 1 on the substrate, said gate electrode 1 is connected with grid line 9; Cover on the gate electrode 1 and extend to the gate insulation layer 2 on the exposed region of said substrate; Cover the active layer 3 on the gate insulation layer 2; Be formed on the pixel electrode 4 on the active layer 3; Be formed on source electrode 5a and drain electrode 5b on the pixel electrode 4, be provided with the TFT raceway groove between said source electrode 5a and the drain electrode 5b, said source electrode 5a is connected with pixel electrode 4, and said drain electrode 5b is connected with data wire 8; Covering source electrode 5a and drain electrode 5b, and extend to the pixel electrode 4 that exposes and the protective layer 6 on the active layer 3.
Material, the thickness of formed each layer are all identical in each layer of forming said array base-plate structure and the manufacture method of above-mentioned array base palte.
Present embodiment also provides a kind of display unit simultaneously, and said display unit comprises above-mentioned array base palte.
Embodiment 2:
The difference of the manufacture method of the said array base palte of present embodiment and embodiment 1 described manufacture method is:
1) said active layer film adopts In 2O 3Process; Said transparent conductive film is employed in In 2O 3Active layer film surface doping of Zn of processing or the plasma injection mode of Sn are formed at the surface of active layer film.
2) said source-drain electrode is identical with the material that pixel electrode adopts, and the method that promptly adopts ion to inject is carried out surface treatment to the active layer film, makes said active layer film surface form transparent conductive film and source leakage metallic film successively.And, when etching forms the figure of gate insulation layer 2, active layer 3, source electrode 5a, data wire 8, TFT raceway groove and pixel electrode 4, only adopt an etching to get final product because source-drain electrode is identical with the material that pixel electrode adopts.
Present embodiment provides a kind of array base palte that adopts above-mentioned manufacture method to process simultaneously.
Present embodiment also provides a kind of display unit simultaneously, and said display unit comprises above-mentioned array base palte.
Material, the thickness of formed each layer are all identical with embodiment 1 in each layer of composition present embodiment array base-plate structure and the manufacture method of present embodiment array base palte, repeat no more.
The manufacture method of array base palte according to the invention and the array base palte that adopts this method to process only need adopt three composition technologies to accomplish, and compared with prior art further reduced composition technology number of times, have simplified the manufacture craft of array base palte; The method that the present invention adopts ion to inject with innovating is carried out surface treatment to the active layer film; Surface at said active layer film forms the more superior transparent conductive film of performance; Thereby saved the transparent conductive film depositing operation, further shortened the manufacturing time and the production cost of array base palte; The figure of source, drain electrode and pattern of pixel electrodes adopt with a composition technology and form, and being connected of pixel electrode and drain electrode need not via hole, and connectivity is good, and electric property is good.
The manufacture method of array base palte according to the invention and the array base palte that adopts this method to process both can be applicable in the display unit; Comprise LCD, OLED or the like; TFT-LCD for example; AM-OLED (Active Matrix-Organic Light Emitting Diode, active matrix type organic light emitting diode display).
It is understandable that above execution mode only is the illustrative embodiments that adopts for principle of the present invention is described, yet the present invention is not limited thereto.For the one of ordinary skilled in the art, under the situation that does not break away from spirit of the present invention and essence, can make various modification and improvement, these modification also are regarded as protection scope of the present invention with improving.

Claims (10)

1. the manufacture method of an array base palte; May further comprise the steps: the figure that forms gate electrode (1), active layer (3), source electrode (5a), drain electrode (5b) and pixel electrode (4) through composition technology respectively; It is characterized in that the figure of said source electrode (5a), drain electrode (5b) and the figure of pixel electrode (4) form through a composition technology.
2. manufacture method according to claim 1 is characterized in that, said manufacture method also includes the step that forms gate insulation layer (2), protective layer (6), data wire (8) and grid line (9);
Said manufacture method is specially:
1) on substrate, forms the figure of gate electrode (1) and grid line (9);
2) completing steps 1) substrate on form the figure of gate insulation layer (2), active layer (3), pixel electrode (4), source electrode (5a), drain electrode (5b) and data wire (8) successively;
3) at completing steps 2) substrate on form the figure of protective layer (6).
3. manufacture method according to claim 2 is characterized in that, said step 2) be specially:
21) on said substrate, form grid insulating film and active layer film successively;
22) at completing steps 21) substrate on form transparent conductive film and source successively and leak metallic film;
23) at completing steps 22) substrate on form one deck photoresist; After adopting half-tone mask plate or gray mask plate that said photoresist is made public, develops; Form the complete reserve area of photoresist, photoresist part reserve area and photoresist on the said substrate and remove the zone fully; The complete reserve area of said photoresist is corresponding to the figure that forms drain electrode (5b); Said photoresist part reserve area is corresponding to the figure that forms pixel electrode (4), and said photoresist is removed the zone fully corresponding to the figure that forms gate insulation layer (2), active layer (3), source electrode (5a), data wire (8) and TFT raceway groove;
24) to completing steps 23) substrate carry out etching, form the figure of gate insulation layer (2), active layer (3), source electrode (5a), data wire (8), TFT raceway groove and pixel electrode (4);
25) to completing steps 24) substrate carry out ashing treatment, ash melts the photoresist of said photoresist part reserve area, then said substrate is carried out etching once more, forms the figure of drain electrode (5b).
4. manufacture method according to claim 3 is characterized in that, said step 22) comprising:
Said transparent conductive film and source are leaked metallic film and are adopted identical materials to process; Its formation method comprises: adopt method that ion injects to step 21) the active layer film that forms carries out surface treatment, makes said active layer film surface form transparent conductive film and metallic film is leaked in the source;
Perhaps; Said transparent conductive film and source are leaked metallic film and are adopted material different to process; Its formation method is: adopt method that ion injects to step 21) the active layer film that forms carries out surface treatment; Make said active layer film surface form transparent conductive film, metallic film is leaked in the formation source on said transparent conductive film.
5. manufacture method according to claim 4 is characterized in that, said active layer film adopts ZnO or In 2O 3Process; Said ion injects and is included in active layer film surface doping In, Sn, Al, B or the Ga that ZnO processes, perhaps at In 2O 3The active layer film surface doping of Zn or the Sn that process.
6. according to the described manufacture method of one of claim 3-5; It is characterized in that the thickness range of said active layer film is 200nm-300nm for the thickness range of thickness range said source leakage metallic film for
Figure FDA0000144290270000022
of
Figure FDA0000144290270000021
said transparent conductive film.
7. manufacture method according to claim 2 is characterized in that, said step 1) comprises: on substrate, form the grid film; Form one deck photoresist then above that; Adopt mask plate that said photoresist is made public, develops, said photoresist reserve area carries out etching to the grid film that comes out again corresponding to forming the zone of gate electrode (1) with the figure of grid line (9); With said photoresist lift off, form the figure of gate electrode (1) and grid line (9) at last.
8. manufacture method according to claim 2 is characterized in that, said step 3) comprises: at completing steps 2) substrate on form the protective layer film; Form one deck photoresist then above that; Adopt mask plate that said photoresist is made public, develops, said photoresist reserve area carries out etching to the protective layer film that comes out again corresponding to the zone of the figure that forms protective layer (6); With said photoresist lift off, form the figure of protective layer (6) at last; The thickness range of said protective layer film is 250nm-300nm, and it adopts the plasma reinforced chemical vapour deposition method and adopts SiN xOr SiO xProcess, perhaps adopt magnetron sputtering method and adopt Al 2O 3Or AIN processes.
9. array base palte that adopts the arbitrary described manufacture method of claim 1-8 to process.
10. a display unit is characterized in that, comprises the described array base palte of claim 9.
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