CN1272664C - Producing method for thin-membrane transistor liquid-crystal displaying device - Google Patents
Producing method for thin-membrane transistor liquid-crystal displaying device Download PDFInfo
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- CN1272664C CN1272664C CN 200310115870 CN200310115870A CN1272664C CN 1272664 C CN1272664 C CN 1272664C CN 200310115870 CN200310115870 CN 200310115870 CN 200310115870 A CN200310115870 A CN 200310115870A CN 1272664 C CN1272664 C CN 1272664C
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Abstract
The present invention relates to a manufacture method of a thin film transistor liquid crystal display, particularly to manufacture of a thin film transistor liquid crystal display (a thin film transistor liquid crystal display TFT-LCD). The present invention provides a glass base plate. A first-layer metal layer is formed on the surface of the base plate and the scan line of a gate electrode is manufactured; two grate insulating layers are orderly deposited; a semiconductor layer is deposited on each grate insulating layer; then, two blocking layers are orderly deposited, and the figures of the two blocking layers are limited; a semiconductor doping layer and a second-layer metal layer are deposited on the blocking layer and etched; then, two passivation layers are respectively and orderly deposited and etched for forming contact hole structure; a transparent conducting layer is deposited, and pixel electrode patterns are limited. The technology of the present invention can be utilized for effectively controlling the quality of film forming and the density of film quality levels, forming a good film-forming interface, using a simple etching method for etching, having good slope angles, ensuring reliable insulating performance and stable TFT electrical performance, and easily etching ideal patterns.
Description
Technical field
The present invention relates to the manufacture method of a kind of Thin Film Transistor-LCD (thin film transistor liquidcrystal display TFT-LCD).Particularly relate to a kind of photoetching process (photo-etching-process, PEP) manufacturing process technology of making Thin Film Transistor-LCD of utilizing five times.
Background technology
Along with developing rapidly of electronics and information industry, the range of application and the demand of flat-panel monitor are increasing.Particularly TFT-LCD becomes the main product of LCD development with its high definition, the demonstration of very color video, advantages such as outward appearance is frivolous, power consumption is few, radiationless pollution.Existing seven photoetching (7PEP) technology maturation of producing TFT-LCD.But its photoetching often, and the production cycle is long, yield rate is low, cost is high.Therefore, TFT-LCD production commercial city is explored in effort and is reduced the photoetching number of times as far as possible, shortens the production cycle, to improve the TFT-LCD manufacturing process technology of TFT-LCD production efficiency, raising yield rate, reduction manufacturing cost.
At present, some TFT-LCD manufacturer is reduced to the photoetching making technology with its manufacture method five times by seven photoetching making technologies.
Shown in Fig. 1 a-Fig. 1 h, make the diagrammatic cross-section of TFT-LCD structure for existing five times general photoetching processes.On transparent glass substrate 10, form TFT-LCD.Wherein include different elements: thin film transistor (TFT), pixel electrode, sweep trace, data line, memory capacitance.
As Fig. 1 a, the first metal layer is deposited on the surface of glass substrate 10 (not shown), again by the first time lithographic fabrication processes the first metal layer limited form gate electrode 11 and sweep trace (not shown).As Fig. 1 b: deposit-gate insulation layer 12, semiconductor layer 13, restraining barrier 14 in regular turn from lower to upper.As Fig. 1 c: utilizing for the second time, photoetching making technology limits the structure that forms restraining barrier 14.Deposit-doping semiconductor layer 15, second metal level 16 in regular turn shown in Fig. 1 d.As scheme e: utilizing for the third time, photoetching making technology limits semiconductor layer 13, doping semiconductor layer 15, source electrode 16a, drain electrode 16b structure.As Fig. 1 f deposit passivation layer 17 again.Utilize the 4th photoetching making technology to finish the etching of contact hole 18, contact hole 19 as Fig. 1 g.As Fig. 1 h deposit transparency conducting layer (not shown), and carry out the complete structure of pixel electrode 20 of the 5th chemical wet etching.Though above-mentioned TFT-LCD manufacturing process technology is to be reduced to chemical wet etching manufacture craft technology five times.But etching technics is complicated when gate insulation layer etching, passivation layer etching, is prone to chamfering, produces during the growth film forming to stride disconnectedly, influences the demonstration of TFT-LCD.How to solve the production Technology problem, the raising yield of products just becomes an important problem in present five chemical wet etchings manufacturing TFT-LCD process.
Summary of the invention
The technical problem to be solved in the present invention provides and a kind ofly adopts sandwich construction, layering to grow into membrane technology, chemical wet etching technology is simple, cost is low Thin Film Transistor-LCD manufacture method.
Its characteristics one of the present invention: in the growth of gate insulation layer film forming, adopt sandwich construction, layering growing technology, deposit gate insulation layer one 32a, gate insulation layer two 32b in regular turn
Its characteristics two of the present invention: in the growth of restraining barrier film forming, adopt sandwich construction, layering growing technology, barrier layer one 34a, restraining barrier two 34b in regular turn; With simple lithographic method etching barrier layer figure.
Its characteristics three of the present invention: in the growth of passivation layer film forming, adopt sandwich construction, the layering growing technology, difference is deposit passivation layer one 37a, passivation layer two 37b in regular turn.Etching contact hole 38, the easy angle of gradient that limits etching solves the technical matters in the above-mentioned production technology during contact hole 39.
In order to realize above-mentioned purpose, the invention provides a kind of manufacture method of film transistor plane indicator spare, its step is as follows:
1. a glass substrate is provided, forms the ground floor metal level and make gate electrode and sweep trace at substrate surface.
2. the two-layer gate insulation layer of deposit in regular turn, deposition of semiconductor layer on the gate insulation layer, the two-layer restraining barrier of growing of deposit in regular turn again, and limit two-layer restraining barrier figure.
3. deposit doping semiconductor layer, second layer metal layer and etching on the restraining barrier,
Purpose is to form ohmic contact layer and source electrode, drain electrode.
4. deposit passivation layers in regular turn and etching form the contact hole structure respectively again.
5. deposit transparency conducting layer, and qualification pixel electrode figure.
The technology of the present invention and existing film transistor plane indicator is compared, and mainly is to adopt sandwich construction, and layering grows into membrane technology.Utilize the technology of the present invention, can effectively control the quality of film forming and the density degree of membranous level, form good one-tenth membrane interface.With simple lithographic method etching, has the good angle of gradient.Guarantee reliable insulating property and stable TFT electric property, easily the desirable figure of etching.
Description of drawings
Fig. 1 a-Fig. 1 h is method, the step diagrammatic cross-section shape of five lithographic fabrication processes technology of existing general TFT-LCD;
The label declaration of accompanying drawing is as follows:
10～glass substrate; 11～gate electrode; 12～gate insulation layer;
13～semiconductor layer; 14～restraining barrier; 15～doping semiconductor layer;
16～the second metal levels; 16a～source electrode; 16b～drain electrode;
17～passivation layer; 18～contact hole; 19～contact hole; 20～pixel electrode.
Fig. 2 a-Fig. 2 h is method, the step diagrammatic cross-section of the TFT-LCD manufacturing process technology of the embodiment of the invention.
The label declaration of accompanying drawing is as follows:
30～glass substrate; 31～gate electrode; 32a～gate insulation layer one;
32b～gate insulation layer two; 33～semiconductor layer; 34a～restraining barrier one;
34b～restraining barrier two; 35～doping semiconductor layer; 36～the second metal levels;
36a～source electrode; 36b～drain electrode; 37a～passivation layer one;
37b～passivation layer two; 38～contact hole; 39～contact hole; 40～pixel electrode.
Embodiment
For clearer understanding purpose of the present invention, characteristics and advantage, hereinafter with embodiment the present invention is further described in conjunction with the accompanying drawings.
See also Fig. 2 a-Fig. 2 h and be the preferred embodiment step diagrammatic cross-section of the present invention for the TFT-LCD manufacture method improving prior art and develop.
Shown in Fig. 2 a: deposit the first metal layer on glass substrate 30 surfaces at first, available molybdenum and tungsten alloy, chromium, aluminium, aluminium alloy or copper are finished.And then carry out the chemical wet etching manufacture craft first time, the first metal layer etching is formed gate electrode 31 reach the sweep trace (not shown) that is connected with gate electrode 31.
Shown in Fig. 2 b: after finishing for the first time the chemical wet etching manufacture craft, then deposit gate insulation layer one 32a, gate insulation layer two 32b in regular turn on glass substrate 30, gate insulation layer one and gate insulation layer two can be SiOx or SiNx or SiOxNx; Or the composite structure of SiOx, SiNx, SiOxNx.Semiconductor layer 33 can be SiNx or SiOxNx for amorphous silicon layer, restraining barrier one 34a, restraining barrier two 34b; Or the composite structure of SiNx, SiOxNx.
Shown in Fig. 2 c: utilize chemical wet etching manufacture craft for the second time, form barrier layer structure, restraining barrier one 34a, restraining barrier two 34b.
A deposit of gate insulation layer film forming is finished, and at first finishes the film forming growth of gate insulation layer one 32a, finishes the film forming growth of membranous gate insulation layer two 32b of difference again.The restraining barrier also adopts layering to grow into membrane technology.At first grow restraining barrier one 34a, regrowth restraining barrier two 34b can effectively limit the restraining barrier figure.
Shown in Fig. 2 d: after finishing for the second time the chemical wet etching manufacture craft, deposit doping semiconductor layer (n in regular turn again
+Doped amorphous silicon layer) 35; Second metal level 36 can be used composite structure, aluminium alloy, molybdenum, the chromium of molybdenum and aluminium.
Shown in Fig. 2 e: utilize photoetching making technology etching semiconductor layer 33, doping semiconductor layer 35 for the third time.Second metal level, 36 etchings are limited the figure of formation source electrode 36a, drain electrode 36b.Finish the making of thin-film transistor structure.
Shown in Fig. 2 f: after finishing for the third time the chemical wet etching manufacture craft, deposit passivation layer one 37a in regular turn; Passivation layer two 37b, passivation layer one and passivation layer two are SiNx or SiOxNx; Or the composite structure of SiNx, SiOxNx.
Shown in Fig. 2 g: utilize photoetching making technology the 4th time, etching is made the structure that forms contact hole 38, contact hole 39.
Contact hole 38 etchings and contact hole 39 are etched in a chemical wet etching technology and finish.In the time of passivation layer one 37a of etching contact hole 38, passivation layer two 37b, also want the gate insulation layer that is superimposed up and down and the passivation layer of etching contact hole 39.In etching contact hole 39, can't be with the second metal layer material etching that is used for linking to each other with pixel electrode on the display pixel, otherwise transparency electrode is bad with second metal layer contacting even do not contact, and influences the demonstration of liquid crystal display.Easily produce simultaneously the angle of gradient chamfering when contact hole 38, contact hole 39 etchings, it is disconnected that striding of rete then can take place during the deposit transparent electrode layer, and drain electrode metal and transparency electrode do not connect, and influence the demonstration of liquid crystal display equally.Gate insulation layer and passivation layer adopted respectively separate into membrane technology.Growth generates different membranous of densification and porousness during gate insulation layer respectively; Or the gate insulating film of unlike material.Guarantee the stability of etching technics on the one hand, can pass through gate insulation layer one 32a, gate insulation layer two 32b again, divide layer growth to eliminate membranous pin hole, improve insulating property.Generate by adjustment time, power during the growth of passivation layer different membranous, i.e. passivation layer one 37a, passivation layer two 37b.Thereby effectively control membranously, make membranous interface in conjunction with good.By control gate insulation course one 32a, gate insulation layer two 32b, passivation layer one 37a, the membrance casting condition of passivation layer two 37b and suitable combination of materials, avoid occurring the etching chamfering, rete can not take place when guaranteeing the deposit transparency electrode stride disconnectedly, drain electrode contacts well with pixel electrode.
Shown in Fig. 2 h: after finishing the 4th chemical wet etching manufacture craft, carry out-transparency conducting layer the deposit (not shown) of (ITO indium tin oxide layer), filling contact hole 38, contact hole 39.Carry out the 5th chemical wet etching manufacture craft again and form pixel electrode 40.
The present invention adopts five chemical wet etching manufacture craft technology to finish the manufacturing process of TFT-LCD.This manufacturing technology is controlled the etch rate and the etching figure of each rete by selecting the membranous of suitable material and control gate insulation course, restraining barrier, passivation layer, guarantees to produce desirable TFT-LCD product.
Claims (7)
1. the manufacture method of a Thin Film Transistor-LCD comprises:
One glass substrate is provided, on substrate, forms gate electrode;
Deposit gate insulation layer, semiconductor layer, restraining barrier in regular turn on substrate and gate electrode, and limit the restraining barrier figure;
Deposit doping semiconductor layer, second layer metal layer and etching on the restraining barrier form ohmic contact layer and source electrode, drain electrode;
Deposit passivation layer and etching form the contact hole structure again;
The deposit transparency conducting layer, and limit the pixel electrode figure; It is characterized in that: described gate insulation layer adopts gate insulation layer one and gate insulation layer two double-deckers, and gate insulation layer one and gate insulation layer two be different membranous of densification and porousness, or the material difference; Passivation layer adopts passivation layer one and passivation layer two double-deckers, and passivation layer one is membranous different with passivation layer two; Restraining barrier one and restraining barrier two double-deckers are adopted in the restraining barrier; Gate insulation layer, restraining barrier, passivation layer adopt the layering deposit to grow into membrane technology respectively and form.
2. the manufacture method of Thin Film Transistor-LCD according to claim 1 is characterized in that: adopt sandwich construction, the film technique of layering deposit gate insulation layer, deposit gate insulation layer one, gate insulation layer two in regular turn.
3. the manufacture method of Thin Film Transistor-LCD according to claim 2, it is characterized in that: gate insulation layer one and gate insulation layer two can be SiOx or SiNx or SiOxNx; Or the composite structure of SiOx, SiNx, SiOxNx.
4. according to the manufacture method of the described Thin Film Transistor-LCD of claim 1, it is characterized in that: adopt sandwich construction, the film technique of layering barrier layer, the restraining barrier one of at first growing, regrowth restraining barrier two.
5. the manufacture method of Thin Film Transistor-LCD according to claim 4, it is characterized in that: restraining barrier one and restraining barrier two can be SiNx or SiOxNx; Or the composite structure of SiNx, SiOxNx.
6. according to the manufacture method of the described Thin Film Transistor-LCD of claim 1, it is characterized in that: adopt sandwich construction, the film technique of layering deposit passivation layer, deposit passivation layer one, passivation layer two in regular turn.
7. the manufacture method of Thin Film Transistor-LCD according to claim 6 is characterized in that: passivation layer one and passivation layer two are SiNx or SiOxNx; Or the composite structure of SiNx, SiOxNx.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310115870 CN1272664C (en) | 2003-12-03 | 2003-12-03 | Producing method for thin-membrane transistor liquid-crystal displaying device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310115870 CN1272664C (en) | 2003-12-03 | 2003-12-03 | Producing method for thin-membrane transistor liquid-crystal displaying device |
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| CN1553269A CN1553269A (en) | 2004-12-08 |
| CN1272664C true CN1272664C (en) | 2006-08-30 |
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Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101107682B1 (en) * | 2004-12-31 | 2012-01-25 | 엘지디스플레이 주식회사 | Thin Film Transistor Substrate for Display Device And Method For Fabricating The Same |
| CN100368913C (en) * | 2005-01-31 | 2008-02-13 | 广辉电子股份有限公司 | Thin film diode liquid crystal display with high aperture ratio |
| CN100371815C (en) * | 2005-01-31 | 2008-02-27 | 广辉电子股份有限公司 | Manufacture of thin-membrane transistor of liquid-crystal displaying device |
| JP2007093686A (en) | 2005-09-27 | 2007-04-12 | Mitsubishi Electric Corp | Liquid crystal display device and manufacturing method thereof |
| CN101526707B (en) | 2008-03-07 | 2011-10-12 | 北京京东方光电科技有限公司 | TFT-LCD array base plate structure and manufacturing method thereof |
| CN101770121B (en) * | 2008-12-26 | 2012-11-21 | 北京京东方光电科技有限公司 | Thin film transistor liquid crystal display (TFT-LCD) array substrate and manufacturing method thereof |
| US8247276B2 (en) | 2009-02-20 | 2012-08-21 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor, method for manufacturing the same, and semiconductor device |
| CN102646631B (en) * | 2011-10-28 | 2015-03-11 | 京东方科技集团股份有限公司 | Manufacturing method of thin film transistor (TFT) array substrate, TFT array substrate and liquid crystal display |
| CN102651343B (en) * | 2012-03-16 | 2014-12-24 | 京东方科技集团股份有限公司 | Manufacturing method of array substrate, array substrate and display device |
| CN103077943B (en) * | 2012-10-26 | 2016-04-06 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display unit |
| CN104701326A (en) * | 2015-03-19 | 2015-06-10 | 京东方科技集团股份有限公司 | Array substrate and manufacture method thereof and display device |
| CN107104106B (en) * | 2017-04-10 | 2019-10-11 | 武汉华星光电技术有限公司 | The production method and TFT substrate of TFT substrate |
| CN109143707A (en) * | 2018-10-08 | 2019-01-04 | 惠科股份有限公司 | A kind of conductive layer insulating method, conductive layer insulation system and display device |
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