CN202009000U - Array substrate and liquid crystal display - Google Patents
Array substrate and liquid crystal display Download PDFInfo
- Publication number
- CN202009000U CN202009000U CN2010206817009U CN201020681700U CN202009000U CN 202009000 U CN202009000 U CN 202009000U CN 2010206817009 U CN2010206817009 U CN 2010206817009U CN 201020681700 U CN201020681700 U CN 201020681700U CN 202009000 U CN202009000 U CN 202009000U
- Authority
- CN
- China
- Prior art keywords
- electrode
- thin film
- array base
- base palte
- resilient coating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The utility model discloses an array substrate and a liquid crystal display. The array substrate comprises a substrate, a conductive pattern and an insulating layer are formed on the substrate, and the insulating layer at least comprises a pixel thin film buffer layer formed between a pixel electrode and the conductive pattern adjacent to the pixel electrode. The array substrate and the liquid crystal display are capable of solving the problem of easiness in falling off of gate lines, gate electrodes or source electrodes and drain electrodes caused by a seam generated between a gate metal thin film or a source drain metal thin film and a transparent pixel thin film during manufacture of an existing array substrate, and have excellent performance.
Description
Technical field
The utility model relates to lcd technology, relates in particular to a kind of array base palte and LCD.
Background technology
LCD is a flat-panel monitor commonly used at present, Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display wherein, be called for short TFT-LCD) owing to have advantages such as volume is little, low in energy consumption, radiationless, and become the main product in the LCD.Usually TFT-LCD comprises liquid crystal panel, drive circuit and backlight.Liquid crystal panel is the critical piece among the TFT-LCD, by array base palte and color membrane substrates box is formed, and is filled with liquid crystal layer therebetween; The voltage that provides by control Driver Circuit deflects ordered liquid crystal molecule, and the light and shade that produces light changes, and wherein the control of voltage is finished by thin-film transistor.
The structure of existing array base palte comprises: underlay substrate, be formed with data line crossing and grid line in length and breadth on the underlay substrate, and data wire and grid line enclose and form the pixel cell that matrix form is arranged; Each pixel cell comprises TFT switch and pixel electrode; The TFT switch comprises gate electrode, source electrode, drain electrode and active layer; Gate electrode connects grid line, and the source electrode connects data wire, and drain electrode connects pixel electrode, and active layer is formed between source electrode and drain electrode and the gate electrode.Wherein, the gate electrode of data wire, grid line, TFT switch, source electrode, drain electrode and active layer, and pixel electrode can be referred to as conductive pattern.For keeping the insulation of each conductive pattern, the conductive pattern that is provided with layer can be provided with at interval, or conductive pattern be set by the different at interval layer of insulating barrier, for example, cover gate insulating barrier on grid line and the gate electrode keeps insulation with TFT switch and data wire; Be coated with passivation layer on TFT switch and the data wire, keep insulation with pixel electrode, pixel electrode can link to each other with drain electrode by passivation layer via hole.
The structure of above-mentioned array base palte forms pattern by several times thin film deposition and photoetching process and finishes, and one time photoetching process forms a layer pattern.Form a layer pattern, at first will on underlay substrate, deposit thin film; Apply one deck light-sensitive material at film surface then, light-sensitive material is carried out exposure imaging by mask plate; Carry out etching by photoetching process then and form final pattern; At last, light sensitive material is peeled off, and formed thin film pattern down.Wherein, each layer pattern all will cover on another layer pattern accurately in accurate position; Every layer pattern can have identical or different material, and thickness is generally the hundreds of nanometer to several microns.
Usually, the quantity of mask used plate and number of times are few more in the manufacture process of array base palte, and production efficiency is high more, and production cost is just low more.At present, the manufacture craft of array base palte develops into photoetching process four times by seven times original photoetching processes, even also has minority manufacturer to bring into use third photo etching technology.Wherein,, generally adopt halftoning or gray tone mask plate, form the pattern that comprises a plurality of structures simultaneously by a photoetching process in order to reduce the number of times of photoetching process.And be more common technology with transparent pixels electrode and other patterned layer one-shot formings by a photoetching process, for example form transparent pixels electrode and gate electrode simultaneously, perhaps form transparent pixels electrode and source electrode and drain electrode etc. simultaneously by a photoetching process.
An above-mentioned photoetching process forms transparent pixels electrode and gate electrode simultaneously, or the process of transparent pixels electrode and source electrode and drain electrode generally is first deposit transparent pixel thin film, and directly metallic film is leaked in deposition grid metallic film or source on the transparent pixels film then; On above-mentioned film, apply photoresist, and form the photoresist pattern through exposure imaging; Next, carry out etching, ashing and etching operation again, and final formation comprise transparent pixels electrode and gate electrode, perhaps comprise the pattern of transparent pixels electrode and source electrode and drain electrode.Usually, industry can be selected light transmission tin indium oxide (Indium Tin Oxides preferably; Abbreviate as: ITO) as the transparent pixels electrode.According to the manufacture craft of ITO, ITO can be divided into amorphous ITO and polycrystalline ITO.And since amorphous ITO can make at normal temperatures, and have that manufacture craft is simple, etching speed is fast, production efficiency advantages of higher and being widely adopted.
But under the high-temperature technology in above-mentioned etching process or the effect of annealing process, amorphous ITO can be transformed into polycrystalline ITO, and the stress of transparent pixels film also can be become the tensile stress of polycrystalline ITO by the compression of amorphous ITO.The change of transparent pixels membrane stress tend to cause and adjacent films between produce the slit, be between transparent pixels film and grid metallic film, perhaps transparent pixels film and source are leaked between metallic film and can be produced the slit, make grid metallic film or source leak the adhesiveness variation of metallic film and transparent pixels film, grid line, gate electrode or source electrode, the electric leakage of final formation are very easily come off, produce the bad of TFT.
The utility model content
The utility model provides a kind of array base palte and LCD, leak grid line, gate electrode or the source electrode that produces the slit between metallic film and transparent pixels film and cause, the problem that electric leakage very easily comes off to solve in the existing array base palte because of grid metallic film or source in the manufacture process, to improve the performance of array base palte.
The utility model provides a kind of array base palte, comprises underlay substrate, is formed with conductive pattern and insulating barrier on the described underlay substrate, and described insulating barrier comprises at least:
The pixel thin film resilient coating, be formed at pixel electrode and and described pixel electrode adjacent conductive pattern between.
Array base palte as mentioned above, wherein, described conductive pattern and insulating barrier also comprise: described pixel electrode and grid line and gate electrode; Described pixel thin film resilient coating is formed between described pixel electrode and described grid line and the gate electrode.
Array base palte as mentioned above, wherein, described pixel electrode is formed on the described underlay substrate; Described grid line and gate electrode are formed on the described pixel thin film resilient coating; Described pixel electrode, described pixel thin film resilient coating and described grid line and gate electrode one-shot forming.
Array base palte as mentioned above, wherein, described conductive pattern and insulating barrier also comprise: gate insulation layer is formed at described grid line and gate electrode top and covers described underlay substrate; The first contact via hole is formed on described pixel thin film resilient coating and the described gate insulation layer, and runs through described pixel thin film resilient coating and described gate insulation layer; Data wire is formed on the described gate insulation layer; Source electrode and drain electrode are formed on the described gate insulation layer, and described drain electrode is connected with described pixel electrode by the described first contact via hole; Active layer is formed on described source electrode and the drain electrode, and is connected with drain electrode with described source electrode; Passivation layer is formed on described active layer, described source electrode and drain electrode top and covers described underlay substrate.
Array base palte as mentioned above, wherein, described conductive pattern and insulating barrier also comprise: described pixel electrode and drain electrode; Described pixel thin film resilient coating is formed between described pixel electrode and the described drain electrode, and is formed with the second contact via hole on the described pixel thin film resilient coating; Described drain electrode is connected with described pixel electrode by the described second contact via hole.
Array base palte as mentioned above, wherein, described drain electrode is formed at described pixel thin film resilient coating top; Described pixel thin film resilient coating is formed at described pixel electrode top; Described pixel electrode, described pixel thin film resilient coating contact the via hole one-shot forming with described second.
Array base palte as mentioned above, wherein, described conductive pattern and insulating barrier also comprise: grid line and gate electrode are formed on the described underlay substrate; Gate insulation layer is formed on described grid line and the gate electrode; Active layer is formed on source electrode and the described drain electrode, and is connected with described drain electrode with described source electrode; Passivation layer is formed on described active layer, described source electrode and the described drain electrode and covers described underlay substrate; Described pixel electrode is formed on the described gate insulation layer.
Array base palte as mentioned above, wherein, described pixel thin film resilient coating is that thickness is 1000～4000 inorganic insulation layer.
Array base palte as mentioned above, wherein, described pixel thin film resilient coating is that thickness is 1500～5000 organic insulator.
The utility model provides a kind of LCD, comprises arbitrary array base palte that the utility model provides.
Array base palte that the utility model provides and LCD, employing pixel electrode and and pixel electrode adjacent conductive pattern between the technical scheme of pixel thin film resilient coating is set, when having avoided in the array base palte manufacture process transparent pixels electrode film generation STRESS VARIATION by the cushioning effect of pixel thin film resilient coating, pixel electrode and and pixel electrode adjacent conductive pattern between form the slit, the increase pixel electrode is adjacent the adhesiveness between the conductive pattern, solve the adjacent conductive pattern because of and pixel electrode between the generation slit in the follow-up problem that is easy to come off of occurring, and finally improved the performance of array base palte.
Description of drawings
The fragmentary top TV structure schematic diagram of the array base palte that Fig. 1 provides for the utility model embodiment one;
The fragmentary top TV structure schematic diagram of the array base palte that Fig. 2 A provides for the utility model embodiment two;
Fig. 2 B dissects structural representation among Fig. 2 A along the side-looking of A-A line;
Fig. 2 C is the flow chart of manufacture method of the array base palte of the utility model embodiment two;
The fragmentary top TV structure schematic diagram of the array base palte that Fig. 3 A provides for the utility model embodiment three;
Fig. 3 B dissects structural representation among Fig. 3 A along the side-looking of A-A line;
Fig. 3 C is the flow chart of manufacture method of the array base palte of the utility model embodiment three.
Reference numeral:
The 1-underlay substrate; The 2-grid line; The 3-gate electrode;
The 4-gate insulation layer; The 5-data wire; The 6-active layer;
7-source electrode; The 8-drain electrode; The 9-passivation layer;
The 10-first contact via hole; The 11-pixel electrode; 20-pixel thin film resilient coating;
The 30-second contact via hole.
Embodiment
For the purpose, technical scheme and the advantage that make the utility model embodiment clearer, below in conjunction with the accompanying drawing among the utility model embodiment, technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the utility model protection.
Embodiment one
The fragmentary top TV structure schematic diagram of the array base palte that Fig. 1 provides for the utility model embodiment one.As shown in Figure 1, the array base palte that present embodiment provides comprises underlay substrate 1, is formed with conductive pattern and insulating barrier on the underlay substrate 1; Wherein, conductive pattern comprises gate electrode 3, source electrode 7, drain electrode 8 and the active layer 6 of data wire 5, grid line 2, TFT switch, and pixel electrode 11.Wherein, data wire 5 and grid line 2 intersect in length and breadth, enclose the formation pixel cell.Pixel cell comprises TFT switch and pixel electrode 11; The insulating barrier of present embodiment comprises pixel thin film resilient coating (not shown in Fig. 1) at least, this pixel thin film resilient coating be formed at pixel electrode 11 and and pixel electrode 11 adjacent conductive patterns between, avoided in array base palte manufacturing process STRESS VARIATION because of the pixel electrode film make pixel electrode 11 and and pixel electrode 11 adjacent conductive patterns between produce the slit.
When the material of pixel electrode is amorphous ITO, because in the manufacturing process of array base palte, amorphous ITO can become polycrystalline ITO because of the influence of high-temperature technology or annealing process, make the stress of transparent pixels film become compression by tensile stress, cause it to be adjacent and produce the slit between the film, reduction transparent pixels film is adjacent the adhesion between the film, and finally cause adhesion variation between formed pixel electrode and the pixel electrode adjacent conductive pattern, the adjacent conductive pattern is easy to come off with pixel electrode, and it is bad to produce TFT.The array base palte of present embodiment, be arranged at pixel electrode and be adjacent pixel thin film resilient coating between the conductive pattern by in the manufacture craft of array base palte, forming, avoid the pixel electrode stress to change and be adjacent at it and produce the slit between conductive pattern by the cushioning effect of pixel thin film resilient coating, overcome defective of the prior art, guaranteed pixel electrode and and pixel electrode adjacent conductive pattern between adhesion, improved the yield of TFT.
In technique scheme, the material of pixel thin film resilient coating is not limited.The pixel thin film resilient coating can adopt organic insulating material also can adopt inorganic insulating material.Wherein, if organic insulating material for example can adopt benzocyclobutane olefine resin (BCB), its thickness is generally 1500～5000; If adopt inorganic insulating material, for example can adopt oxide, nitride or oxynitrides, its corresponding reacting gas can be silane (SiH
4), ammonia (NH
3), nitrogen (N
2) or dichloro hydrogen silicon (SiH
2Cl
2), ammonia (NH
3), nitrogen (N
2), its thickness can be 1000～4000.
Further, in conjunction with being the minimizing photoetching process in the prior art, the most common photoetching process of passing through forms transparent pixels electrode and gate electrode simultaneously, perhaps form the manufacture craft of transparent pixels electrode and source electrode and drain electrode simultaneously, pixel thin film resilient coating in the array base palte that present embodiment provides is arranged between pixel electrode and grid line and the gate electrode, perhaps be arranged between pixel electrode and source electrode and the drain electrode, and cover the entire substrate substrate.Following embodiment will illustrate the structure and the manufacture method of the utility model array base palte respectively based on technique scheme at above-mentioned two kinds of situations.
Embodiment two
The fragmentary top TV structure schematic diagram of the array base palte that Fig. 2 A provides for the utility model embodiment two.Fig. 2 B dissects structural representation among Fig. 2 A along the side-looking of A-A line.Shown in Fig. 2 A and Fig. 2 B, the array base palte of present embodiment comprises underlay substrate 1, and formation pixel electrode 11, pixel thin film resilient coating 20, grid line 2, data wire 5, gate electrode 3, gate insulation layer 4, active layer 6, source electrode 7, drain electrode 8, passivation layer 9 contact via hole 10 with first on the underlay substrate 1.
Wherein, pixel electrode 11 directly is formed on the underlay substrate 1, and pixel thin film resilient coating 20 is formed on the pixel electrode 11; Grid line 2 and gate electrode 3 are formed on the pixel thin film resilient coating 20; For simplified manufacturing technique, but pixel electrode 11, pixel thin film resilient coating 20 and grid line 2 and gate electrode 3 one-shot formings promptly form pixel electrode 11, pixel thin film resilient coating 20 and grid line 2 and gate electrode 3 simultaneously by a composition technology.
Further, the array base palte of present embodiment also comprises: gate insulation layer 4, the first contact via hole 10, data wire 5, active layer 6, source electrode 7, drain electrode 8 and passivation layer 9.Wherein, gate insulation layer 4 is formed on grid line 2 and the gate electrode 3; The first contact via hole 10 is formed on gate insulation layer 4 and the pixel thin film resilient coating 20, and runs through gate insulation layer 4 and pixel thin film resilient coating 20, exposed portions serve pixel electrode 11.Data wire 5 is formed on the gate insulation layer 4; Active layer 6, source electrode 7 and drain electrode 8 are formed on the gate insulation layer 4, wherein, active layer 6 is formed on source electrode 7 and the drain electrode 8, and be connected with drain electrode 8 with source electrode 7 respectively, to form the TFT raceway groove, source electrode 7 is connected with data wire 5, and drain electrode 8 is connected with pixel electrode 11 by the first contact via hole 10.Passivation layer 9 is formed on active layer 6, source electrode 7 and drain electrode 8 tops and covers underlay substrate 1, i.e. all patterns on the passivation layer 9 covering underlay substrates 1.
The array base palte of present embodiment, between pixel electrode and grid line and gate electrode, be provided with the pixel thin film resilient coating, this structure can be avoided producing the slit between pixel electrode and grid line and the gate electrode, can guarantee the adhesion between pixel electrode and grid line and the gate electrode, prevent that grid line and gate electrode from coming off, and then guaranteed the yield of TFT.
Fig. 2 C is the flow chart of manufacture method of the array base palte of the utility model embodiment two.Shown in Fig. 2 C, the making flow process of the array base palte of present embodiment comprises:
Step 202, using plasma strengthens chemical vapour deposition (CVD) (Plasma Chemical VaporDeposition; Abbreviate as: PECVD) method deposit thickness on the transparent pixels film is about 1000～4000 inorganic insulation layer film, perhaps is 1500～5000 organic insulation layer film by spin coating mode applied thickness; Above-mentioned organic insulation layer film or inorganic insulation layer film are in order to form the pixel thin film resilient coating in the present embodiment.
Step 203, thickness is about 3000～5000 grid metallic film on the method deposition of sputter or thermal evaporation adopting on the above-mentioned film, wherein, the grid metallic film can be selected chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum metal or alloy such as (Mo) for use, it can be single layer structure, also can form sandwich construction by multiple layer metal.
Step 204 is carried out composition by composition technology to above-mentioned film, forms the pattern that comprises grid line, gate electrode, pixel thin film resilient coating and pixel electrode.
Step 205 on the underlay substrate that forms above-mentioned pattern, adopts PECVD method deposit thickness to be about 3000～5000 gate insulation layer film; Wherein, the gate insulation layer film can adopt oxide, nitride or oxynitrides, and wherein employed reacting gas can be SiH in the PECVD process
4, NH
3, N
2Or SiH
2Cl
2, NH
3
Step 206 is carried out composition by composition technology to above-mentioned film, forms to comprise that gate insulation layer contacts the pattern of via hole with first; The described first contact via hole runs through gate insulation layer and pixel thin film resilient coating, and the exposed portions serve pixel electrode.
Step 207 on the underlay substrate that forms above-mentioned pattern, adopts sputter or thermal evaporation method to deposit a layer thickness and is about 2000～4000 source leakage metallic film; Wherein, metallic film is leaked in this source can be chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum metal and alloys such as (Mo), and it can be a kind of single layer structure, also can be a kind of sandwich construction.
Step 208, above-mentioned film is carried out composition, form the pattern that comprises data wire, source electrode and drain electrode by composition technology; Wherein, drain electrode is connected with pixel electrode by the first contact via hole.
Step 209 is forming on the underlay substrate of above-mentioned pattern, and adopting sputtering method to deposit a layer thickness is 300～1500 active layer film; The active layer film is generally metal-oxide semiconductor (MOS), can select amorphous indium oxide gallium zinc (a-IGZO) for use, also can select other metal oxide semiconductor material for use.
Step 210 is carried out composition by composition technology to above-mentioned film, forms the pattern that comprises active layer; Wherein, metal oxide semiconductor layer is placed on source electrode and the drain electrode, after forming source electrode and drain electrode, form active layer, to the damage of metal oxide semiconductor layer, help improving the characteristic of TFT when having avoided forming source electrode and drain electrode pattern by composition technology.
Step 211, on the underlay substrate that forms above-mentioned pattern, adopting PECVD method successive sedimentation one layer thickness is 1000～4000 about passivation layer films, forms the passivation layer that covers the entire substrate substrate.
Can form the structure of the array base palte of present embodiment by above-mentioned steps, but be not limited to this, also can adopt other manufacturing process to form the structure of present embodiment array base palte.
Wherein, above-mentioned composition technology is included in and applies photoresist on the film, utilizes mask plate that photoresist is carried out exposure imaging and forms the photoresist pattern, the photoresist pattern is carried out etching, and removes the residue photoresist to form the pattern in the above steps.Because composition technology is those skilled in the art's common practise, and those skilled in the art can understand and realize the process of this composition technology according to the structure of the array base palte of present embodiment, and therefore, present embodiment repeats no more.
The array base palte of present embodiment, by in manufacturing process, between transparent pixels film and grid metallic film, depositing organic insulating layer of thin-film or inorganic insulation layer film, the slit that produces so that the transparent pixels film because of the influence that is subjected to high temperature or annealing process transformation for stress is taken place is cushioned, having guaranteed does not have the slit between transparent pixels film and the grid metallic film, guarantee the adhesion between grid metallic film and the transparent pixels film, prevent that the grid metallic film from coming off, and then make the array base palte of present embodiment have higher yield.
Embodiment three
The fragmentary top TV structure schematic diagram of the array base palte that Fig. 3 A provides for the utility model embodiment three.Fig. 3 B dissects structural representation among Fig. 3 A along the side-looking of A-A line.Shown in Fig. 3 A and Fig. 3 B, the array base palte of present embodiment comprises underlay substrate 1, is formed with grid line 2, gate electrode 3, gate insulation layer 4, active layer 6, pixel electrode 11, pixel thin film resilient coating 20, source electrode 7, drain electrode 8, data wire 5 and passivation layer 9 on the underlay substrate 1.
Wherein, pixel thin film resilient coating 20 is formed between pixel electrode 11 and the drain electrode 8; Concrete pixel electrode 11 is positioned at pixel thin film resilient coating 20 belows, and drain electrode 8 is formed at pixel thin film resilient coating 20 tops, and is formed with the second contact via hole 30 on the pixel thin film resilient coating, and drain electrode 8 is connected with pixel electrode 11 by the second contact via hole 30.
Further, in the array base palte of present embodiment, grid line 2 and gate electrode 3 are formed directly on the underlay substrate 1; Gate insulation layer 4 is formed on grid line 2 and gate electrode 3 tops and covering underlay substrate 1; Pixel electrode 11 is formed on the gate insulation layer 4; Active layer 6 is formed on source electrode 7 and the drain electrode 8 and is connected with drain electrode 8 with source electrode 7 respectively, with formation TFT raceway groove; Wherein, data wire 5 forms with layer with source electrode 7 and drain electrode 8.Passivation layer 9 is covered on the underlay substrate 1 of patterns such as forming data wire 5, source electrode 7 and drain electrode 8.
The array base palte of present embodiment is provided with the pixel thin film resilient coating between pixel electrode and drain electrode.This pixel thin film resilient coating is in the manufacturing process of array base palte, can change stress and the slit that produces is cushioned to transparent pixels film Yin Gaowen or anneal process affects, make transparent pixels film and source leak between the metallic film and do not have the slit, the adhesion between metallic film and the transparent pixels film is leaked in the assurance source, and then make the drain electrode and the pixel electrode difficult drop-off of formation, improved the yield of present embodiment array base palte.
Fig. 3 C is the flow chart of manufacture method of the array base palte of the utility model embodiment three.Shown in Fig. 3 C, this manufacture method specifically comprises:
Step 301 adopts the method for sputter or thermal evaporation to deposit a layer thickness on underlay substrate and is about 1500～5000 grid metallic film.Wherein, underlay substrate can be transparent glass substrate or quartz base plate.The grid metallic film can use a kind of material, for example: chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), aluminium (Al), copper metal or alloy such as (Cu); Also can use the material that is combined into by multiple layer metal.
Step 302 is carried out composition by composition technology to above-mentioned grid metallic film, forms the pattern that comprises grid line and gate electrode.
Step 303, on the underlay substrate that forms above-mentioned pattern, adopt PECVD method successive sedimentation one layer thickness to be about 3000～5000 gate insulation layer film, then the method deposit thickness by sputter or thermal evaporation is about 300～1000 transparent pixels film, i.e. amorphous ITO; Wherein, the gate insulation layer film can adopt oxide, nitride or oxynitrides, and wherein employed reacting gas can be SiH in the PECVD process
4, NH
3, N
2Or SiH
2Cl
2, NH
3
Step 304, on amorphous ITO, depositing a layer thickness by the PECVD method is 1000～4000 inorganic insulation layer film, perhaps spin coating mode applied thickness is 1500～5000 one deck organic insulation layer films;
Step 305 is carried out composition by composition technology to above-mentioned film, forms to comprise that gate insulation layer, pixel electrode, pixel thin film resilient coating contact the pattern of via hole with second;
Step 306, on the underlay substrate that forms above-mentioned pattern, the method deposit thickness that adopts sputter or thermal evaporation is 3000～5000 source leakage metallic film; Wherein, metallic film is leaked in the source can select chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum metal or alloy such as (Mo) for use, the sandwich construction that it can also can be made up of multiple layer metal for single layer structure.
Step 307, above-mentioned film is carried out composition, form the pattern that comprises data wire, source electrode, drain electrode by composition technology; Wherein, drain electrode is connected with pixel electrode by the second contact via hole.
Step 308 on the underlay substrate that forms above-mentioned pattern, adopts sputtering method deposition one deck active layer film; Wherein, the active layer film can be that 1000～3000 semiconductor layer film and thickness are that 1000～3000 ohmic contact layer film is formed by thickness.The active layer film is generally metal-oxide semiconductor (MOS), can select amorphous indium oxide gallium zinc (a-IGZO) for use, also can select other metal oxide semiconductor material for use.
Step 309 is carried out composition by composition technology to above-mentioned film, forms the pattern that comprises active layer; Wherein, the metal-oxide semiconductor layer is placed on source electrode and the drain electrode, after forming source electrode and drain electrode, form active layer, to the damage of metal oxide semiconductor layer, help improving the characteristic of TFT when having avoided forming source electrode and drain electrode pattern by composition technology.
Step 310 is forming on the underlay substrate of above-mentioned pattern, is 1000～4000 passivation layer film by PECVD method successive sedimentation one layer thickness, to form the passivation layer that covers the entire substrate substrate.Wherein, the passivation layer film can adopt oxide, nitride or oxynitrides, and wherein employed reacting gas can be SiH in the PECVD process
4, NH
3, N
2Or SiH
2Cl
2, NH
3
Wherein, above-mentioned composition technology is included in and applies photoresist on the film, utilizes mask plate that photoresist is carried out exposure imaging and forms the photoresist pattern, the photoresist pattern is carried out etching, and removes the residue photoresist to form the pattern in the above steps.Because composition technology is those skilled in the art's common practise, and those skilled in the art can understand and realize the process of this composition technology according to the structure of the array base palte of present embodiment, and therefore, present embodiment repeats no more.
Can form the array base palte of present embodiment by above-mentioned steps, but be not limited to this, also can adopt other manufacturing process to form the array base-plate structure of present embodiment.
The array base palte of present embodiment, by in manufacturing process, leaking organic insulating layer of thin-film of deposition or inorganic insulation layer film between the metallic film at transparent pixels film and source, the slit that produces so that the transparent pixels film because of the influence that is subjected to high temperature or annealing process transformation for stress is taken place is cushioned, having guaranteed does not have the slit between transparent pixels film and the source leakage metallic film, the adhesion between metallic film and the transparent pixels film is leaked in the assurance source, the source that prevents is leaked metallic film and is come off, and then makes the array base palte of present embodiment have higher yield.
Implement four
The utility model embodiment three provides a kind of LCD, comprises parts such as outside framework, liquid crystal panel and drive circuit.Wherein liquid crystal panel is by the array base palte that color membrane substrates and the utility model provide box to be formed, and is filled with liquid crystal layer betwixt.And array base palte wherein can be provided by the array base palte that provides with the utility model embodiment.Wherein discuss no longer in detail in the present embodiment, can see the utility model the foregoing description for details about the structure of array base palte and the method flow of manufacturing array substrate.
In sum, therefore LCD of the present utility model, has the advantage of better performances equally owing to have the array base palte that the utility model provides.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be finished by the relevant hardware of program command, aforesaid program can be stored in the computer read/write memory medium, this program is carried out the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
It should be noted that at last: above embodiment only in order to the explanation the technical solution of the utility model, is not intended to limit; Although the utility model is had been described in detail with reference to previous embodiment, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of each embodiment technical scheme of the utility model.
Claims (10)
1. an array base palte comprises underlay substrate, is formed with conductive pattern and insulating barrier on the described underlay substrate, it is characterized in that, described insulating barrier comprises at least:
The pixel thin film resilient coating, be formed at pixel electrode and and described pixel electrode adjacent conductive pattern between.
2. array base palte according to claim 1 is characterized in that, described conductive pattern and insulating barrier also comprise: described pixel electrode and grid line and gate electrode;
Described pixel thin film resilient coating is formed between described pixel electrode and described grid line and the gate electrode.
3. array base palte according to claim 2 is characterized in that:
Described pixel electrode is formed on the described underlay substrate;
Described grid line and gate electrode are formed on the described pixel thin film resilient coating;
Described pixel electrode, described pixel thin film resilient coating and described grid line and gate electrode one-shot forming.
4. array base palte according to claim 3 is characterized in that, described conductive pattern and insulating barrier also comprise:
Gate insulation layer is formed on described grid line and gate electrode top and covers described underlay substrate;
The first contact via hole is formed on described pixel thin film resilient coating and the described gate insulation layer, and runs through described pixel thin film resilient coating and described gate insulation layer;
Data wire is formed on the described gate insulation layer;
Source electrode and drain electrode are formed on the described gate insulation layer, and described drain electrode is connected with described pixel electrode by the described first contact via hole;
Active layer is formed on described source electrode and the drain electrode, and is connected with drain electrode with described source electrode;
Passivation layer is formed on described active layer, described source electrode and drain electrode top and covers described underlay substrate.
5. array base palte according to claim 1 is characterized in that, described conductive pattern and insulating barrier also comprise: described pixel electrode and drain electrode;
Described pixel thin film resilient coating is formed between described pixel electrode and the described drain electrode, and is formed with the second contact via hole on the described pixel thin film resilient coating; Described drain electrode is connected with described pixel electrode by the described second contact via hole.
6. array base palte according to claim 5 is characterized in that:
Described drain electrode is formed at described pixel thin film resilient coating top;
Described pixel thin film resilient coating is formed at described pixel electrode top;
Described pixel electrode, described pixel thin film resilient coating contact the via hole one-shot forming with described second.
7. array base palte according to claim 6 is characterized in that, described conductive pattern and insulating barrier also comprise:
Grid line and gate electrode are formed on the described underlay substrate;
Gate insulation layer is formed on described grid line and the gate electrode;
Active layer is formed on source electrode and the described drain electrode, and is connected with described drain electrode with described source electrode;
Passivation layer is formed on described active layer, described source electrode and the described drain electrode and covers described underlay substrate;
Described pixel electrode is formed on the described gate insulation layer.
8. according to each described array base palte of claim 1-7, it is characterized in that described pixel thin film resilient coating is that thickness is 1000～4000 inorganic insulation layer.
9. according to each described array base palte of claim 1-7, it is characterized in that described pixel thin film resilient coating is that thickness is 1500～5000 organic insulator.
10. LCD that comprises each described array base palte of claim 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206817009U CN202009000U (en) | 2010-12-16 | 2010-12-16 | Array substrate and liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206817009U CN202009000U (en) | 2010-12-16 | 2010-12-16 | Array substrate and liquid crystal display |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202009000U true CN202009000U (en) | 2011-10-12 |
Family
ID=44750659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010206817009U Expired - Lifetime CN202009000U (en) | 2010-12-16 | 2010-12-16 | Array substrate and liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202009000U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956713A (en) * | 2012-10-19 | 2013-03-06 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
| CN103700668A (en) * | 2013-12-19 | 2014-04-02 | 合肥京东方光电科技有限公司 | Array substrate and preparation method thereof as well as display device |
| CN104280967A (en) * | 2014-10-31 | 2015-01-14 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate, display panel and display device |
| CN105633103A (en) * | 2016-04-12 | 2016-06-01 | 京东方科技集团股份有限公司 | Array substrate, display device and manufacturing method of array substrate |
-
2010
- 2010-12-16 CN CN2010206817009U patent/CN202009000U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956713A (en) * | 2012-10-19 | 2013-03-06 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
| US9502570B2 (en) | 2012-10-19 | 2016-11-22 | Boe Technology Group Co., Ltd. | Thin film transistor and manufacturing method thereof, an array substrate and a display device |
| CN103700668A (en) * | 2013-12-19 | 2014-04-02 | 合肥京东方光电科技有限公司 | Array substrate and preparation method thereof as well as display device |
| CN104280967A (en) * | 2014-10-31 | 2015-01-14 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate, display panel and display device |
| CN105633103A (en) * | 2016-04-12 | 2016-06-01 | 京东方科技集团股份有限公司 | Array substrate, display device and manufacturing method of array substrate |
| CN105633103B (en) * | 2016-04-12 | 2018-12-18 | 京东方科技集团股份有限公司 | A kind of production method of array substrate, display device and array substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102468306B (en) | Array base plate, liquid crystal display, and manufacturing method for array substrate | |
| CN102034750B (en) | Array substrate and manufacturing method thereof | |
| CN101957529B (en) | FFS (Fringe Field Switching) type TFT-LCD (Thin Film Transistor Liquid Crystal Display) array substrate and manufacturing method thereof | |
| CN102446925B (en) | Array base plate, liquid crystal display and manufacturing method for array base plate | |
| CN102148196B (en) | TFT-LCD (thin film transistor-liquid crystal display) array substrate and manufacturing method therefor | |
| CN102629577B (en) | TFT array substrate and manufacturing method thereof and display device | |
| US11398505B2 (en) | Display substrate and manufacturing method thereof, display panel, and display device | |
| US20140061635A1 (en) | Array Substrate, Manufacturing Method And The Display Device Thereof | |
| JP5685565B2 (en) | Thin film transistor and manufacturing method thereof | |
| CN101561604B (en) | TFT-LCD array substrate structure and manufacturing method thereof | |
| KR20100075026A (en) | Thin film transistor array substrate and method of fabricating the same | |
| JP2015521383A (en) | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY PANEL, AND DISPLAY DEVICE | |
| CN102053435A (en) | Liquid crystal display device and method for fabricating the same | |
| CN103700665A (en) | Metal oxide thin film transistor array substrate and manufacturing method and display method thereof | |
| CN102637648B (en) | Thin-film-transistor liquid crystal display, array substrate and manufacturing method of array substrate | |
| CN102468243B (en) | TFT (Thin Film Transistor) array substrate, manufacturing method and liquid crystal display device | |
| CN103887245A (en) | Manufacturing method of array substrate | |
| CN103762199A (en) | Method for manufacturing array base plate of liquid crystal display | |
| CN103715266A (en) | Oxide thin-film transistor, manufacturing method of array substrate and display device | |
| CN102569185A (en) | Array substrate, production method thereof and liquid crystal display | |
| CN202009000U (en) | Array substrate and liquid crystal display | |
| US9048322B2 (en) | Display substrate and method of manufacturing the same | |
| CN102456620B (en) | Array substrate and manufacturing method thereof | |
| CN101963726A (en) | FFS (Fringe Field Switching) type TFT-LCD (Thin Film Transistor-Liquid Crystal Display) array base plate and manufacturing method thereof | |
| CN104916649A (en) | Array substrate and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20111012 |
|
| CX01 | Expiry of patent term |