WO2020073617A1 - Manufacturing method for thin-film transistor substrate, and thin-film transistor substrate - Google Patents

Manufacturing method for thin-film transistor substrate, and thin-film transistor substrate Download PDF

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Publication number
WO2020073617A1
WO2020073617A1 PCT/CN2019/079097 CN2019079097W WO2020073617A1 WO 2020073617 A1 WO2020073617 A1 WO 2020073617A1 CN 2019079097 W CN2019079097 W CN 2019079097W WO 2020073617 A1 WO2020073617 A1 WO 2020073617A1
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Prior art keywords
film transistor
thin film
transistor substrate
layer
manufacturing
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PCT/CN2019/079097
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French (fr)
Chinese (zh)
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陈书志
陈俊吉
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020073617A1 publication Critical patent/WO2020073617A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed

Definitions

  • the present invention relates to the field of display technology, and in particular, to a method for manufacturing a thin film transistor substrate and a thin film transistor substrate.
  • the liquid crystal display panel is composed of a thin film transistor array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
  • multiple processes such as four Process
  • the more processes required the higher the production cost of the TFT array substrate, and the increased process time and complexity.
  • the existing thin film transistor substrate manufacturing method requires more manufacturing processes, which results in a higher production cost of the thin film transistor substrate.
  • a method for manufacturing a thin film transistor substrate including:
  • the second metal layer is made of transparent conductive material.
  • the manufacturing method of the thin film transistor substrate further includes:
  • the passivation layer covers the pixel electrode, and the manufacturing method of the thin film transistor substrate further includes:
  • the thickness of the second metal layer is greater than or equal to half the thickness of the passivation layer.
  • the transparent conductive material is indium tin oxide, indium zinc oxide or indium tin zinc oxide.
  • a method for manufacturing a thin film transistor substrate including:
  • the second metal layer is made of transparent conductive material.
  • the manufacturing method of the thin film transistor substrate further includes:
  • the passivation layer covers the pixel electrode, and the manufacturing method of the thin film transistor substrate further includes:
  • the thickness of the second metal layer is greater than or equal to half the thickness of the passivation layer.
  • the transparent conductive material is indium tin oxide, indium zinc oxide or indium tin zinc oxide.
  • the invention also provides a method for manufacturing a thin film transistor substrate, including:
  • a grid provided on the substrate
  • a gate insulating layer provided on the substrate and covering the gate
  • a second metal layer disposed on the gate insulating layer, the second metal layer includes a source electrode, a drain electrode, and a pixel electrode;
  • the source electrode, the drain electrode and the pixel electrode are all made of transparent conductive material.
  • the thin film transistor substrate further includes a passivation layer disposed on the gate insulating layer and covering the source electrode and the drain electrode.
  • the passivation layer is provided with a through hole exposing the pixel electrode.
  • the thickness of the second metal layer is greater than or equal to half the thickness of the passivation layer.
  • the transparent conductive material is indium tin oxide, indium zinc oxide or indium tin zinc oxide.
  • the second metal layer is formed of a transparent conductive metal, so that the drain electrode can be directly extended as a pixel electrode, and the source electrode, the drain electrode, and the pixel electrode are formed by the same etching process, thereby reducing the process steps, reducing production costs, and process time And complexity.
  • FIG. 1 is a schematic diagram of a manufacturing process of a thin film transistor substrate in a specific embodiment of the present invention
  • FIG. 2 is a schematic diagram of forming a gate and a gate insulating layer in a specific embodiment of the present invention
  • FIG. 3 is a schematic diagram of a semiconductor layer in a specific embodiment of the present invention.
  • FIG. 4 is a schematic diagram of forming a second metal layer in a specific embodiment of the present invention.
  • FIG. 5 is a schematic diagram of forming a source electrode, a drain electrode and a pixel electrode in a specific embodiment of the present invention
  • FIG. 6 is a schematic diagram of a passivation layer in a specific embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a thin film transistor substrate in a specific embodiment of the present invention.
  • the present invention is directed to the existing manufacturing method of the thin film transistor substrate, which requires many manufacturing processes, resulting in a technical problem of high production cost of the thin film transistor substrate.
  • a method for manufacturing a thin film transistor substrate as shown in FIG. 1, the method for manufacturing a thin film transistor substrate includes:
  • the second metal layer is made of transparent conductive material.
  • the second metal layer is formed of a transparent conductive metal, so that the drain electrode can be directly extended as a pixel electrode, and the source electrode, the drain electrode, and the pixel electrode are formed by the same etching process, thereby reducing the process steps, reducing production costs, process time and the complexity.
  • the transparent conductive material is indium tin oxide (ITO), indium zinc oxide (IZO) or indium tin zinc oxide (ITZO).
  • the first metal layer is formed on the substrate 10 by a sputtering method; it should be noted that in actual implementation, the first metal layer may also be formed by chemical vapor deposition or other physical deposition methods.
  • the process of patterning the first metal layer to form the gate electrode 20 it is preferable to use a mixed solution of nitric acid, phosphoric acid and acetic acid to wet etch the first metal layer; it needs to be understood that In specific implementation, other methods may also be used to perform wet etching on the first metal layer, which is not listed here one by one.
  • the semiconductor layer 40 is patterned.
  • the material of the semiconductor layer 40 is preferably polysilicon.
  • the semiconductor layer 40 may first deposit an amorphous silicon layer, and then, perform a rapid thermal annealing step on the amorphous silicon layer to make the The amorphous silicon layer is recrystallized into a polysilicon layer.
  • a second metal layer 50 is formed on the semiconductor layer 40 and the gate insulating layer 30, and the second metal layer 50 is made of a transparent conductive material.
  • the second metal layer 50 is preferably deposited by sputtering.
  • the second metal layer 50 may be formed in other ways according to process conditions and production costs.
  • the second metal layer 50 is etched to form the source electrode 51, the drain electrode 52 and the pixel electrode 53.
  • the manufacturing method of the thin film transistor substrate 10 further includes:
  • the passivation layer 60 plays a role of isolation and protection.
  • the passivation layer 60 covers the pixel electrode 53, and the manufacturing method of the thin film transistor substrate 10 further includes:
  • the thickness of the second metal layer 50 is greater than or equal to half the thickness of the passivation layer 60.
  • the resistance of the second metal layer 50 made of a transparent conductive material is relatively large. By increasing the thickness of the second metal layer 50, the resistance is reduced, and at the same time, the passivation layer 60 prevents the pixel electrode 53 has an impact.
  • the present invention also provides a thin film transistor substrate 10.
  • the thin film transistor substrate 10 includes a substrate 10, a gate electrode 20 provided on the substrate 10, and an arrangement A gate insulating layer 30 on the substrate 10 and covering the gate 20, a semiconductor layer 40 provided on the gate insulating layer 30, and a second metal layer provided on the gate insulating layer 30 50.
  • the second metal layer 50 includes a source electrode 51, a drain electrode 52, and a pixel electrode 53.
  • the source electrode 51, the drain electrode 52, and the pixel electrode 53 are all made of a transparent conductive material.
  • the second metal layer 50 is formed of a transparent conductive metal, so that the electrode of the drain 52 can be directly extended as the pixel electrode 53, and the source 51, the drain 52, and the pixel electrode 53 are formed by the same etching process, thereby reducing the manufacturing process and reducing Production cost, process time and complexity.
  • the transparent conductive material is indium tin oxide, indium zinc oxide, or indium tin zinc oxide.
  • the thin film transistor substrate 10 further includes a passivation layer 60 disposed on the gate insulating layer 30 and covering the source electrode 51 and the drain electrode 52.
  • the passivation layer 60 is provided with a through hole 70 exposing the pixel electrode 53.
  • the thickness of the second metal layer 50 is greater than or equal to half the thickness of the passivation layer 60.
  • the second metal layer 50 is formed of a transparent conductive metal, so that the drain 52 electrode can be directly extended as the pixel electrode 53, and the source 51, the drain 52 and the pixel electrode 53 are subjected to the same etching process Formed to reduce process steps, reduce production costs, process time and complexity.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

Provided is a manufacturing method for a thin-film transistor substrate, the method comprising: forming a first metal layer on a substrate; etching the first metal layer to form a gate electrode; forming, on the substrate, a gate insulation layer covering the gate electrode; forming a semiconductor layer on the gate insulation layer; forming a second metal layer on the semiconductor layer and the gate insulation layer; and etching the second metal layer to form a source electrode, a drain electrode and a pixel electrode, wherein the second metal layer is made of a transparent conductive material.

Description

薄膜晶体管基板的制作方法及其薄膜晶体管基板Thin film transistor substrate manufacturing method and thin film transistor substrate 技术领域Technical field
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管基板的制作方法及其薄膜晶体管基板。The present invention relates to the field of display technology, and in particular, to a method for manufacturing a thin film transistor substrate and a thin film transistor substrate.
背景技术Background technique
液晶显示面板由薄膜晶体管阵列基板、彩膜基板以及设置于阵列基板和彩膜基板之间的液晶层构成，而现有技术中，在薄膜晶体管阵列基板制作中，需要通过多道制程（例如四道制程），而需要的制程越多，会导致薄膜晶体管阵列基板的生产成本越高，增加制程时间及复杂度。The liquid crystal display panel is composed of a thin film transistor array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. In the prior art, in the manufacture of the thin film transistor array substrate, multiple processes (such as four Process), and the more processes required, the higher the production cost of the TFT array substrate, and the increased process time and complexity.
技术问题technical problem
现有的薄膜晶体管基板的制作方法，所需要的制程较多，导致薄膜晶体管基板的生产成本较高。The existing thin film transistor substrate manufacturing method requires more manufacturing processes, which results in a higher production cost of the thin film transistor substrate.
技术解决方案Technical solution
一种薄膜晶体管基板的制作方法，包括：A method for manufacturing a thin film transistor substrate, including:
S10、采用溅射法或化学气相沉积法在基板上形成第一金属层；S10. Use a sputtering method or a chemical vapor deposition method to form a first metal layer on the substrate;
S20、对所述第一金属层进行刻蚀，以形成栅极；S20. Etching the first metal layer to form a gate;
S30、在所述基板上形成覆盖所述栅极的栅极绝缘层；S30, forming a gate insulating layer covering the gate on the substrate;
S40、在所述栅极绝缘层上形成半导体层；S40. Form a semiconductor layer on the gate insulating layer;
S50、在所述半导体层和所述栅极绝缘层上形成第二金属层；S50. Form a second metal layer on the semiconductor layer and the gate insulating layer;
S60、对所述第二金属层进行刻蚀，以形成源极、漏极以及像素电极；S60, etching the second metal layer to form a source electrode, a drain electrode, and a pixel electrode;
其中，所述第二金属层由透明导电材料制成。Wherein, the second metal layer is made of transparent conductive material.
优选的，所述薄膜晶体管基板的制作方法还包括：Preferably, the manufacturing method of the thin film transistor substrate further includes:
S70、在所述栅极绝缘层上形成覆盖所述源极和所述漏极的钝化层。S70. Form a passivation layer covering the source electrode and the drain electrode on the gate insulating layer.
优选的，所述钝化层覆盖所述像素电极，所述薄膜晶体管基板的制作方法还包括：Preferably, the passivation layer covers the pixel electrode, and the manufacturing method of the thin film transistor substrate further includes:
S80、在所述钝化层上形成通孔以露出所述像素电极。S80. Form a through hole on the passivation layer to expose the pixel electrode.
优选的，所述第二金属层的厚度大于或等于所述钝化层厚度的一半。Preferably, the thickness of the second metal layer is greater than or equal to half the thickness of the passivation layer.
优选的，所述透明导电材料为氧化铟锡、氧化铟锌或氧化铟锡锌。Preferably, the transparent conductive material is indium tin oxide, indium zinc oxide or indium tin zinc oxide.
一种薄膜晶体管基板的制作方法，包括：A method for manufacturing a thin film transistor substrate, including:
S10、在基板上形成第一金属层；S10. Form a first metal layer on the substrate;
S20、对所述第一金属层进行刻蚀，以形成栅极；S20. Etching the first metal layer to form a gate;
S30、在所述基板上形成覆盖所述栅极的栅极绝缘层；S30, forming a gate insulating layer covering the gate on the substrate;
S40、在所述栅极绝缘层上形成半导体层；S40. Form a semiconductor layer on the gate insulating layer;
S50、在所述半导体层和所述栅极绝缘层上形成第二金属层；S50. Form a second metal layer on the semiconductor layer and the gate insulating layer;
S60、对所述第二金属层进行刻蚀，以形成源极、漏极以及像素电极；S60, etching the second metal layer to form a source electrode, a drain electrode, and a pixel electrode;
其中，所述第二金属层由透明导电材料制成。Wherein, the second metal layer is made of transparent conductive material.
优选的，所述薄膜晶体管基板的制作方法还包括：Preferably, the manufacturing method of the thin film transistor substrate further includes:
S70、在所述栅极绝缘层上形成覆盖所述源极和所述漏极的钝化层。S70. Form a passivation layer covering the source electrode and the drain electrode on the gate insulating layer.
优选的，所述钝化层覆盖所述像素电极，所述薄膜晶体管基板的制作方法还包括：Preferably, the passivation layer covers the pixel electrode, and the manufacturing method of the thin film transistor substrate further includes:
S80、在所述钝化层上形成通孔以露出所述像素电极。S80. Form a through hole on the passivation layer to expose the pixel electrode.
优选的，所述第二金属层的厚度大于或等于所述钝化层厚度的一半。Preferably, the thickness of the second metal layer is greater than or equal to half the thickness of the passivation layer.
优选的，所述透明导电材料为氧化铟锡、氧化铟锌或氧化铟锡锌。Preferably, the transparent conductive material is indium tin oxide, indium zinc oxide or indium tin zinc oxide.
本发明还提供一种薄膜晶体管基板的制作方法，包括：The invention also provides a method for manufacturing a thin film transistor substrate, including:
基板；Substrate
设置在所述基板上的栅极；A grid provided on the substrate;
设置在所述基板上且覆盖所述栅极的栅极绝缘层；A gate insulating layer provided on the substrate and covering the gate;
设置在所述栅极绝缘层上的半导体层；A semiconductor layer provided on the gate insulating layer;
设置在所述栅极绝缘层上的第二金属层，所述第二金属层包括源极、漏极以及像素电极；A second metal layer disposed on the gate insulating layer, the second metal layer includes a source electrode, a drain electrode, and a pixel electrode;
其中，所述源极、漏极以及所述像素电极均采用透明导电材料制成。Wherein, the source electrode, the drain electrode and the pixel electrode are all made of transparent conductive material.
优选的，所述薄膜晶体管基板还包括设置在所述栅极绝缘层上且覆盖所述源极和所述漏极的钝化层。Preferably, the thin film transistor substrate further includes a passivation layer disposed on the gate insulating layer and covering the source electrode and the drain electrode.
优选的，所述钝化层上设置有露出所述像素电极的通孔。Preferably, the passivation layer is provided with a through hole exposing the pixel electrode.
优选的，所述第二金属层的厚度大于或等于所述钝化层厚度的一半。Preferably, the thickness of the second metal layer is greater than or equal to half the thickness of the passivation layer.
优选的，所述透明导电材料为氧化铟锡、氧化铟锌或氧化铟锡锌。Preferably, the transparent conductive material is indium tin oxide, indium zinc oxide or indium tin zinc oxide.
有益效果Beneficial effect
将第二金属层采用透明导电金属形成，从而可直接延伸漏极电极作为像素电极，将源极、漏极和像素电极通过同一道刻蚀工艺形成，从而减少制程工序，降低生产成本、制程时间及复杂度。The second metal layer is formed of a transparent conductive metal, so that the drain electrode can be directly extended as a pixel electrode, and the source electrode, the drain electrode, and the pixel electrode are formed by the same etching process, thereby reducing the process steps, reducing production costs, and process time And complexity.
附图说明BRIEF DESCRIPTION
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly explain the embodiments or the technical solutions in the prior art, the following will briefly introduce the drawings used in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only inventions. For some embodiments, those of ordinary skill in the art can obtain other drawings based on these drawings without creative work.
图1为本发明具体实施方式中薄膜晶体管基板的制作流程示意图；1 is a schematic diagram of a manufacturing process of a thin film transistor substrate in a specific embodiment of the present invention;
图2为本发明具体实施方式中形成栅极和栅极绝缘层时的示意图；2 is a schematic diagram of forming a gate and a gate insulating layer in a specific embodiment of the present invention;
图3为本发明具体实施方式中形成半导体层时的示意图；3 is a schematic diagram of a semiconductor layer in a specific embodiment of the present invention;
图4为本发明具体实施方式中形成第二金属层时的示意图；4 is a schematic diagram of forming a second metal layer in a specific embodiment of the present invention;
图5为本发明具体实施方式中形成源极、漏极和像素电极时的示意图；5 is a schematic diagram of forming a source electrode, a drain electrode and a pixel electrode in a specific embodiment of the present invention;
图6为本发明具体实施方式中形成钝化层时的示意图；6 is a schematic diagram of a passivation layer in a specific embodiment of the present invention;
图7为本发明具体实施方式中薄膜晶体管基板的结构示意图。7 is a schematic structural diagram of a thin film transistor substrate in a specific embodiment of the present invention.
附图标记：Reference mark:
10、基板；20、栅极；30、栅极绝缘层；40、半导体层；50、第二金属层；51、源极；52、漏极；53、像素电极；60、钝化层；70、通孔。10. Substrate; 20, Gate; 30, Gate insulating layer; 40, Semiconductor layer; 50, Second metal layer; 51, Source; 52, Drain; 53, Pixel electrode; 60, Passivation layer; 70 , Through holes.
本发明的实施方式Embodiments of the invention
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。The descriptions of the following embodiments refer to additional drawings to illustrate specific embodiments that can be implemented by the present invention. Directional terms mentioned in the present invention, such as [upper], [lower], [front], [rear], [left], [right], [inner], [outer], [side], etc., are for reference only Attach the direction of the schema. Therefore, the directional terminology is used to illustrate and understand the present invention, not to limit the present invention. In the figure, units with similar structures are indicated by the same reference numerals.
本发明针对现有的薄膜晶体管基板的制作方法，所需要的制程较多，导致薄膜晶体管基板的生产成本较高的技术问题，本发明可以解决该问题。The present invention is directed to the existing manufacturing method of the thin film transistor substrate, which requires many manufacturing processes, resulting in a technical problem of high production cost of the thin film transistor substrate.
一种薄膜晶体管基板的制作方法，如图1所示，所述薄膜晶体管基板的制作方法包括：A method for manufacturing a thin film transistor substrate, as shown in FIG. 1, the method for manufacturing a thin film transistor substrate includes:
S10、在基板上形成第一金属层；S10. Form a first metal layer on the substrate;
S20、对所述第一金属层进行刻蚀，以形成栅极；S20. Etching the first metal layer to form a gate;
S30、在所述基板上形成覆盖所述栅极的栅极绝缘层；S30, forming a gate insulating layer covering the gate on the substrate;
S40、在所述栅极绝缘层上形成半导体层；S40. Form a semiconductor layer on the gate insulating layer;
S50、在所述半导体层和所述栅极绝缘层上形成第二金属层；S50. Form a second metal layer on the semiconductor layer and the gate insulating layer;
S60、对所述第二金属层进行刻蚀，以形成源极、漏极以及像素电极；S60, etching the second metal layer to form a source electrode, a drain electrode, and a pixel electrode;
其中，所述第二金属层由透明导电材料制成。Wherein, the second metal layer is made of transparent conductive material.
第二金属层采用透明导电金属形成，从而可直接延伸漏极电极作为像素电极，将源极、漏极和像素电极通过同一道刻蚀工艺形成，从而减少制程工序，降低生产成本、制程时间及复杂度。The second metal layer is formed of a transparent conductive metal, so that the drain electrode can be directly extended as a pixel electrode, and the source electrode, the drain electrode, and the pixel electrode are formed by the same etching process, thereby reducing the process steps, reducing production costs, process time and the complexity.
需要说明的是，所述透明导电材料为铟锡氧化物(ITO)、铟锌氧化物(IZO)或铟锡锌氧化物(ITZO)。It should be noted that the transparent conductive material is indium tin oxide (ITO), indium zinc oxide (IZO) or indium tin zinc oxide (ITZO).
具体的，如图2所示，在基板10上形成第一金属层，并对所述第一金属层进行图案化处理，以形成图案化的栅极20后，在所述基板10上形成覆盖所述栅极20的栅极绝缘层30。Specifically, as shown in FIG. 2, after forming a first metal layer on the substrate 10 and patterning the first metal layer to form a patterned gate 20, a cover is formed on the substrate 10 The gate insulating layer 30 of the gate 20.
在一实施例中，采用溅射法在基板10形成所述第一金属层；需要说明的是，在实际实施中，也可采用化学气相沉积或其他物理沉积法形成第一金属层。In one embodiment, the first metal layer is formed on the substrate 10 by a sputtering method; it should be noted that in actual implementation, the first metal layer may also be formed by chemical vapor deposition or other physical deposition methods.
其中，对所述第一金属层进行图案化处理以形成栅极20的过程中，优选使用硝酸、磷酸以及醋酸的混合液对所述第一金属层进行湿法刻蚀；需要理解的是，在具体实施中，也可使用其他的方式对所述第一金属层进行湿法刻蚀，此处不一一列举。In the process of patterning the first metal layer to form the gate electrode 20, it is preferable to use a mixed solution of nitric acid, phosphoric acid and acetic acid to wet etch the first metal layer; it needs to be understood that In specific implementation, other methods may also be used to perform wet etching on the first metal layer, which is not listed here one by one.
具体的，如图3所示，在所述栅极绝缘层30上形成半导体层40后，对半导体层40进行图案化处理。Specifically, as shown in FIG. 3, after the semiconductor layer 40 is formed on the gate insulating layer 30, the semiconductor layer 40 is patterned.
其中，所述半导体层40的材料优选为多晶硅，在本实施例中，所述半导体层40可先沉积一非晶硅层，接着，对该非晶硅层进行快速热退火步骤，以使该非晶硅层再结晶成一多晶硅层。Wherein, the material of the semiconductor layer 40 is preferably polysilicon. In this embodiment, the semiconductor layer 40 may first deposit an amorphous silicon layer, and then, perform a rapid thermal annealing step on the amorphous silicon layer to make the The amorphous silicon layer is recrystallized into a polysilicon layer.
具体的，如图4所示，在所述半导体层40和栅极绝缘层30上形成第二金属层50，所述第二金属层50由透明导电材料制成。Specifically, as shown in FIG. 4, a second metal layer 50 is formed on the semiconductor layer 40 and the gate insulating layer 30, and the second metal layer 50 is made of a transparent conductive material.
在本优选实施例中，优选使用溅射法沉积形成第二金属层50，当然，可以理解的是，在具体实施中，也可根据工艺条件和生产成本选用其他方式形成第二金属层50。In the preferred embodiment, the second metal layer 50 is preferably deposited by sputtering. Of course, it can be understood that, in specific implementation, the second metal layer 50 may be formed in other ways according to process conditions and production costs.
具体的，如图5所示，对所述第二金属层50进行刻蚀，以形成源极51、漏极52以及像素电极53。Specifically, as shown in FIG. 5, the second metal layer 50 is etched to form the source electrode 51, the drain electrode 52 and the pixel electrode 53.
具体的，如图6所示，所述薄膜晶体管基板10的制作方法还包括：Specifically, as shown in FIG. 6, the manufacturing method of the thin film transistor substrate 10 further includes:
S70、在所述栅极20绝缘层上形成覆盖所述源极51和所述漏极52的钝化层60。通过钝化层60起到隔绝保护作用。S70, forming a passivation layer 60 covering the source electrode 51 and the drain electrode 52 on the insulating layer of the gate electrode 20. The passivation layer 60 plays a role of isolation and protection.
具体的，如图7所示，所述钝化层60覆盖所述像素电极53，所述薄膜晶体管基板10的制作方法还包括：Specifically, as shown in FIG. 7, the passivation layer 60 covers the pixel electrode 53, and the manufacturing method of the thin film transistor substrate 10 further includes:
S80、在所述钝化层60上形成通孔70以露出所述像素电极53。直接延伸漏极52作为像素电极53的同时，不会妨碍像素显示功能。S80. Form a through hole 70 on the passivation layer 60 to expose the pixel electrode 53. The direct extension of the drain 52 as the pixel electrode 53 does not hinder the pixel display function.
具体的，所述第二金属层50的厚度大于或等于所述钝化层60厚度的一半。Specifically, the thickness of the second metal layer 50 is greater than or equal to half the thickness of the passivation layer 60.
需要说明的是，在实际应用中，发现透明导电材料制成的第二金属层50的电阻较大，通过提高第二金属层50的厚度，从而降低阻抗，同时防止钝化层60对像素电极53造成影响。It should be noted that in practical applications, it is found that the resistance of the second metal layer 50 made of a transparent conductive material is relatively large. By increasing the thickness of the second metal layer 50, the resistance is reduced, and at the same time, the passivation layer 60 prevents the pixel electrode 53 has an impact.
基于上述薄膜晶体管基板10的制作方法，本发明还提供一种薄膜晶体管基板10，如图7所示，所述薄膜晶体管基板10包括基板10、设置在所述基板10上的栅极20、设置在所述基板10上且覆盖所述栅极20的栅极绝缘层30、设置在所述栅极绝缘层30上的半导体层40以及设置在所述栅极绝缘层30上的第二金属层50。Based on the manufacturing method of the thin film transistor substrate 10 described above, the present invention also provides a thin film transistor substrate 10. As shown in FIG. 7, the thin film transistor substrate 10 includes a substrate 10, a gate electrode 20 provided on the substrate 10, and an arrangement A gate insulating layer 30 on the substrate 10 and covering the gate 20, a semiconductor layer 40 provided on the gate insulating layer 30, and a second metal layer provided on the gate insulating layer 30 50.
其中，所述第二金属层50包括源极51、漏极52以及像素电极53，所述源极51、漏极52以及所述像素电极53均采用透明导电材料制成。The second metal layer 50 includes a source electrode 51, a drain electrode 52, and a pixel electrode 53. The source electrode 51, the drain electrode 52, and the pixel electrode 53 are all made of a transparent conductive material.
第二金属层50采用透明导电金属形成，从而可直接延伸漏极52电极作为像素电极53，将源极51、漏极52和像素电极53通过同一道刻蚀工艺形成，从而减少制程工序，降低生产成本、制程时间及复杂度。The second metal layer 50 is formed of a transparent conductive metal, so that the electrode of the drain 52 can be directly extended as the pixel electrode 53, and the source 51, the drain 52, and the pixel electrode 53 are formed by the same etching process, thereby reducing the manufacturing process and reducing Production cost, process time and complexity.
需要说明的是，所述透明导电材料为氧化铟锡、氧化铟锌或氧化铟锡锌。It should be noted that the transparent conductive material is indium tin oxide, indium zinc oxide, or indium tin zinc oxide.
具体的，所述薄膜晶体管基板10还包括设置在所述栅极绝缘层30上且覆盖所述源极51和所述漏极52的钝化层60。Specifically, the thin film transistor substrate 10 further includes a passivation layer 60 disposed on the gate insulating layer 30 and covering the source electrode 51 and the drain electrode 52.
具体的，所述钝化层60上设置有露出所述像素电极53的通孔70。Specifically, the passivation layer 60 is provided with a through hole 70 exposing the pixel electrode 53.
具体的，所述第二金属层50的厚度大于或等于所述钝化层60厚度的一半。Specifically, the thickness of the second metal layer 50 is greater than or equal to half the thickness of the passivation layer 60.
本发明的有益效果为：将第二金属层50采用透明导电金属形成，从而可直接延伸漏极52电极作为像素电极53，将源极51、漏极52和像素电极53通过同一道刻蚀工艺形成，从而减少制程工序，降低生产成本、制程时间及复杂度。The beneficial effects of the present invention are: the second metal layer 50 is formed of a transparent conductive metal, so that the drain 52 electrode can be directly extended as the pixel electrode 53, and the source 51, the drain 52 and the pixel electrode 53 are subjected to the same etching process Formed to reduce process steps, reduce production costs, process time and complexity.
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。In summary, although the present invention has been disclosed as above with preferred embodiments, the above-mentioned preferred embodiments are not intended to limit the present invention. Those of ordinary skill in the art can do various things without departing from the spirit and scope of the present invention. Kind of changes and retouching, so the protection scope of the present invention is subject to the scope defined by the claims.

Claims (15)

  1. 一种薄膜晶体管基板的制作方法，其中，所述薄膜晶体管基板的制作方法包括：A method for manufacturing a thin film transistor substrate, wherein the method for manufacturing a thin film transistor substrate includes:
    S10、采用溅射法或化学气相沉积法在基板上形成第一金属层；S10. Use a sputtering method or a chemical vapor deposition method to form a first metal layer on the substrate;
    S20、对所述第一金属层进行刻蚀，以形成栅极；S20. Etching the first metal layer to form a gate;
    S30、在所述基板上形成覆盖所述栅极的栅极绝缘层；S30, forming a gate insulating layer covering the gate on the substrate;
    S40、在所述栅极绝缘层上形成半导体层；S40. Form a semiconductor layer on the gate insulating layer;
    S50、在所述半导体层和所述栅极绝缘层上形成第二金属层；S50. Form a second metal layer on the semiconductor layer and the gate insulating layer;
    S60、对所述第二金属层进行刻蚀，以形成源极、漏极以及像素电极；S60, etching the second metal layer to form a source electrode, a drain electrode, and a pixel electrode;
    其中，所述第二金属层由透明导电材料制成。Wherein, the second metal layer is made of transparent conductive material.
  2. 根据权利要求1所述的薄膜晶体管基板的制作方法，其中，所述薄膜晶体管基板的制作方法还包括：The method for manufacturing a thin film transistor substrate according to claim 1, wherein the method for manufacturing a thin film transistor substrate further comprises:
    S70、在所述栅极绝缘层上形成覆盖所述源极和所述漏极的钝化层。S70. Form a passivation layer covering the source electrode and the drain electrode on the gate insulating layer.
  3. 根据权利要求2所述的薄膜晶体管基板的制作方法，其中，所述钝化层覆盖所述像素电极，所述薄膜晶体管基板的制作方法还包括：The method for manufacturing a thin film transistor substrate according to claim 2, wherein the passivation layer covers the pixel electrode, and the method for manufacturing the thin film transistor substrate further includes:
    S80、在所述钝化层上形成通孔以露出所述像素电极。S80. Form a through hole on the passivation layer to expose the pixel electrode.
  4. 根据权利要求3所述的薄膜晶体管基板的制作方法，其中，所述第二金属层的厚度大于或等于所述钝化层厚度的一半。The method for manufacturing a thin film transistor substrate according to claim 3, wherein the thickness of the second metal layer is greater than or equal to half the thickness of the passivation layer.
  5. 根据权利要求1所述的薄膜晶体管基板的制作方法，其中，所述透明导电材料为氧化铟锡、氧化铟锌或氧化铟锡锌。The method for manufacturing a thin film transistor substrate according to claim 1, wherein the transparent conductive material is indium tin oxide, indium zinc oxide, or indium tin zinc oxide.
  6. 一种薄膜晶体管基板的制作方法，其中，所述薄膜晶体管基板的制作方法包括：A method for manufacturing a thin film transistor substrate, wherein the method for manufacturing a thin film transistor substrate includes:
    S10、在基板上形成第一金属层；S10. Form a first metal layer on the substrate;
    S20、对所述第一金属层进行刻蚀，以形成栅极；S20. Etching the first metal layer to form a gate;
    S30、在所述基板上形成覆盖所述栅极的栅极绝缘层；S30, forming a gate insulating layer covering the gate on the substrate;
    S40、在所述栅极绝缘层上形成半导体层；S40. Form a semiconductor layer on the gate insulating layer;
    S50、在所述半导体层和所述栅极绝缘层上形成第二金属层；S50. Form a second metal layer on the semiconductor layer and the gate insulating layer;
    S60、对所述第二金属层进行刻蚀，以形成源极、漏极以及像素电极；S60, etching the second metal layer to form a source electrode, a drain electrode, and a pixel electrode;
    其中，所述第二金属层由透明导电材料制成。Wherein, the second metal layer is made of transparent conductive material.
  7. 根据权利要求6所述的薄膜晶体管基板的制作方法，其中，所述薄膜晶体管基板的制作方法还包括：The method for manufacturing a thin film transistor substrate according to claim 6, wherein the method for manufacturing a thin film transistor substrate further comprises:
    S70、在所述栅极绝缘层上形成覆盖所述源极和所述漏极的钝化层。S70. Form a passivation layer covering the source electrode and the drain electrode on the gate insulating layer.
  8. 根据权利要求7所述的薄膜晶体管基板的制作方法，其中，所述钝化层覆盖所述像素电极，所述薄膜晶体管基板的制作方法还包括：The method for manufacturing a thin film transistor substrate according to claim 7, wherein the passivation layer covers the pixel electrode, and the method for manufacturing the thin film transistor substrate further includes:
    S80、在所述钝化层上形成通孔以露出所述像素电极。S80. Form a through hole on the passivation layer to expose the pixel electrode.
  9. 根据权利要求8所述的薄膜晶体管基板的制作方法，其中，所述第二金属层的厚度大于或等于所述钝化层厚度的一半。The method for manufacturing a thin film transistor substrate according to claim 8, wherein the thickness of the second metal layer is greater than or equal to half the thickness of the passivation layer.
  10. 根据权利要求6所述的薄膜晶体管基板的制作方法，其中，所述透明导电材料为氧化铟锡、氧化铟锌或氧化铟锡锌。The method for manufacturing a thin film transistor substrate according to claim 6, wherein the transparent conductive material is indium tin oxide, indium zinc oxide, or indium tin zinc oxide.
  11. 一种薄膜晶体管基板，其中，所述薄膜晶体管基板包括：A thin film transistor substrate, wherein the thin film transistor substrate includes:
    基板；Substrate
    设置在所述基板上的栅极；A grid provided on the substrate;
    设置在所述基板上且覆盖所述栅极的栅极绝缘层；A gate insulating layer provided on the substrate and covering the gate;
    设置在所述栅极绝缘层上的半导体层；A semiconductor layer provided on the gate insulating layer;
    设置在所述栅极绝缘层上的第二金属层，所述第二金属层包括源极、漏极以及像素电极；A second metal layer disposed on the gate insulating layer, the second metal layer includes a source electrode, a drain electrode, and a pixel electrode;
    其中，所述源极、漏极以及所述像素电极均采用透明导电材料制成。Wherein, the source electrode, the drain electrode and the pixel electrode are all made of transparent conductive material.
  12. 根据权利要求11所述的薄膜晶体管基板，其中，所述薄膜晶体管基板还包括设置在所述栅极绝缘层上且覆盖所述源极和所述漏极的钝化层。The thin film transistor substrate of claim 11, wherein the thin film transistor substrate further comprises a passivation layer provided on the gate insulating layer and covering the source electrode and the drain electrode.
  13. 根据权利要求12所述的薄膜晶体管基板，其中，所述钝化层上设置有露出所述像素电极的通孔。The thin film transistor substrate according to claim 12, wherein the passivation layer is provided with a through hole exposing the pixel electrode.
  14. 根据权利要求13所述的薄膜晶体管基板，其中，所述第二金属层的厚度大于或等于所述钝化层厚度的一半。The thin film transistor substrate of claim 13, wherein the thickness of the second metal layer is greater than or equal to half the thickness of the passivation layer.
  15. 根据权利要求11所述的薄膜晶体管基板，其中，所述透明导电材料为氧化铟锡、氧化铟锌或氧化铟锡锌。The thin film transistor substrate according to claim 11, wherein the transparent conductive material is indium tin oxide, indium zinc oxide, or indium tin zinc oxide.
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