WO2020073617A1 - Procédé de fabrication de substrat de transistor à couches minces, et substrat de transistor à couches minces - Google Patents

Procédé de fabrication de substrat de transistor à couches minces, et substrat de transistor à couches minces Download PDF

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Publication number
WO2020073617A1
WO2020073617A1 PCT/CN2019/079097 CN2019079097W WO2020073617A1 WO 2020073617 A1 WO2020073617 A1 WO 2020073617A1 CN 2019079097 W CN2019079097 W CN 2019079097W WO 2020073617 A1 WO2020073617 A1 WO 2020073617A1
Authority
WO
WIPO (PCT)
Prior art keywords
film transistor
thin film
transistor substrate
layer
manufacturing
Prior art date
Application number
PCT/CN2019/079097
Other languages
English (en)
Chinese (zh)
Inventor
陈书志
陈俊吉
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2020073617A1 publication Critical patent/WO2020073617A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed

Definitions

  • the present invention relates to the field of display technology, and in particular, to a method for manufacturing a thin film transistor substrate and a thin film transistor substrate.
  • the liquid crystal display panel is composed of a thin film transistor array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
  • multiple processes such as four Process
  • the more processes required the higher the production cost of the TFT array substrate, and the increased process time and complexity.
  • the existing thin film transistor substrate manufacturing method requires more manufacturing processes, which results in a higher production cost of the thin film transistor substrate.
  • a method for manufacturing a thin film transistor substrate including:
  • the second metal layer is made of transparent conductive material.
  • the manufacturing method of the thin film transistor substrate further includes:
  • the passivation layer covers the pixel electrode, and the manufacturing method of the thin film transistor substrate further includes:
  • the thickness of the second metal layer is greater than or equal to half the thickness of the passivation layer.
  • the transparent conductive material is indium tin oxide, indium zinc oxide or indium tin zinc oxide.
  • a method for manufacturing a thin film transistor substrate including:
  • the second metal layer is made of transparent conductive material.
  • the manufacturing method of the thin film transistor substrate further includes:
  • the passivation layer covers the pixel electrode, and the manufacturing method of the thin film transistor substrate further includes:
  • the thickness of the second metal layer is greater than or equal to half the thickness of the passivation layer.
  • the transparent conductive material is indium tin oxide, indium zinc oxide or indium tin zinc oxide.
  • the invention also provides a method for manufacturing a thin film transistor substrate, including:
  • a grid provided on the substrate
  • a gate insulating layer provided on the substrate and covering the gate
  • a second metal layer disposed on the gate insulating layer, the second metal layer includes a source electrode, a drain electrode, and a pixel electrode;
  • the source electrode, the drain electrode and the pixel electrode are all made of transparent conductive material.
  • the thin film transistor substrate further includes a passivation layer disposed on the gate insulating layer and covering the source electrode and the drain electrode.
  • the passivation layer is provided with a through hole exposing the pixel electrode.
  • the thickness of the second metal layer is greater than or equal to half the thickness of the passivation layer.
  • the transparent conductive material is indium tin oxide, indium zinc oxide or indium tin zinc oxide.
  • the second metal layer is formed of a transparent conductive metal, so that the drain electrode can be directly extended as a pixel electrode, and the source electrode, the drain electrode, and the pixel electrode are formed by the same etching process, thereby reducing the process steps, reducing production costs, and process time And complexity.
  • FIG. 1 is a schematic diagram of a manufacturing process of a thin film transistor substrate in a specific embodiment of the present invention
  • FIG. 2 is a schematic diagram of forming a gate and a gate insulating layer in a specific embodiment of the present invention
  • FIG. 3 is a schematic diagram of a semiconductor layer in a specific embodiment of the present invention.
  • FIG. 4 is a schematic diagram of forming a second metal layer in a specific embodiment of the present invention.
  • FIG. 5 is a schematic diagram of forming a source electrode, a drain electrode and a pixel electrode in a specific embodiment of the present invention
  • FIG. 6 is a schematic diagram of a passivation layer in a specific embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a thin film transistor substrate in a specific embodiment of the present invention.
  • the present invention is directed to the existing manufacturing method of the thin film transistor substrate, which requires many manufacturing processes, resulting in a technical problem of high production cost of the thin film transistor substrate.
  • a method for manufacturing a thin film transistor substrate as shown in FIG. 1, the method for manufacturing a thin film transistor substrate includes:
  • the second metal layer is made of transparent conductive material.
  • the second metal layer is formed of a transparent conductive metal, so that the drain electrode can be directly extended as a pixel electrode, and the source electrode, the drain electrode, and the pixel electrode are formed by the same etching process, thereby reducing the process steps, reducing production costs, process time and the complexity.
  • the transparent conductive material is indium tin oxide (ITO), indium zinc oxide (IZO) or indium tin zinc oxide (ITZO).
  • the first metal layer is formed on the substrate 10 by a sputtering method; it should be noted that in actual implementation, the first metal layer may also be formed by chemical vapor deposition or other physical deposition methods.
  • the process of patterning the first metal layer to form the gate electrode 20 it is preferable to use a mixed solution of nitric acid, phosphoric acid and acetic acid to wet etch the first metal layer; it needs to be understood that In specific implementation, other methods may also be used to perform wet etching on the first metal layer, which is not listed here one by one.
  • the semiconductor layer 40 is patterned.
  • the material of the semiconductor layer 40 is preferably polysilicon.
  • the semiconductor layer 40 may first deposit an amorphous silicon layer, and then, perform a rapid thermal annealing step on the amorphous silicon layer to make the The amorphous silicon layer is recrystallized into a polysilicon layer.
  • a second metal layer 50 is formed on the semiconductor layer 40 and the gate insulating layer 30, and the second metal layer 50 is made of a transparent conductive material.
  • the second metal layer 50 is preferably deposited by sputtering.
  • the second metal layer 50 may be formed in other ways according to process conditions and production costs.
  • the second metal layer 50 is etched to form the source electrode 51, the drain electrode 52 and the pixel electrode 53.
  • the manufacturing method of the thin film transistor substrate 10 further includes:
  • the passivation layer 60 plays a role of isolation and protection.
  • the passivation layer 60 covers the pixel electrode 53, and the manufacturing method of the thin film transistor substrate 10 further includes:
  • the thickness of the second metal layer 50 is greater than or equal to half the thickness of the passivation layer 60.
  • the resistance of the second metal layer 50 made of a transparent conductive material is relatively large. By increasing the thickness of the second metal layer 50, the resistance is reduced, and at the same time, the passivation layer 60 prevents the pixel electrode 53 has an impact.
  • the present invention also provides a thin film transistor substrate 10.
  • the thin film transistor substrate 10 includes a substrate 10, a gate electrode 20 provided on the substrate 10, and an arrangement A gate insulating layer 30 on the substrate 10 and covering the gate 20, a semiconductor layer 40 provided on the gate insulating layer 30, and a second metal layer provided on the gate insulating layer 30 50.
  • the second metal layer 50 includes a source electrode 51, a drain electrode 52, and a pixel electrode 53.
  • the source electrode 51, the drain electrode 52, and the pixel electrode 53 are all made of a transparent conductive material.
  • the second metal layer 50 is formed of a transparent conductive metal, so that the electrode of the drain 52 can be directly extended as the pixel electrode 53, and the source 51, the drain 52, and the pixel electrode 53 are formed by the same etching process, thereby reducing the manufacturing process and reducing Production cost, process time and complexity.
  • the transparent conductive material is indium tin oxide, indium zinc oxide, or indium tin zinc oxide.
  • the thin film transistor substrate 10 further includes a passivation layer 60 disposed on the gate insulating layer 30 and covering the source electrode 51 and the drain electrode 52.
  • the passivation layer 60 is provided with a through hole 70 exposing the pixel electrode 53.
  • the thickness of the second metal layer 50 is greater than or equal to half the thickness of the passivation layer 60.
  • the second metal layer 50 is formed of a transparent conductive metal, so that the drain 52 electrode can be directly extended as the pixel electrode 53, and the source 51, the drain 52 and the pixel electrode 53 are subjected to the same etching process Formed to reduce process steps, reduce production costs, process time and complexity.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un substrat de transistor à couches minces, le procédé consistant : à former une première couche métallique sur un substrat ; à graver la première couche métallique pour former une électrode de grille ; à former, sur le substrat, une couche d'isolation de grille recouvrant l'électrode de grille ; à former une couche semi-conductrice sur la couche d'isolation de grille ; à former une seconde couche métallique sur la couche semi-conductrice et la couche d'isolation de grille ; et à graver la seconde couche métallique pour former une électrode de source, une électrode de drain et une électrode de pixel, la seconde couche métallique étant constituée d'un matériau conducteur transparent.
PCT/CN2019/079097 2018-10-08 2019-03-21 Procédé de fabrication de substrat de transistor à couches minces, et substrat de transistor à couches minces WO2020073617A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811167707.6A CN109545750B (zh) 2018-10-08 2018-10-08 薄膜晶体管基板的制作方法及其薄膜晶体管基板
CN201811167707.6 2018-10-08

Publications (1)

Publication Number Publication Date
WO2020073617A1 true WO2020073617A1 (fr) 2020-04-16

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PCT/CN2019/079097 WO2020073617A1 (fr) 2018-10-08 2019-03-21 Procédé de fabrication de substrat de transistor à couches minces, et substrat de transistor à couches minces

Country Status (2)

Country Link
CN (1) CN109545750B (fr)
WO (1) WO2020073617A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112289834A (zh) * 2020-10-22 2021-01-29 深圳市华星光电半导体显示技术有限公司 显示面板及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101097388A (zh) * 2006-06-30 2008-01-02 Lg.菲利浦Lcd株式会社 液晶显示器件的阵列基板及其制造方法
US20110299005A1 (en) * 2010-06-02 2011-12-08 Mitsubishi Electric Corporation Active matrix substrate and liquid crystal device
CN102651343A (zh) * 2012-03-16 2012-08-29 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板及显示装置
CN102655155A (zh) * 2012-02-27 2012-09-05 京东方科技集团股份有限公司 阵列基板及其制造方法和显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101097388A (zh) * 2006-06-30 2008-01-02 Lg.菲利浦Lcd株式会社 液晶显示器件的阵列基板及其制造方法
US20110299005A1 (en) * 2010-06-02 2011-12-08 Mitsubishi Electric Corporation Active matrix substrate and liquid crystal device
CN102655155A (zh) * 2012-02-27 2012-09-05 京东方科技集团股份有限公司 阵列基板及其制造方法和显示装置
CN102651343A (zh) * 2012-03-16 2012-08-29 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板及显示装置

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Publication number Publication date
CN109545750A (zh) 2019-03-29
CN109545750B (zh) 2020-03-27

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