CN102165569B - The manufacture method of field-effect transistor - Google Patents
The manufacture method of field-effect transistor Download PDFInfo
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- CN102165569B CN102165569B CN200980137848.6A CN200980137848A CN102165569B CN 102165569 B CN102165569 B CN 102165569B CN 200980137848 A CN200980137848 A CN 200980137848A CN 102165569 B CN102165569 B CN 102165569B
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 230000005669 field effect Effects 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000137 annealing Methods 0.000 claims abstract description 39
- 238000004544 sputter deposition Methods 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 24
- 229910007541 Zn O Inorganic materials 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 19
- 239000001301 oxygen Substances 0.000 claims description 18
- 229910052760 oxygen Inorganic materials 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000005546 reactive sputtering Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 124
- 239000010409 thin film Substances 0.000 abstract description 19
- 230000008569 process Effects 0.000 abstract description 14
- 230000000694 effects Effects 0.000 abstract description 11
- 230000007547 defect Effects 0.000 abstract description 7
- 239000013078 crystal Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 100
- 230000004888 barrier function Effects 0.000 description 19
- 230000007797 corrosion Effects 0.000 description 19
- 238000005260 corrosion Methods 0.000 description 19
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 238000012545 processing Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000033228 biological regulation Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000011148 porous material Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005477 sputtering target Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005266 casting Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000002353 field-effect transistor method Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000035899 viability Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
Abstract
The present invention provides the manufacture method of a kind of field-effect transistor, and it also can improve transistor characteristic without carrying out the high temperature anneal.Sputtering method is used to form the In Ga Zn O thin film constituting active layer with the film-forming temperature of more than 100 DEG C.Make annealing treatment in an atmosphere by the temperature of 300 DEG C again.The purpose implementing annealing is to improve the transistor characteristic of the active layer just formed.Compared with the most heated and In Ga Zn O thin film that formed, heated substrate is while the internal strain of the In Ga Zn O thin film using sputtering method and being formed or defect are less.Therefore, compared with the most heated and In Ga Zn O thin film that formed, using the heated and identical material film that formed as improving annealing effect during active layer.Thus the present invention can form the active layer with excellent crystal pipe characteristic by process annealing process.
Description
Technical field
The present invention relates to the manufacture method of the field-effect transistor of a kind of active layer, this activity
Layer is formed by InGaZnO based semiconductor oxide.
Background technology
In recent years, people are widely used AMLCD.This active matrix liquid liquid crystal
Each pixel of display has the field effect thin film transistor (TFT) (TFT) as switch element.
People are known to the thin film transistor (TFT) of following kind, i.e. active layer is made up of polysilicon
The amorphous silicon film transistor that polycrystalline SiTFT and active layer are made up of non-crystalline silicon.
Compared with polycrystalline SiTFT, the active layer of amorphous silicon film transistor is prone to system
Make and can on bigger substrate the advantage of homogeneous film formation.
Owing to transparent amorphous oxide thin film is compared with non-crystalline silicon, its carrier (electronics, hole)
Mobile degree higher, as active layer material, it is developed by people.Such as,
In patent documentation 1, recording a kind of field-effect transistor, its active layer employs of the same clanization
Compound InMO3(ZnO)m(M=In, Fe, Ga or Al, m is more than 1 less than 50
Integer).It addition, in patent documentation 2, record one and be formed with In-Ga-Zn-O system
The manufacture method of the field-effect transistor of active layer, to by having InGaO3(ZnO)4Composition
The target that constitutes of polycrystalline sintered body carry out sputtering processing and to form this In-Ga-Zn-O system active
Layer.
[patent documentation 1] Japanese invention Patent Publication No 2004-103957 (the
[0010] section)
[patent documentation 2] Japanese invention Patent Publication No 2006-165527 (the
[0103]～[0119] section)
Do not have when just being formed owing to having the active layer of In-Ga-Zn-O set member
There is the transistor characteristic (electric conduction properties of flow, cut-off current characteristic, current on/off ratio etc.) of practicality,
So to make annealing treatment at a proper temperature after forming active layer.Annealing temperature is the highest
More can obtain preferable transistor characteristic.
But the upper limit of annealing temperature is limited to the effect film outside used base material or active layer
The heat resisting temperature of (electrode film, dielectric film).Accordingly, it is considered to the thermostability of these structure sheafs,
It sometimes appear that problems with, i.e. required crystal cannot be obtained because annealing grade is insufficient
Pipe characteristic.
Summary of the invention
In view of the foregoing, it is an object of the invention to provide the manufacture of a kind of field-effect transistor
Method, it also can improve transistor characteristic without carrying out the high temperature anneal.
To achieve these goals, field-effect transistor described in one embodiment of the present invention
Manufacture method includes that heated substrate is while using sputtering method to form active layer on the substrate on one side
Operation, wherein, active layer has In-Ga-Zn-O set member.To the described work formed
Property layer makes annealing treatment.
Accompanying drawing explanation
Fig. 1 is the manufacture method of the field-effect transistor representing explanation described in embodiment of the present invention
In the profile of main portions of each operation.
Fig. 2 is the manufacture method of the field-effect transistor representing explanation described in embodiment of the present invention
In the profile of main portions of each operation.
Fig. 3 is the manufacture method of the field-effect transistor representing explanation described in embodiment of the present invention
In the profile of main portions of each operation.
Fig. 4 is the manufacture method of the field-effect transistor representing explanation described in embodiment of the present invention
In the profile of main portions of each operation.
Fig. 5 is the manufacture method of the field-effect transistor representing explanation described in embodiment of the present invention
In the profile of main portions of each operation..
Fig. 6 is the electric conduction properties of flow of the sample for evaluation representing that embodiment of the present invention is to be illustrated
An experimental result with cut-off current characteristic.
Fig. 7 is the simulated section figure of the sample for evaluation representing that embodiment of the present invention is to be illustrated.
Fig. 8 be the sample for evaluation representing that embodiment of the present invention is to be illustrated annealing conditions and
One experimental result of the relation between switch current ratio.
Detailed description of the invention
The manufacture method of the field-effect transistor described in one embodiment of the present invention includes on one side
Heated substrate is while using sputtering method to form the operation of active layer, wherein, activity on the substrate
Layer has In-Ga-Zn-O set member.The described active layer formed is made annealing treatment.
The purpose implementing annealing is to improve the transistor characteristic of the active layer just formed.
Compared with the most heated and In-Ga-Zn-O thin film that formed, heated substrate is while using
Sputtering method and the internal strain of In-Ga-Zn-O thin film or the defect that are formed are less.Therefore, with not
In-Ga-Zn-O thin film that is heated and that formed is compared, by identical material that is heated and that formed
Thin film is as improving annealing effect during active layer.Thus the present invention can be processed by process annealing
And form the active layer of the transistor characteristic with excellence.
More typical base material is glass substrate.The size of this base material is not particularly limited.
The film-forming temperature of above-mentioned active layer can be more than 100 DEG C.
Therefore, compared with the most heated and active layer that formed, the present invention can reduce imparting regulation
Annealing temperature required during transistor characteristic.It addition, film-forming temperature is not limited to 100 DEG C,
Suitably can change according to membrance casting condition.As the heater of heated substrate, heating can be used
Pipe or heating lamp.
The annealing temperature of above-mentioned active layer can also be more than 300 DEG C.The annealing of above-mentioned active layer
Processing pressure can be normal atmosphere, it is also possible to less than normal atmosphere.Processing environment is permissible
It is in atmosphere, it is also possible in oxygen atmosphere.
The experimental result done according to the present inventor, is formed with inciting somebody to action the most heated
The result obtained when making annealing treatment in 400 DEG C of conditions and air of active layer compare,
Active layer that is heated and that formed can obtain when making annealing treatment in 300 DEG C of conditions and air
Identical switch current ratio (conducting electric current/cut-off current).It follows that with the most heated and
The active layer formed is compared, and the active layer of identical material that is heated and that formed passes through process annealing
Process can form the active layer of the transistor characteristic with excellence.
In the operation forming above-mentioned active layer, it is possible to using can be with oxidizing gas (such as O2、
O3、H2Deng) occur the sputtering method of chemical reaction to form above-mentioned active layer.
Simple In-Ga-Zn-O target can be used for forming the sputtering target of In-Ga-Zn-O thin film,
It is used as In2O3Target, Ga2O3Multiple target such as target, ZnO target.Oxygen atmosphere is carried out
Spatter film forming processing, to import oxygen pneumatic (flow) be controlled time, can be easily
Control the oxygen concentration in thin film.
Above-mentioned base material includes grid, it is possible to was formed before forming above-mentioned active layer and is used for covering institute
State the gate insulating film of grid.
Thus can be made into bottom gate type field-effect transistor.Grid can also be formed on base material
Electrode film, it would however also be possible to employ using base material itself as the structure of grid.
Can form the protecting film covering above-mentioned active layer, and formed contact this active layer source electrode and
Drain electrode.Sputtering method can be used to form protecting film.
Below according to accompanying drawing, embodiments of the present invention are described.
[the first embodiment]
Fig. 1～Fig. 5 is the field-effect transistor representing explanation described in first embodiment of the invention
The profile of the main portions of each operation of manufacture method.In the present embodiment, explanation has
The manufacture method of the field-effect transistor of so-called bottom-gate-type transistor structure.
As shown in (A) in Fig. 1, a first surface at base material 10 forms gate electrode film 11F.
More typical base material 10 is glass substrate.More typical gate electrode film 11F by molybdenum,
The metal single layer film of chromium, aluminum etc. or metallized multilayer film are constituted, and it is formed for example with sputtering method.
Being not particularly limited the thickness of gate electrode film 11F, such as it is 300nm.
Next, as shown in (D) in (B)～Fig. 1 in Fig. 1, gate electrode film 11F is processed into
The pattern with regulation shape is formed with mask 12 against corrosion.This operation has photoresist film
12F formation process ((B) in Fig. 1), exposure process ((C) in Fig. 1), development work
Sequence ((D) in Fig. 1).
It is allowed to after being coated on gate electrode film 11F by liquid photosensitive material be dried and form photoresist
Film 12F.It is used as dry type film resist as photoresist film 12F.Through mask 13
Can develop after the photoresist film 12F formed is exposed.Therefore, can be at grid
Mask 12 against corrosion is formed on film 11F.
Then as shown in (E) in Fig. 1, using mask 12 against corrosion as mask to gate electrode film 11F
It is etched processing.Therefore, grid 11 can be formed on the surface of base material 10.
The engraving method of gate electrode film 11F is not particularly limited, wet etching can be used, also
Dry etching method can be used.Mask 12 against corrosion is removed after etching and processing.Remove mask 12 against corrosion
Method be suitable for the ashing of oxygen plasma and process, but present embodiment is not limited thereto, also
The method removed with medicinal liquid can be used.
It follows that as shown in (A) in Fig. 2, formed can cover on a surface of base material 10
The gate insulating film 14 of grid 11.
More typical gate insulating film 14 is by silicon oxide film (SiO2), silicon nitride film (SiNx)
Constituting Deng oxide-film or nitride film, its such as CVD or employing sputtering method are formed.To grid
The thickness of film 11F is not particularly limited, and such as it is 200～500nm.
Next, as shown in (B) in Fig. 2, gate insulating film 14 sequentially forms and has
Thin film (hereinafter referred to as " IGZO the film ") 15F of In-Ga-Zn-O set member and barrier layer
Form film 16F.Use sputtering method to form IGZO film 15F and barrier layer forms film 16F.
IGZO film 15F can be formed continuously and barrier layer forms film 16F.At this time it is also possible to same
Arrange in sputtering cavity and be used for forming the sputtering target of IGZO film 15F and for forming barrier layer
Form the sputtering target of film 16F.The target used by switching, can be individually formed IGZO film 15F
Or barrier layer forms film 16F.
IGZO film 15F is formed when base material 10 being heated to set point of temperature.Base material 10
Heating-up temperature such as more than 100 DEG C.In the present embodiment, employing can produce chemistry
The sputtering method of reaction forms active layer 15 (IGZO film 15F), wherein, by oxygen ring
Target is sputtered by border and the reactant reacted with oxygen is deposited on base material 10.
Discharge type can be any one of DC electric discharge, AC electric discharge, RF electric discharge.It addition,
May be used without arranging the magnetron discharge method of permanent magnet in the rear side of target.
IGZO film 15F and barrier layer are formed the respective thickness of film 16F be not particularly limited,
The thickness of such as IGZO film 15F is 50～200nm, and barrier layer forms the thickness of film 16F and is
30～300nm.
The active layer (current carrying layer) 15 of transistor it is made up of IGZO film 15F.In aftermentioned composition
The metal film pattern formation process of source electrode and drain electrode, and use processing method to remove IGZO
In the operation of the unwanted part of film 15F, barrier layer forms film 16F and plays protection IGZO
The etch protection layer effect of the trench region of film is to prevent from being etched agent erosion.Barrier layer forms film
16F is such as by SiO2Constitute.
It follows that as shown in (D) in (C) and Fig. 2 in Fig. 2, barrier layer is formed film
16F is processed into be had the pattern of regulation shape and is formed with after mask 27 against corrosion, against corrosion covers through this
Film 27 forms film 16F to barrier layer and is etched processing.Therefore, it can formation and clip grid
Dielectric film 14 and IGZO film 15F and with the barrier layer 16 faced by grid 14.
As shown in (E) in Fig. 2, formed after removing mask 27 against corrosion and can cover IGZO film 15F
Metal film 17F with barrier layer 16.
More typical metal film 17F is by the metal single layer film of molybdenum, chromium, aluminum etc. or metallic multilayer
Film is constituted, and it is formed for example with sputtering method.The thickness of metal film 17F is not particularly limited,
Such as it is 100～500nm.
Then, as shown in (B) in (A) and Fig. 3 in Fig. 3, metal film 17F is carried out pattern
Form processing.
The pattern formation process of metal film 17F has formation process (Fig. 3 of mask 18 against corrosion
In (A)) and the etching work procedure ((B) in Fig. 3) of metal film 17F.Mask 18 against corrosion
There is the mask that the area just above making barrier layer 16 is uncovered with the peripheral region of each transistor
Pattern.Wet etching is used to be etched adding to metal film 17F after forming mask 18 against corrosion
Work.Therefore, metal film 17F is separated into source electrode 17S and drain electrode 17D.It addition, thereafter
Explanation in, the most also by source electrode 17S and drain electrode 17D be generically and collectively referred to as source/drain 17.
In source/drain 17 formation process, barrier layer 16 is played the etching of metal film 17F and is stopped
The effect of layer.Barrier layer 16 is positioned at the source electrode 17S on IGZO film 15F and drain electrode to cover
The mode in the region (hereinafter referred to as " trench region ") between 17D is formed.Therefore, IGZO
The trench region of film 15F is unaffected in the etching work procedure of metal film 17F.
It follows that as shown in (D) in (C) and Fig. 3 in Fig. 3, with mask 18 against corrosion be
Mask is etched processing to IGZO film 15F.
Engraving method is not particularly limited, wet etching can be used, it would however also be possible to employ dry type
Etching method.Through the etching work procedure of this IGZO film 15F, IGZO film 15F i.e. can be with element
Isolated for unit, the active layer 15 being made up of IGZO film 15F can be formed again.
Now, the etching protective film of the IGZO film 15F being positioned at trench region is played on barrier layer 16
Effect.Therefore, the trench region of active layer 15 is in the etching work procedure of IGZO film 15F
Unaffected.
After the pattern of IGZO film 15F forms processing, use the method such as ashing process from source/
Mask 18 ((D) in Fig. 3) against corrosion is removed in drain electrode 17.
Next, as shown in (A) in Fig. 4, formed on the surface of base material 10 and can cover source/drain
Pole 17, barrier layer 16, active layer 15, the protecting film (passivating film) 19 of gate insulating film 14.
The transistor unit that protecting film 19 is used for completely cutting off including active layer 15 connects with the external world
Touch, such that it is able to guarantee electrical characteristic and the material behavior of regulation.More typical protecting film 19
By silicon oxide film (SiO2), silicon nitride film (SiNx) etc. oxide-film or nitride film constitute,
It is for example with CVD or uses sputtering method to be formed.The most special to the thickness of protecting film 19
Limiting, such as it is 200～500nm.
Then, as shown in (D) in (B)～Fig. 4 in Fig. 4, protecting film 19 is formed and source
The intercommunicating pore 19a of/drain electrode 17 connection.This operation has and forms mask against corrosion on protecting film 19
The operation ((B) in Fig. 4) of 20, the peristome 20a from mask 20 against corrosion is exposed
Protecting film 19 is etched the operation ((C) in Fig. 4) of processing, removes mask 20 against corrosion
Operation ((D) in Fig. 4).
Dry etching method is have employed but it also may use wet etching when forming intercommunicating pore 19a.
Although it addition, eliminate its diagram, any desired position being likewise formed with and source electrode 17S
The contact hole connected.
It follows that as shown in (D) in (A)～Fig. 5 in Fig. 5, formed through intercommunicating pore 19a
The nesa coating 21 contacted with source/drain 17.This operation has formation transparent conductive film
The operation ((A) in Fig. 5) of 21F, on transparent conductive film 21F, form mask against corrosion
The operation ((B) in Fig. 5) of 22, to the electrically conducting transparent not covered by mask 22 against corrosion
Thin film 21F is etched the operation ((C) in Fig. 5) of processing, removes mask 20 against corrosion
Operation ((D) in Fig. 5).
More typical transparent conductive film 21F is made up of ito film or IZO film, and it is such as adopted
Formed by sputtering method, CVD.It is etched transparent conductive film 21F adding and uses man-hour
Wet etching, but present embodiment is not limited thereto, it would however also be possible to employ dry etching method.
Afterwards to the transistor unit being formed with nesa coating 21 as shown in (D) in Fig. 5
100 make annealing treatment, and its object is to relax the stress of active layer 15.Therefore, do so
The transistor characteristic required for active layer 15 can be given.
By above each step, i.e. can be made into field-effect transistor.
In the present embodiment, structure is formed when base material 10 being heated to set point of temperature
The IGZO film 15F of Viability layer 15.Compared with the most heated and IGZO film that formed, as
Defect in the above-mentioned heated and internal strain of IGZO film 15F that formed or thin film is less.
Compared with the most heated and active layer that formed, by the IGZO film 15F formed through heating
As transistor characteristic (electric conduction properties of flow, the shutoff that can obtain excellence during active layer 15
Current characteristics, switch current ratio etc.).
The present inventor determines the current characteristics of three below active layer sample respectively and (leads
Energising flow valuve, cut-off current value), described three active layer samples be heating-up temperature be 100 DEG C
Under the conditions of use sputtering method formed active layer (sample 1), heating-up temperature be 200 DEG C of conditions
Active layer (sample 2) that lower employing sputtering method is formed and the most heated and use sputtering method to be formed
Active layer (sample 3).Fig. 6 represents its experimental result.In figure, transverse axis is for forming thin film
Time oxygen pneumatic, the longitudinal axis is current value.It addition, the "●" in figure represents leading of sample 1
Energising flow valuve, "○" represent the cut-off current value of sample 1, and " ◆ " represents leading of sample 2
Energising flow valuve, the cut-off current value of " ◇ " expression sample 2, " ▲ " represent leading of sample 3
Energising flow valuve, the cut-off current value of " △ " expression sample 3.
Sample 1, sample 2, sample 3 membrance casting condition in substrate when simply forming active layer
Temperature is different, and sample 1 is 100 DEG C, sample 2 is 200 DEG C, sample 3 is room temperature.Sputtering
The power of negative electrode is that at the film forming of 0.6kW (DC), active layer, process gases is argon and oxygen
Mixed gas, ar pressure be constant 0.74Pa (flow: 230sccm).It addition,
Output valve according to the thermocouple being arranged on substrate measures substrate temperature.
Fig. 7 is the simulated section figure of the structure representing sample 1～3.Transistor in sample 1～3
Element by the p-type silicon substrate as grid 31, the silicon nitride film as gate insulating film 32,
IGZO film as active layer 33, the aluminum film as source/drain 34S, 34D constitute and
Use laminar structure.Using CVD to form gate insulating film 32, its thickness is 350nm.
Using sputtering method to form active layer 33, its thickness is 50nm.
Above-mentioned this transistor unit has the function of following switch element, i.e. through controlling applying
The electricity of flowing between source electrode 34S and drain electrode 34d is controlled to the size of the voltage of grid 31
The size of stream (electric current Ids between source drain).Being particularly due to its operation principle is according to work
The size of the electric field between gate-to-source changes the groove distribution situation in active layer,
And control the size of electric current between source drain with this, so this transistor unit
It is referred to as field-effect transistor.
Experimental result shown in Fig. 6 is the current characteristics after active layer 33 is just formed, this
Time do not implement annealing.Additionally sample 1, sample 2, each component size of sample 3,
The structure of the circuit evaluating electrical characteristic is the most identical.Turn on current value means grid voltage
(Vgs) higher than the size of electric current (Ids) between source drain during threshold voltage (Vth).
Cut-off current value means grid voltage (Vgs) less than electric current between source drain during threshold voltage
(Ids) size.In general, for transistor characteristic, people require to turn on electric current
Value is big and cut-off current value is little, or requires the bigger of turn on current value/cut-off current value.
As shown in the experimental result in Fig. 6, therefrom can confirm that for sample 1, sample 2,
For sample 3, their turn on current value and cut-off current value are along with the oxygen in film forming environment
The difference of air pressure and change.Especially can confirm that following a kind of trend, i.e. for sample 1～3
In any one for, oxygen pneumatic its turn on current value the lowest and cut-off current value are the biggest.
When comparative sample 1, sample 2 and sample 3, and there is activity that is the most heated and that formed
The sample 3 of layer is compared, and has the heated and sample 1 of active layer that formed and sample 2
Turn on current value is bigger.When this situation can be estimated as forming active layer by heating, can make
Strain and defect in active layer reduce, and so can improve carrier (electronics, hole)
Mobile degree.
It addition, can be confirmed it significantly from sample 1 show following trend, i.e. it turns off
Current value declines also with the increase of oxygen pneumatic, especially when oxygen pneumatic is 0.28Pa its
Cut-off current value is down to 1.0 × 10-14(A).This situation can be estimated as the insulation of active layer
Performance strengthens along with the increase of oxygen pneumatic, so can cause the decline of cut-off current value.
Further, can confirm that when comparative sample 1 and sample 2, when oxygen pneumatic is 0.02Pa,
The turn on current value of sample 1 and cut-off current value all big than sample 2, but when oxygen pneumatic is
When 0.03～0.28Pa, the turn on current value of sample 2 and cut-off current value are the most all than sample 1
Greatly.ON/OFF current value between sample 1 and sample 2 occurs that the reason of difference is film forming
Add the difference of the heating-up temperature in man-hour.(0.02Pa under the conditions of oxygen pneumatic the most in an experiment
Above below 0.28Pa) can confirm that and there is the sample of active layer that is the most heated and that formed
3 compare, and can improve current characteristics and switch current ratio when using sample 1 and sample 2.
As it has been described above, with the most heated and compared with forming the situation of active layer, heated and formed
Turn on current value can be improved when there is the active layer of In-Ga-Zn-O composition.Here with sputtering
Add as a example by the film-forming temperature in man-hour is 100 DEG C and 200 DEG C and be illustrated.But heating-up temperature
Being not limited to upper example, such as they can be less than 100 degree or not enough more than 100 DEG C
200 DEG C, or also may be used more than 200 DEG C.That is, can according to required transistor characteristic suitably
Set heating-up temperature.
During it addition, use under at heating environment sputtering method to form active layer 15, can be behind
Annealing operation in obtain preferable annealing effect.The purpose implementing annealing is to improve just
The transistor characteristic of the active layer formed.With the most heated and compared with forming the situation of active layer,
Owing to heated and that the formed internal strain of active layer 15 or defect are less, thus its for from
The heat that exterior conductive comes has higher sensitivity, and this is to when reducing annealing further
Temperature there is facilitation.
For the sample 1 illustrated by Fig. 6 and Fig. 7, sample 2 and sample 3, Fig. 8 is to represent
The experimental result of the switch current ratio recorded before and after they are made annealing treatment respectively.Evaluate and use
Sample is to have under the conditions of oxygen pneumatic is 0.28Pa the active layer using sputtering method to be formed
Sample.Annealing temperature respectively 200 DEG C, 300 DEG C, 400 DEG C, annealing environment be all
In air, annealing time be 15 minutes."●" in figure represents the switch electricity of sample 1
Flow ratio, " ◆ " represent sample 2 switch current ratio, " ▲ " represent sample 3 switch electricity
Flow ratio.
For have the most heated and for the sample 3 of active layer that formed, 400 DEG C of conditions
Under obtain the switch current ratio more than 7 figure places.In contrast, for having at 100 DEG C and
For using sample 1 and the sample 2 of the active layer of sputtering method formation under the conditions of 200 DEG C, they
The switch current ratio reaching 8 figure places is just obtained under the conditions of 300 DEG C.
From the experimental result shown in Fig. 8 it can be seen that switch more than equal with sample 3 for obtaining
Current ratio, compared with the annealing temperature needed for sample 3, when using sample 1 and sample 2
Annealing temperature can be down to than the former degree of the lowest less than 100 DEG C.Therefore, heated
And the active layer formed is when just being formed, because of strain or the less reason of defect in its thin film,
Its atom can be diffused having higher response from outside thermic load.Therefore,
Even if the thermic load that temperature is relatively low can also be obtained preferable transistor characteristic.
During in particular by sample 1 and sample 2, due to can less than sample 3 temperature conditions under
Also preferable transistor characteristic can be obtained, even if so because of the effect film outside base material or active layer
The thermostability of (electrode film, dielectric film) and make treatment temperature limited, use sample 1 and sample
Also have the advantage that when 2, i.e. by they be easily obtained as the object of the invention preferable
Transistor characteristic.
It addition, when sample 1 and sample 2 being made annealing treatment with the high temperature more than 300 DEG C,
Can further improve switch current ratio.It is same as not accordingly, it is considered to use to element thermostability etc.
Heated and form the annealing conditions of thin film when making annealing treatment, can improve further electrically
Characteristic.Annealing temperature such as can be made to be more than 300 DEG C and less than 400 DEG C.Further, since use
Aluminum there will be the problem of bag (forming trickle projection on surface) when making grid, and will move back
The upper limit of fire temperature can efficiently control the generation of this defect when being set as 350 DEG C.
It is explained above embodiments of the present invention, certainly the invention is not limited in above-mentioned enforcement
Mode, without departing from the scope of the subject in the invention, can carry out various modification to it.
Such as, in the above-described embodiment as a example by the manufacture method of bottom gate type field-effect transistor
Being illustrated, its grid is formed at the lower floor side of active layer.But the invention is not limited in
This, present invention can be suitably applied in the manufacture method of top gate type field-effect transistor, and its grid is formed
Side, upper strata at active layer.
It addition, in the above-described embodiment, the film forming temperature of active layer 15 (IGZO film 15F)
Degree is more than 100 DEG C, and forming the annealing temperature after active layer 15 is 300 DEG C.But the present invention
It is not limited thereto, can suitably change over film temperature according to the transistor characteristic of required element
And annealing temperature.
[description of reference numerals]
10, base material；11, grid；14, gate insulating film；15, active layer；16, resistance
Barrier；17 (17S, 17D), source/drain；19, protecting film
Claims (4)
1. the manufacture method of a field-effect transistor, it is characterised in that
Use the temperature adding heat pipe or heating lamp heated substrate to more than 100 DEG C less than 200 DEG C,
When being heated to more than 100 DEG C less than 200 DEG C, using oxygen pneumatic condition is 0.02Pa
The reactive sputtering of above below 0.28Pa forms active layer on the substrate, and wherein, this is lived
Property layer has In-Ga-Zn-O set member,
Heat the described active layer the formed temperature to more than 300 DEG C less than 400 DEG C to institute
State active layer to make annealing treatment, make the stress of described active layer be relaxed, and make field effect
The conducting electric current of transistor reaches the level of 1.E+08 with the ratio of cut-off current.
2. the manufacture method of field-effect transistor as claimed in claim 1, it is characterised in that
The operation forming above-mentioned active layer includes: uses and with oxidizing gas, chemistry can occur
The sputtering method of reaction forms described active layer.
3. the manufacture method of field-effect transistor as claimed in claim 1, it is characterised in that
Described base material includes grid,
The gate insulating film covering described grid was formed before forming described active layer.
4. the manufacture method of field-effect transistor as claimed in claim 3, it is characterised in that
Form the protecting film covering described active layer,
Form source electrode and the drain electrode contacting this active layer.
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