CN105575803B - The manufacturing method of field-effect transistor - Google Patents
The manufacturing method of field-effect transistor Download PDFInfo
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- CN105575803B CN105575803B CN201610010064.9A CN201610010064A CN105575803B CN 105575803 B CN105575803 B CN 105575803B CN 201610010064 A CN201610010064 A CN 201610010064A CN 105575803 B CN105575803 B CN 105575803B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 49
- 238000000137 annealing Methods 0.000 claims abstract description 43
- 239000000463 material Substances 0.000 claims abstract description 32
- 230000008569 process Effects 0.000 claims abstract description 31
- 238000004544 sputter deposition Methods 0.000 claims abstract description 23
- 229910007541 Zn O Inorganic materials 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims description 22
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 21
- 239000001301 oxygen Substances 0.000 claims description 21
- 229910052760 oxygen Inorganic materials 0.000 claims description 21
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 1
- 238000012545 processing Methods 0.000 abstract description 19
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- 230000000694 effects Effects 0.000 abstract description 7
- 239000013078 crystal Substances 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 140
- 239000010410 layer Substances 0.000 description 106
- 230000004888 barrier function Effects 0.000 description 19
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- 238000005477 sputtering target Methods 0.000 description 3
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- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
Abstract
The present invention provides a kind of manufacturing method of field-effect transistor, and transistor characteristic can be also improved without carrying out the high temperature anneal.The In-Ga-Zn-O films for constituting active layer are formed with 100 DEG C or more of film-forming temperature using sputtering method.It is made annealing treatment in an atmosphere with 300 DEG C of temperature again.The purpose for implementing annealing is to improve the transistor characteristic of the active layer just formed.With it is not heated and compared with the In-Ga-Zn-O films that are formed, the internal strains of In-Ga-Zn-O films or defect that sputtering method is used while heated substrate and is formed are less.Therefore, with it is not heated and compared with the In-Ga-Zn-O films that are formed, the identical material film formed heated when active layer as can be improved annealing effect.Thus the present invention can form the active layer with excellent crystal pipe characteristic by process annealing processing.
Description
Technical field
The present invention relates to a kind of manufacturing methods of the field-effect transistor of active layer, and the active layer is by InGaZnO systems
Conductor oxidate is formed.
Background technology
In recent years, active matrix liquid crystal display is widely used in people.Each picture of the active matrix liquid liquid crystal display
Element has the field-effect thin film transistor (TFT) (TFT) as switch element.
There is known the thin film transistor (TFT)s of following type by people, that is, the polysilicon membrane crystal that active layer is made of polysilicon
The amorphous silicon film transistor that pipe and active layer are made of non-crystalline silicon.
Compared with polycrystalline SiTFT, the active layer of amorphous silicon film transistor is easily fabricated and can be larger
Substrate on homogeneous film formation the advantages of.
Since transparent amorphous oxide film is compared with non-crystalline silicon, the mobile degree of carrier (electronics, hole) is higher,
As active layer material, people develop it.For example, in patent document 1, recording a kind of field effect transistor
Pipe, active layer have used congeners InMO3(ZnO)m(M=In, Fe, Ga or Al, m are 1 or more the integer less than 50).
In addition, in patent document 2, recording a kind of manufacturer for the field-effect transistor being formed with In-Ga-Zn-O systems active layer
Method, to by with InGaO3(ZnO)4The target that the polycrystalline sintered body of ingredient is constituted carries out sputtering processing and forms the In-Ga-Zn-
O systems active layer.
【Patent document 1】Japanese invention patent Publication special open 2004-103957 (the【0010】Section)
【Patent document 2】Japanese invention patent Publication special open 2006-165527 (the【0103】~【0119】Section)
Since the active layer with In-Ga-Zn-O set members does not have practical transistor in the state of just being formed
Characteristic (conducting electric current characteristic, cut-off current characteristic, ON/OFF electric current ratio etc.), so will be in temperature appropriate after forming active layer
It is made annealing treatment under degree.The more higher more available preferable transistor characteristic of annealing temperature.
But the upper limit of annealing temperature is limited to the effect film (electrode film, insulating film) except used base material or active layer
Heat resisting temperature.Accordingly, it is considered to the heat resistance of these structure sheafs, it sometimes appear that problems with, that is, because annealing grade is not filled
Divide and required transistor characteristic can not be obtained.
Invention content
In view of the foregoing, the purpose of the present invention is to provide a kind of manufacturing method of field-effect transistor, without into
Row the high temperature anneal can also improve transistor characteristic.
To achieve the goals above, the manufacturing method of the field-effect transistor described in one embodiment of the present invention is：?
Base material has been heated under 100 DEG C or more 200 DEG C of state of temperatures below, has used oxygen pneumatic condition for 0.02Pa or more
0.28Pa sputtering methods below form active layer on the substrate, wherein and the active layer has In-Ga-Zn-O set members, with
300 DEG C or more the heating temperature conditions less than 400 DEG C make annealing treatment to being formed by the active layer.
Due to being (100 DEG C or more) after heating base material, above-mentioned active layer is formed on base material by reactive sputtering, because
And as latter embodiments are confirmed, with it is not heated into the film of film compared with, even if subsequent annealing temperature compared with
Low (less than 400 DEG C), can also obtain higher transistor characteristic.
In the present invention, reached by the ratio of the annealing, the conducting electric current and cut-off current that make field-effect transistor
To the level of 1.E+08.That is, due to being (100 DEG C or more) after heating base material, formed on base material by reactive sputtering
State active layer, thus, even if annealing temperature is relatively low, it can also make the conducting electric current and cut-off current of field-effect transistor
Ratio reaches the level of 1.E+08.
In the present invention, before forming the active layer by film process, heating tube or heating lamp can be used to heat institute
It states base material and reaches above-mentioned state of temperature.
Description of the drawings
Fig. 1 is the main of each process in the manufacturing method for indicate to illustrate the field-effect transistor described in embodiment of the present invention
The sectional view at position.
Fig. 2 is the main of each process in the manufacturing method for indicate to illustrate the field-effect transistor described in embodiment of the present invention
The sectional view at position.
Fig. 3 is the main of each process in the manufacturing method for indicate to illustrate the field-effect transistor described in embodiment of the present invention
The sectional view at position.
Fig. 4 is the main of each process in the manufacturing method for indicate to illustrate the field-effect transistor described in embodiment of the present invention
The sectional view at position.
Fig. 5 is the main of each process in the manufacturing method for indicate to illustrate the field-effect transistor described in embodiment of the present invention
The sectional view at position.
Fig. 6 is the conducting electric current characteristic and cut-off current characteristic for the sample for evaluation for indicating that embodiment of the present invention to be illustrated
An experimental result.
Fig. 7 is the simulated section figure for the sample for evaluation for indicating that embodiment of the present invention to be illustrated.
Fig. 8 is between the annealing conditions and switching current ratio of the sample for evaluation for indicating that embodiment of the present invention to be illustrated
Relationship an experimental result.
Specific implementation mode
The manufacturing method of field-effect transistor described in one embodiment of the present invention includes having carried out heating simultaneously to base material
And the process for using sputtering method to form active layer on the substrate, wherein active layer has In-Ga-Zn-O set members.To institute's shape
At the active layer made annealing treatment.
The purpose for implementing annealing is to improve the transistor characteristic of the active layer just formed.With not heated and shape
At In-Ga-Zn-O films compare, heated substrate and the internal strain of In-Ga-Zn-O films that is formed using sputtering method or
Defect is less.Therefore, compared with not heated and formation In-Ga-Zn-O films, the identical material formed heated is thin
Annealing effect can be improved when film is as active layer.Thus the present invention can be formed by process annealing is handled has excellent crystal
The active layer of pipe characteristic.
More typical base material is glass substrate.The size of the base material is not particularly limited.
The film-forming temperature of above-mentioned active layer can be at 100 DEG C or more.
Therefore, compared with not heated and formation active layer, the present invention, which can reduce, assigns regulation transistor characteristic when institute
The annealing temperature needed.In addition, film-forming temperature is not limited to 100 DEG C, can suitably be changed according to membrance casting condition.As heated substrate
Heating tube or heating lamp can be used in heating device.
The annealing temperature of above-mentioned active layer can also be at 300 DEG C or more.The annealing pressure of above-mentioned active layer can be
Standard atmospheric pressure may also be below standard atmospheric pressure.Processing environment can be in air, can also be in oxygen atmosphere.
Experimental result that inventor according to the present invention is done is it is found that with the active layer that is formed not heated 400
Obtained result is compared when being made annealing treatment in DEG C condition and air, and the heated and active layer that is formed is in 300 DEG C of conditions
And it can get identical switching current ratio (conducting electric current/cut-off current) when being made annealing treatment in air.It follows that with not
Active layer that is heated and being formed is compared, and heated and the identical material of formation active layer is handled by process annealing and can be formed
Active layer with excellent transistor characteristic.
In the process for forming above-mentioned active layer, can also be used can be with oxidizing gas (such as O2、O3、H2Deng) change
The sputtering method for learning reaction forms above-mentioned active layer.
Simple In-Ga-Zn-O targets can be used in sputtering target to form In-Ga-Zn-O films, it is possible to use In2O3Target,
Ga 2O3Multiple targets such as target, ZnO target.The spatter film forming processing carried out in oxygen atmosphere, to oxygen pneumatic (flow, the oxygen of importing
Qi leel pressure) when being controlled, it can easily control the oxygen concentration in film.
Above-mentioned base material includes grid, and it is exhausted also the grid for being used for covering the grid can be formed before forming above-mentioned active layer
Velum.
Thus it can be made into bottom gate type field-effect transistor.Grid can also be to form electrode film on base material, can also
Using the structure by base material itself as grid.
The protective film for covering above-mentioned active layer can be formed, and forms the source electrode and drain electrode for contacting the active layer.It can be used and splash
It penetrates method and forms protective film.
Below according to description of the drawings embodiments of the present invention.
【First embodiment】
Fig. 1~Fig. 5 be indicate to illustrate the field-effect transistor described in first embodiment of the invention manufacturing method it is each
The sectional view of the main portions of process.In the present embodiment, illustrate the field-effect with so-called bottom-gate-type transistor structure
The manufacturing method of transistor.
As shown in (A) in Fig. 1, gate electrode film 11F is formed on a surface of base material 10 first.
More typical base material 10 is glass substrate.More typical gate electrode film 11F by molybdenum, chromium, aluminium etc. metal single layer
Film or metallized multilayer film are constituted, and are formed for example, by using sputtering method.The thickness of gate electrode film 11F is not particularly limited, such as its
For 300nm.
Next as shown in (D) in (B)~Fig. 1 in Fig. 1, gate electrode film 11F is processed into the pattern shape with regulation shape
At with mask 12 against corrosion.The process has photoresist film 12F formation process ((B) in Fig. 1), exposure process (in Fig. 1
(C)), developing procedure ((D) in Fig. 1).
It is allowed to dry after liquid photosensitive material is coated on gate electrode film 11F and forms photoresist film 12F.As photic
Dry type film resist can also be used in resist film 12F.After mask 13 is exposed to being formed by photoresist film 12F
It can develop.Therefore, mask 12 against corrosion can be formed on gate electrode film 11F.
Then as shown in (E) in Fig. 1, processing is etched to gate electrode film 11F using mask 12 against corrosion as mask.Therefore,
Grid 11 can be formed on the surface of base material 10.
The engraving method of gate electrode film 11F is not particularly limited, wet etching can be used, dry-etching can also be used
Method.Mask 12 against corrosion is removed after etching and processing.The method for removing mask 12 against corrosion is applicable in the ashing processing of oxygen plasma, but this
Embodiment is not limited thereto, and can also use the method removed with liquid.
Next, as shown in (A) in Fig. 2, the gate insulating film that can cover grid 11 is formed on a surface of base material 10
14。
More typical gate insulating film 14 is by silicon oxide film (SiO2), silicon nitride film (SiNx) etc. oxidation films or nitride film
It constitutes, such as CVD method or use sputtering method are formed.The thickness of gate electrode film 11F is not particularly limited, for example, its for 200~
500nm。
Next it as shown in (B) in Fig. 2, is sequentially formed on gate insulating film 14 with the thin of In-Ga-Zn-O set members
Film (hereinafter referred to as " IGZO films ") 15F and barrier layer form film 16F.IGZO films 15F and barrier layer are formed using sputtering method
Form film 16F.IGZO films 15F can be formed continuously and barrier layer forms film 16F.At this point, can also be set in same sputtering cavity
Set the sputtering target for forming IGZO films 15F and for forming the sputtering target that barrier layer forms film 16F.It is used by switching
Target, IGZO films 15F or barrier layer can be individually formed and form film 16F.
IGZO films 15F is formed in the state that base material 10 is heated to set point of temperature.The heating temperature of base material 10 for example exists
100 DEG C or more.In the present embodiment, active layer 15 (IGZO film 15F) is formed using the sputtering method that can generate chemical reaction,
Wherein, it will be deposited on base material 10 with the reactant that oxygen reacts by being sputtered to target in oxygen atmosphere.It puts
Electric form can be any one of DC electric discharges, AC electric discharges, RF electric discharges.In addition, can also be used target back side setting forever
The magnetron discharge method of magnet.
To IGZO films 15F and barrier layer the respective thickness of film 16F is formed to be not particularly limited, for example, IGZO films 15F thickness
Degree is 50~200nm, and the thickness that barrier layer forms film 16F is 30~300nm.
The active layer (current carrying layer) 15 of transistor is made of IGZO films 15F.In the aftermentioned metal film for constituting source electrode and drain electrode
Pattern formation process, and use in the process of unwanted part of processing method removal IGZO films 15F, barrier layer is formed
Film 16F plays the role of that the etch protection layer of the trench region of IGZO films is protected to corrode to prevent from being etched agent.Barrier layer forms film
16F is for example by SiO2It constitutes.
Next, as shown in (D) in (C) and Fig. 2 in Fig. 2, barrier layer formation film 16F is processed into regulation shape
After pattern forms mask 27 against corrosion, film 16F is formed to barrier layer through the mask 27 against corrosion and is etched processing.It therefore, can be with
Form the barrier layer 16 for clipping gate insulating film 14 and IGZO films 15F and being faced with grid 14.
As shown in (E) in Fig. 2, the metal film that can cover IGZO films 15F and barrier layer 16 is formed after removing mask 27 against corrosion
17F。
More typical metal film 17F is made of the metal single layer film or metallized multilayer film of molybdenum, chromium, aluminium etc., such as is adopted
It is formed with sputtering method.The thickness of metal film 17F is not particularly limited, such as it is 100~500nm.
Then as shown in (B) in (A) and Fig. 3 in Fig. 3, pattern is carried out to metal film 17F and forms processing.
The pattern formation process of metal film 17F has the formation process ((A) in Fig. 3) and metal film 17F of mask 18 against corrosion
Etching work procedure ((B) in Fig. 3).Mask 18 against corrosion has the peripheral region of the area just above and each transistor that make barrier layer 16
The mask pattern of domain opening.It is formed after mask 18 against corrosion and processing is etched to metal film 17F using wet etching.Therefore,
Metal film 17F is separated into source electrode 17S and drain electrode 17D.In addition, in explanation thereafter, sometimes also by source electrode 17S and drain electrode
17D is collectively referred to as source/drain 17.
In 17 formation process of source/drain, the etch stop layer of metal film 17F is played the role of on barrier layer 16.Barrier layer
16 in a manner of covering the region (hereinafter referred to as " trench region ") between the source electrode 17S being located on IGZO films 15F and drain electrode 17D
It is formed.Therefore, the trench region of IGZO films 15F is unaffected in the etching work procedure of metal film 17F.
It is that mask is etched IGZO films 15F with mask 18 against corrosion next, as shown in (D) in (C) and Fig. 3 in Fig. 3
Processing.
Engraving method is not particularly limited, wet etching can be used, dry etching method can also be used.Through the IGZO
The etching work procedure of film 15F, IGZO films 15F can be isolated as unit of element, and can be formed by IGZO film 15F structures
At active layer 15.
At this point, the etching protective film of the IGZO films 15F positioned at trench region is played the role of on barrier layer 16.Therefore, active
The trench region of layer 15 is unaffected in the etching work procedure of IGZO films 15F.
After the pattern of IGZO films 15F forms processing, against corrosion cover is removed from source/drain 17 using the methods of ashing processing
Film 18 ((D) in Fig. 3).
Next as shown in (A) in Fig. 4, source/drain 17, barrier layer 16, activity can be covered by being formed on the surface of base material 10
The protective film (passivating film) 19 of layer 15, gate insulating film 14.
The transistor unit that protective film 19 is used for completely cutting off including active layer 15 is contacted with the external world, so as to ensure to advise
Fixed electrical characteristic and material property.More typical protective film 19 is by silicon oxide film (SiO2), silicon nitride film (SiNx) etc. oxidations
Film or nitride film are constituted, and are formed for example, by using CVD method or using sputtering method.There is no special limit to the thickness of protective film 19
It is fixed, such as it is 200~500nm.
Then as shown in (D) in (B)~Fig. 4 in Fig. 4, the intercommunicating pore being connected to source/drain 17 is formed on protective film 19
19a.The process has forms the process ((B) in Fig. 4) of mask 20 against corrosion, to the opening from mask 20 against corrosion on protective film 19
The protective film 19 that portion 20a exposes is etched the process ((C) in Fig. 4) of processing, the process of removal mask 20 against corrosion (in Fig. 4
(D))。
Dry etching method is used when forming intercommunicating pore 19a, but wet etching can also be used.In addition, though omitting
Its diagram, is likewise formed with the contact hole being connect with source electrode 17S on arbitrary desired position.
Next, as shown in (D) in (A)~Fig. 5 in Fig. 5, formed through intercommunicating pore 19a contacted with source/drain 17 it is transparent
Conductive film 21.The process has process ((A) in Fig. 5), the shape on transparent conductive film 21F for forming transparent conductive film 21F
At the process ((B) in Fig. 5) of mask 22 against corrosion, to not being etched by the transparent conductive film 21F that mask 22 against corrosion covers
The process ((C) in Fig. 5) of processing, the process ((D) in Fig. 5) of removal mask 20 against corrosion.
More typical transparent conductive film 21F is made of ito film or IZO films, for example, by using sputtering method, CVD method shape
At.Wet etching is used when being etched processing to transparent conductive film 21F, but present embodiment is not limited thereto,
Dry etching method can also be used.
The transistor unit 100 that transparent conductive film 21 is formed with as shown in (D) in Fig. 5 is made annealing treatment later,
Its object is to mitigate the stress of active layer 15.Therefore, doing so can assign active layer 15 required transistor characteristic.
Pass through above each step, you can field-effect transistor is made.
In the present embodiment, the IGZO for constituting active layer 15 is formed in the state that base material 10 is heated to set point of temperature
Film 15F.With it is not heated and formed IGZO films compared with, as above-mentioned heated formed IGZO films 15F internal strain or
The defects of film is less.Compared with not heated and formation active layer, by the IGZO film 15F conducts formed by heating
Excellent transistor characteristic (conducting electric current characteristic, cut-off current characteristic, switching current ratio etc.) can be obtained when active layer 15.
The present inventor determines current characteristics (turn on current value, the shutdown of following three active layer samples respectively
Current value), three active layer samples are the active layer (sample formed using sputtering method under the conditions of heating temperature is 100 DEG C
1) active layer (sample 2) that is formed using sputtering method under the conditions of, heating temperature is 200 DEG C and not heated sputtering method shape is used
At active layer (sample 3).Its experimental result is indicated in Fig. 6.Horizontal axis is oxygen pneumatic when forming film in figure, and the longitudinal axis is electricity
Flow valuve.In addition, the "●" in figure indicates that the turn on current value of sample 1, "○" indicate the cut-off current value of sample 1, " ◆ " indicates
The turn on current value of sample 2, " ◇ " indicate that the cut-off current value of sample 2, " ▲ " indicate turn on current value, " △ " table of sample 3
The cut-off current value of sample product 3.
Sample 1, sample 2, sample 3 membrance casting condition in substrate temperature when only forming active layer it is different, sample 1 is
100 DEG C, sample 2 be 200 DEG C, sample 3 be room temperature.The power of sputter cathode is the film process gas of 0.6kW (DC), active layer
It is constant 0.74Pa (flows for the mixed gas of argon gas and oxygen, ar pressure：230sccm).In addition, according to mounted on
The output valve of thermocouple on substrate measures substrate temperature.
Fig. 7 is the simulated section figure for the structure for indicating sample 1~3.Transistor unit in sample 1~3 is by as grid
31 p-type silicon substrate, the silicon nitride film as gate insulating film 32, the IGZO films as active layer 33, as source/drain 34S,
The aluminium film of 34D constitutes and uses laminar structure.Gate insulating film 32, film thickness 350nm are formed using CVD method.Using splashing
It penetrates method and forms active layer 33, film thickness 50nm.
Above-mentioned this transistor unit has the function of following switch element, that is, the voltage of grid 31 is applied to through control
Size control the size of electric current (electric current Ids between source drain) flowed between source electrode 34S and drain electrode 34d.Especially
Since its operation principle is to be distributed feelings according to the size for acting on the electric field between gate-to-source to change the groove in active layer
Condition, and size of electric current between source drain is controlled with this, so this transistor unit is referred to as field effect transistor
Pipe.
Experimental result shown in Fig. 6 is the current characteristics after active layer 33 is just formed, at this time without implementing at annealing
Reason.In addition sample 1, sample 2, each component size of sample 3, the structure for the circuit for evaluating electrical characteristic are all identical.Conducting
Current value means the size of electric current (Ids) between source drain when grid voltage (Vgs) is higher than threshold voltage (Vth).Shutdown electricity
Flow valuve means the size of electric current (Ids) between source drain when grid voltage (Vgs) is less than threshold voltage.In general, as
For transistor characteristic, people require turn on current value big and cut-off current value is small, or require turn on current value/cut-off current
What is be worth is bigger.
As shown in the experimental result in Fig. 6, therefrom confirm for sample 1, sample 2, sample 3, they lead
Energization flow valuve and cut-off current value change with the difference of the oxygen pneumatic in film forming environment.Especially confirm following one kind
Trend, that is, for any one of sample 1~3, its lower turn on current value of oxygen pneumatic and cut-off current value are more
Greatly.
When contrast sample 1, sample 2 and sample 3, compared with the sample 3 of the active layer formed with not heated, have
It is heated and formed active layer sample 1 and sample 2 turn on current value it is larger.Such case can be estimated as passing through heating
And when forming active layer, strain and defect in active layer can be made to reduce, the shifting in carrier (electronics, hole) can be improved in this way
Traverse degree.
In addition, can significantly confirm it from sample 1 shows following trend, that is, its cut-off current value is also with oxygen
The increase of air pressure and decline, especially oxygen pneumatic be 0.28Pa when its cut-off current value be down to 1.0 × 10-14(A).This feelings
The insulation performance that condition can be estimated as active layer enhances with the increase of oxygen pneumatic, can cause under cut-off current value in this way
Drop.
In addition, confirmed when contrast sample 1 and sample 2, when oxygen pneumatic is 0.02Pa, the conducting electric current of sample 1
Value and cut-off current value it is all bigger than sample 2, but when oxygen pneumatic be 0.03~0.28Pa when, the turn on current value of sample 2 and
Cut-off current value is then all bigger than sample 1.There is the reason of difference and is in ON/OFF current value between sample 1 and sample 2
The difference of heating temperature when film forming processing.Under the conditions of oxygen pneumatic at least in an experiment (0.02Pa or more 0.28Pa or less)
It confirms, compared with the sample 3 of the active layer formed with not heated, electric current can be improved when using sample 1 and sample 2
Characteristic and switching current ratio.
As described above, with it is not heated and the case where form active layer compared with, it is heated and being formed has In-Ga-Zn-O
Turn on current value can be improved when the active layer of ingredient.For film-forming temperature when being processed here by sputtering is 100 DEG C and 200 DEG C
It is illustrated.But heating temperature is not limited to example, such as its can less than 100 degree, or more than 100 DEG C without
200 DEG C of foot, or also may be used more than 200 DEG C.That is, heating temperature can suitably be set according to required transistor characteristic.
In addition, when using sputtering method to form active layer 15 under heating environment, obtained in annealing operation that can be behind
Preferable annealing effect.The purpose for implementing annealing is to improve the transistor characteristic of the active layer just formed.With without adding
Heat and the case where forming active layer, is compared, the internal strain of the active layer 15 formed due to heated or defect are less, thus its
There is higher sensibility for the heat to come from exterior conductive, this, which has temperature when further decreasing annealing, promotees
Into effect.
For sample 1, sample 2 and the sample 3 illustrated by Fig. 6 and Fig. 7, Fig. 8 is to indicate to carry out at annealing them respectively
The experimental result of the switching current ratio measured before and after reason.Sample for evaluation is that have to use under the conditions of oxygen pneumatic is 0.28Pa
The sample for the active layer that sputtering method is formed.Annealing temperature is respectively 200 DEG C, 300 DEG C, 400 DEG C, annealing environment be all big
In gas, annealing time be 15 minutes."●" in figure indicates that the switching current ratio of sample 1, " ◆ " indicate the switch electricity of sample 2
Stream ratio, " ▲ " indicate the switching current ratio of sample 3.
For the sample 3 of the active layer formed with not heated, obtained more than 7 under the conditions of 400 DEG C
Several switching current ratios.In contrast, for the active layer for using sputtering method formation under the conditions of 100 DEG C and 200 DEG C
For sample 1 and sample 2, they just obtain the switching current ratio for reaching 8 digits under the conditions of 300 DEG C.
Can be seen that from experimental result shown in Fig. 8 for obtain with the same above switching current ratio of sample 3, with 3 institute of sample
The annealing temperature needed is compared, use when sample 1 and sample 2 can will annealing temperature be down to 100 DEG C also lower than the former with
Under degree.Therefore, heated and formation active layer is when just forming, because of the edge strained in its film or defect is less
Therefore atom can be diffused to having higher response from external thermic load.Therefore, even if it is lower to temperature
Thermic load can also obtain preferable transistor characteristic.
When in particular by sample 1 and sample 2, preferable crystalline substance can be also obtained due to that can be less than under the temperature condition of sample 3
Body pipe characteristic, so even if the heat resistance of effect film (electrode film, insulating film) except base material or active layer due to make processing temperature
Degree is limited, is also had the advantage that when using sample 1 and sample 2, that is, be easily obtained by them be used as the object of the invention compared with
Good transistor characteristic.
In addition, when being made annealing treatment to sample 1 and sample 2 with the high temperature more than 300 DEG C, switch can further improve
Electric current ratio.Accordingly, it is considered to use to element heat resistance etc. and be same as annealing conditions that are not heated and forming film and anneal
When processing, electrical characteristic can be further increased.Such as annealing temperature can be made for 300 DEG C or more and less than 400 DEG C.In addition, by
The problem of (subtle protrusion is formed on surface) is wrapped in it will appear when being formed from aluminium grid, and the upper limit of annealing temperature is set
The generation of the defect can be efficiently controlled when being 350 DEG C.
Embodiments of the present invention are explained above, the invention is not limited in the above embodiments certainly, are not departing from
In the range of present subject matter, various modifications can be carried out to it.
For example, be illustrated by taking the manufacturing method of bottom gate type field-effect transistor as an example in the above-described embodiment,
Grid is formed in the lower layer side of active layer.But the present invention is not limited thereto, and it is brilliant to present invention can be suitably applied to top gate type field-effect
In the manufacturing method of body pipe, grid is formed in the upper layer side of active layer.
In addition, in the above-described embodiment, the film-forming temperature of active layer 15 (IGZO film 15F) is formed and is lived at 100 DEG C or more
Property layer 15 after annealing temperature be 300 DEG C.But the present invention is not limited thereto, it can be special according to the transistor of required element
Property suitably change film-forming temperature and annealing temperature.
【Reference sign】
10, base material；11, grid；14, gate insulating film；15, active layer；16, barrier layer；17 (17S, 17D), source/drain
Pole；19, protective film.
Claims (3)
1. a kind of manufacturing method of field-effect transistor, which is characterized in that
In the case where base material to be heated to 100 DEG C or more 200 DEG C of state of temperatures below, use oxygen pneumatic condition be 0.02Pa with
Upper 0.28Pa sputtering methods below form active layer on the substrate, wherein and the active layer has In-Ga-Zn-O set members,
It is made annealing treatment with 300 DEG C or more the heating temperature conditions less than 400 DEG C to being formed by the active layer.
2. the manufacturing method of field-effect transistor as described in claim 1, which is characterized in that
By the annealing, the ratio of the conducting electric current and cut-off current that make field-effect transistor reaches the water of 1.E+08
It is flat.
3. the manufacturing method of field-effect transistor as described in claim 1, which is characterized in that
Before forming the active layer by film process, reached using heating tube or the heating lamp heating base material above-mentioned
State of temperature.
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| KR102424181B1 (en) | 2010-12-17 | 2022-07-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Oxide material and semiconductor device |
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