WO2018181296A1 - Method for manufacturing channel-etch-type thin film transistor - Google Patents

Method for manufacturing channel-etch-type thin film transistor Download PDF

Info

Publication number
WO2018181296A1
WO2018181296A1 PCT/JP2018/012407 JP2018012407W WO2018181296A1 WO 2018181296 A1 WO2018181296 A1 WO 2018181296A1 JP 2018012407 W JP2018012407 W JP 2018012407W WO 2018181296 A1 WO2018181296 A1 WO 2018181296A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electrode
channel
film
thin film
Prior art date
Application number
PCT/JP2018/012407
Other languages
French (fr)
Japanese (ja)
Inventor
中村　好伸
宮本　忠芳
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Publication of WO2018181296A1 publication Critical patent/WO2018181296A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • One embodiment of the present invention relates to a method for manufacturing a channel-etched thin film transistor.
  • the active matrix substrate includes a switching element such as a thin film transistor (hereinafter, “TFT”) for each pixel.
  • TFT thin film transistor
  • An active matrix substrate including TFTs as switching elements is called a TFT substrate.
  • a TFT substrate used in a liquid crystal display device has, for example, a glass substrate, a plurality of TFTs supported by the glass substrate, gate wirings and source wirings, and pixel electrodes arranged in a matrix.
  • the gate electrode of each TFT is electrically connected to the gate wiring
  • the source electrode is electrically connected to the source wiring
  • the drain electrode is electrically connected to the pixel electrode.
  • the TFT, source wiring and gate wiring are usually covered with an interlayer insulating layer
  • the pixel electrode is provided on the interlayer insulating layer, and is connected to the drain electrode of the TFT in a contact hole formed in the interlayer insulating layer. Has been.
  • amorphous silicon TFT As TFTs, TFTs using an amorphous silicon film as an active layer (hereinafter referred to as “amorphous silicon TFT”) and TFTs using a polycrystalline silicon film as an active layer (hereinafter referred to as “polycrystalline silicon TFT”) have been widely used. Yes. Recently, an oxide semiconductor has attracted attention as a material for an active layer of a TFT. An oxide semiconductor TFT can operate at a higher speed than an amorphous silicon TFT. In addition, since the oxide semiconductor film is formed by a simpler process than the polycrystalline silicon film, the oxide semiconductor film can be applied to a device that requires a large area. In this specification, a TFT having an oxide semiconductor film as an active layer may be referred to as an “oxide semiconductor TFT”.
  • the source electrode and the source electrode of the TFT are generally formed from the same conductive film together with the source wiring.
  • a material of the conductive film aluminum (Al) or Al alloy having high conductivity is widely used. Recently, it has also been proposed to use copper (Cu) which is more excellent in conductivity.
  • a layer including the source wiring and formed of the same conductive film may be referred to as a “source wiring layer”.
  • a source wiring having a low wiring resistance can be formed.
  • Al film (or Al alloy film) and the semiconductor layer of the TFT are brought into contact with each other, there is a possibility that Al diffuses inside the semiconductor layer and desired TFT characteristics cannot be obtained. Even when the source wiring layer is formed using Cu, Cu may diffuse into the semiconductor layer, and desired TFT characteristics may not be obtained.
  • a heat treatment for example, about 200 to 600 ° C.
  • the surface of the Al layer may be deformed to generate a projection called hillock. Hillocks on the surface of the Al layer reduce the insulating properties of the interlayer insulating layer.
  • Patent Documents 1 and 2 disclose a source electrode and a drain electrode having a structure in which a molybdenum (Mo) layer, an Al layer, and a Mo layer are sequentially stacked.
  • Patent Document 3 discloses that a titanium (Ti) layer is formed between an Al layer or a Cu layer and an oxide semiconductor layer.
  • Patent Document 4 discloses a source electrode and a drain electrode having a structure in which a Ti layer, an Al layer, and a Ti layer are sequentially stacked.
  • the metal wiring material of the TFT may be formed in a laminated structure in which an Al layer is sandwiched between a Ti layer or a Mo layer in consideration of adhesion to upper and lower layers, reactivity, productivity, and the like. It is common.
  • the resistance and load capacity of the wiring have increased, and the problem of wiring delay has become apparent.
  • the only way to prevent the aperture ratio from decreasing is to increase the thickness of the wiring.
  • FIG. 1A and 1B are diagrams schematically showing main components of a TFT
  • FIG. 1A is a plan view
  • FIG. 1B is a cross-sectional view taken along line XX in FIG. 1A.
  • reference numeral 101 denotes a gate electrode
  • reference numeral 102 denotes a channel layer
  • reference numerals 103 and 104 denote source / drain electrodes (hereinafter referred to as “S / D electrodes”). Since reference numerals 103 and 104 are connected from the S / D electrode to the wiring, they are referred to as S / D electrode wirings here.
  • the film thicknesses of the S / D electrode wirings 103 and 104 are indicated by h.
  • FIG. 2A and 2B are enlarged views of the vicinity of the S / D electrode wiring 103 and the channel layer 102 on the left side of FIG. 1B, and FIG. 2A shows the case where the film thickness of the S / D electrode wiring 103 is h1. Is a case where the thickness of the S / D electrode wiring 103 is thicker than that in the case of FIG. 2A.
  • FIG. 2A and FIG. 2B what is indicated by reference numeral 105 using a dotted line is an upper insulating film (Pas film, protective film).
  • the upper insulating film 105 covers the tapered portion (including the end surface 103 a) of the S / D electrode wiring 103 between the S / D electrode wiring 103 and the channel layer 102.
  • the covering portions of the tapered portion (including the end surface 103a) of the upper insulating film 105 in FIGS. 2A and 2B are denoted by A1 and A2, respectively.
  • the coating of the end surface 103a extending in the direction perpendicular to the substrate is thinner than the coating of the surface 103b extending in the direction parallel to the substrate. Therefore, the covering portion A2 in the case of FIG. 2B in which the height of the end surface 103b, that is, the S / D electrode wiring 103 is thick, is deteriorated as compared with the covering portion A1 in the case of FIG. 2A.
  • oxide semiconductor TFTs that have recently been attracting attention, particularly channel etch type structures, moisture or the like is generated from the portions with poor coverage of the tapered portion of the S / D electrode (covered portions A1 and A2 in FIGS. 2A and 2B). Intrusion will result in abnormal characteristics and lead to serious defects leading to poor reliability.
  • the oxide semiconductor TFT is annealed at 300 ° C. or higher (eg, 350 ° C. for 1 hour) after forming the upper insulating film (passivation (Pas) film (eg, SiO 2 film), protective film) to diffuse oxygen from the Pas film.
  • passivation (Pas) film eg, SiO 2 film
  • protective film to diffuse oxygen from the Pas film. It is necessary to reduce the oxygen defects in the oxide semiconductor, but the deterioration of the coverage of the taper portion of the S / D electrode is caused by the volume change (shrink) of Al during the annealing and the volume change of Ti and Mo. This is because Al voids are generated in the tapered portion of the S / D electrode.
  • the “channel etch TFT” will be described in comparison with the “etch stop TFT”.
  • the etch stop layer is not formed on the channel region (layer), and the lower surface of the end of the source and drain electrodes on the channel side
  • the oxide semiconductor layer having a region (layer) is disposed in contact with the upper surface.
  • the “channel etch TFT” is formed, for example, by forming a conductive film for a source / drain electrode on an oxide semiconductor layer forming a channel region (layer) and performing source / drain separation. In the source / drain separation step, the surface portion of the channel region may be etched.
  • etch stop type TFT that is, a TFT in which an etch stop layer is formed on the channel region
  • the lower surface of the end of the source and drain electrodes on the channel side is located on the etch stop layer
  • Etch-stop type TFT forms an etch stop layer that covers the channel region of the oxide semiconductor layer, and then forms a conductive film for the source and drain electrodes on the oxide semiconductor layer and the etch stop layer. However, it is formed by performing source / drain separation.
  • One aspect of the present invention has been made in view of such circumstances, and an object of the present invention is to provide a method for manufacturing a channel-etched thin film transistor that can reduce deterioration in the coverage of the S / D electrode taper portion of the passivation film.
  • At least one of the source electrode and the drain electrode has a laminated structure of a metal layer other than Al / an Al layer / a metal layer other than Al
  • energy is applied so as to reduce a volume of an Al layer in the conductive film and a step of forming a conductive film for a source electrode and a drain electrode.
  • the step of applying energy may be a metal ion implantation step.
  • the metal ion implantation step may be performed by heating the substrate temperature to 100 to 250 ° C.
  • the metal layer may be made of either Ti or Mo.
  • a method for manufacturing a channel-etched thin film transistor that can reduce deterioration in the coverage of the S / D electrode taper portion of the passivation film can be provided.
  • FIG. 1B is a diagram schematically showing main components of a TFT, and is a cross-sectional view taken along line XX in FIG. 1A.
  • FIG. 1B is an enlarged view of the vicinity of the S / D electrode wiring 103 and the channel layer 102 on the left side of FIG. 1B, and shows a case where the film thickness of the S / D electrode wiring 103 is h1.
  • 1B is an enlarged view of the vicinity of the S / D electrode wiring 103 and the channel layer 102 on the left side of FIG. 1B, and is a case where the thickness of the S / D electrode wiring 103 is thicker than that in the case of FIG. 2A.
  • FIG. 3 is a first process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor.
  • FIG. 7 is a second process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor.
  • FIG. 7 is a third process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor.
  • FIG. 9 is a fourth process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor.
  • FIG. 9 is a fifth process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor.
  • FIG. 10 is a sixth process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor.
  • FIG. 9 is a fourth process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor.
  • FIG. 9 is a fifth process cross-sectional view illustrating an example of a method for
  • FIG. 11 is a seventh process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor. It is a graph which shows the result of the TFT characteristic before and behind performing the high temperature, high humidity reliability test which was placed for 150 hours in the environment of temperature 60 degreeC and humidity 95% about an Example and a comparative example. The result of the TFT characteristic before a property test is shown. It is a graph which shows the result of the TFT characteristic before and after performing the high temperature, high humidity reliability test which was placed in the environment of temperature 60 ° C. and humidity 95% for 150 hours for the example and the comparative example.
  • the result of the TFT characteristic after a property test is shown. It is a graph which shows the result of the TFT characteristic before and behind performing the high temperature, high humidity reliability test which was placed for 150 hours in the environment of temperature 60 degreeC and humidity 95% about an Example and a comparative example. The result of the TFT characteristic after a property test is shown.
  • At least one of the source electrode and the drain electrode has a laminated structure of a metal layer other than Al / an Al layer / a metal layer other than Al
  • a channel etch type thin film transistor having a channel layer made of an oxide semiconductor a conductive film forming process for an electrode for forming a conductive film for a source electrode and a drain electrode, and a volume of an Al layer in the conductive film
  • An energy applying step for applying energy so as to reduce the thickness an electrode forming step for patterning the conductive film to form a source electrode and a drain electrode, and a passivation film forming step for forming a passivation film.
  • 4A to 4G an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention will be described.
  • 4A to 4G are process cross-sectional views for explaining a method for manufacturing the channel-etched thin film transistor 10.
  • the substrate 11 is prepared.
  • a glass substrate, a silicon substrate, a heat-resistant plastic substrate, a resin substrate, or the like can be used.
  • plastic substrate or the resin substrate polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), acrylic, polyimide, or the like can be used.
  • silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like may be appropriately used as a base coat for each substrate. it can.
  • the gate electrode 12 is formed on the substrate 11.
  • the gate electrode 12 can be formed by depositing a conductive film on the substrate 11 by a sputtering method or the like and then patterning the conductive film using a photolithography process.
  • a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu), or an alloy thereof, or metal nitriding thereof A thing can be used suitably. Further, a plurality of these layers may be stacked.
  • W / TaN 370 nm / 50 nm as a conductive film with a sputtering apparatus
  • it can be patterned into a desired pattern by a photolithography method and a dry etching method.
  • a gate insulating film 14 is formed on the gate electrode 12.
  • the gate insulating film 14 can be formed using, for example, a CVD method.
  • the gate insulating film may be a single layer film or a multilayer film.
  • silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like can be used as appropriate.
  • the lower-layer side gate insulating film is formed using silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x> y) or the like, and the upper-layer side gate insulating film Is preferably formed using silicon oxide (SiOx), silicon oxynitride (SiOxNy) (x> y), or the like.
  • a rare gas element such as argon is preferably contained in the reaction gas and mixed into the insulating film.
  • a SiN layer (325 nm) and a SiO 2 layer (50 nm) can be successively deposited on the gate electrode 12 using a CVD apparatus.
  • the oxide semiconductor film 15 is formed over the gate insulating film 14.
  • the oxide semiconductor film 15 is formed by forming a thin film for an oxide semiconductor film on the gate insulating film 14 by sputtering or CVD, and then patterning the thin film for an oxide semiconductor film using a photolithography process. Can be formed.
  • etching can be performed using a resist mask in a photolithography process, and the oxide semiconductor film can be patterned into a desired shape. .
  • the oxide semiconductor included in the oxide semiconductor layer 15 may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion.
  • the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface.
  • the oxide semiconductor layer 15 may have a stacked structure of two or more layers. In the case where the oxide semiconductor layer 15 has a stacked structure, the oxide semiconductor layer 15 may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, a plurality of crystalline oxide semiconductor layers having different crystal structures may be included. In addition, a plurality of amorphous oxide semiconductor layers may be included.
  • the energy gap of the oxide semiconductor included in the upper layer is preferably larger than the energy gap of the oxide semiconductor included in the lower layer.
  • the energy gap of the lower oxide semiconductor may be larger than the energy gap of the upper oxide semiconductor.
  • the oxide semiconductor layer 15 may include at least one metal element of In, Ga, and Zn, for example.
  • the oxide semiconductor layer 15 is, for example, an In—Ga—Zn—O-based semiconductor (hereinafter, abbreviated as “In—Ga—Zn—O-based semiconductor”, and sometimes abbreviated as “IGZO”).
  • a TFT having an In—Ga—Zn—O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one hundredth of that of an a-Si TFT). It is suitably used as a drive TFT and a pixel TFT.
  • a TFT having an In—Ga—Zn—O-based semiconductor layer is used, power consumption of the display device can be significantly reduced.
  • the In—Ga—Zn—O based semiconductor may be amorphous or may have a crystalline part.
  • a crystalline In—Ga—Zn—O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.
  • Such a crystal structure of an In—Ga—Zn—O-based semiconductor is disclosed in, for example, Japanese Patent Laid-Open No. 2012-134475.
  • the oxide semiconductor layer may include another oxide semiconductor instead of the In—Ga—Zn—O-based semiconductor.
  • an In—Sn—Zn—O based semiconductor eg, In 2 O 3 —SnO 2 —ZnO
  • an In—Al—Zn—O based semiconductor e.g. In 2 O 3 —SnO 2 —ZnO
  • ZnO Zn—O based semiconductor
  • IZO In—Zn—O based semiconductor
  • ZTO Zn—Ti—O based semiconductor
  • Cd—Ge—O based semiconductor Cd—Pb—O based semiconductor
  • InGaO 3 (ZnO) 5 magnesium zinc oxide (Mg x Zn 1 ⁇ x O), cadmium zinc oxide (Cd x Zn 1-x O), cadmium oxide (CdO), Mg—Zn—O-based semiconductor, In—Ga—Sn—O-based semiconductor, and the like may be included.
  • ZnO is amorphous in which one or more impurity elements of Group 1 element, Group 13 element, Group 14 element, Group 15 element or Group 17 element are added.
  • a state, a polycrystalline state, a microcrystalline state in which an amorphous state and a polycrystalline state are mixed, or a state in which no impurity element is added can be used.
  • a conductive film 16 for forming a source electrode and a drain electrode is formed on the entire surface of the oxide semiconductor layer 15 and the gate insulating film 14.
  • the conductive layer 16 has a laminated structure in which an aluminum (Al) layer is sandwiched between metal layers other than Al.
  • a metal such as titanium (Ti) or molybdenum (Mo), an alloy thereof, or a metal nitride thereof can be used as appropriate.
  • a Ti layer (50 nm) / Al layer (300 nm) / Ti layer (30 nm) can be formed by sputtering.
  • ion implantation is performed with acceleration energy that passes through the metal layer disposed on the Al layer and does not reach the metal layer disposed below the Al layer (for example, 150 keV, 10 16 / cm 2 ), and by applying the energy, the volume of the Al layer is changed (shrinked) in advance.
  • the acceleration energy for ion implantation can be, for example, 80 to 200 keV, and the density can be, for example, 10 15 to 10 17 ions / cm 2 .
  • various ion-implanted metal elements for imparting energy can be used, but aluminum (Al) is preferable because aluminum (Al) generally includes an impurity element and thus the electrical conductivity is lowered.
  • the laminated structure of the conductive film for S / D electrodes is Ti layer / Al layer / Ti layer
  • the Ti layer under the Al layer and the oxide semiconductor layer for example, IGZO layer
  • the Ti layer under the Al layer and the oxide semiconductor layer react to form a deteriorated layer.
  • the electrode conductive film 16 is processed into a desired shape using a resist mask in a photolithography process, thereby forming the source electrode 16A or the drain electrode 16B.
  • a passivation film (Pas film) 17 that is an insulating film is formed so as to cover the entire structure that has been formed.
  • the thickness of the passivation film is, for example, about 300 to 500 nm.
  • This insulating film can be formed using an insulating material such as silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxynitride using a thin film formation method such as a plasma CVD method or a sputtering method.
  • annealing is performed at a temperature of about 200 to 400 ° C.
  • the passivation film Pas film
  • it can be set to 350 ° C. for 1 hour.
  • the same conditions as the annealing for reducing oxygen defects in the oxide semiconductor film for example, When annealing is performed at 350 ° C. for 1 hour, the lowermost Ti layer or Mo layer of the S / D electrode conductive film reacts with the oxide semiconductor layer, and the oxide semiconductor layer in the channel region changes in quality. Therefore, a TFT having good characteristics cannot be obtained.
  • the layer to which energy is applied can be only the Al layer in the conductive film for the S / D electrode.
  • Such a reaction between the lowermost Ti layer or Mo layer of the S / D electrode conductive film and the oxide semiconductor layer does not occur.
  • a resist mask is formed on the passivation film (Pas film) by a photolithography process, etching for contact holes is performed, and heat treatment is performed on the entire surface of the substrate.
  • the passivation film (Pas film) is not limited to a single layer, and may be two layers or three or more layers. However, the film in contact with the oxide semiconductor layer (for example, the IGZO film) contains oxygen. It is preferably included. Further, a planarizing film made of an organic insulating material may be further formed on the passivation film (Pas film).
  • a transparent conductive film such as ITO or IZO film is formed on the entire surface of the substrate on which the passivation film (Pas film) is formed, for example, by sputtering, and then photolithography, wet etching, and A transparent electrode is formed by removing and cleaning the resist.
  • a display device is obtained in which a liquid crystal layer is sandwiched and held between a counter substrate.
  • Example 10 Glass (AN100 manufactured by Asahi Glass Co., Ltd.) is used as the substrate, and a laminated film of W (370 nm) / TaN (50 nm) is deposited as a conductive film on this substrate using a sputtering apparatus, and then a photolithography method and a dry etching method. To form a gate electrode by processing into a desired pattern. Next, SiN (325 nm) and SiO 2 (50 nm) were successively deposited on the gate electrode by a CVD apparatus to form a gate insulating film. Next, a channel layer made of IGZO was formed on the gate electrode.
  • a three-layer laminated structure of Ti layer (50 nm) / Al layer (300 nm) / Ti layer (30 nm) was formed as a conductive film for S / D electrodes by a sputtering apparatus.
  • the substrate was set to 200 ° C., and Al ion implantation (150 keV, 10 16 ions / cm 2 ) was performed for 1 hour.
  • the S / D electrode conductive film was processed into a desired pattern by a photolithography method and a dry etching method to form an S / D electrode.
  • SiO 2 (300 nm) / SiN (300 nm) was deposited as a passivation film, and annealing (350 ° C., 1 hour) was performed to reduce oxygen defects in the channel layer made of IGZO. Thereafter, an organic flattening film was formed, and an ITO transparent electrode was further formed as a common electrode to produce a channel etch type TFT.
  • the comparative example produced a channel etch type TFT in the same manner as the example except that the Al ion implantation step was not performed.
  • FIG. 5A to 5C show the results of TFT characteristics before and after conducting a high-temperature and high-humidity reliability test for 150 hours in an environment of a temperature of 60 ° C. and a humidity of 95% for the examples and comparative examples.
  • FIG. 5A shows the result of TFT characteristics before the high-temperature and high-humidity reliability test for the example
  • FIG. 5B shows the result of TFT characteristics after the high-temperature and high-humidity reliability test for the comparative example
  • FIG. 5C shows the results of TFT characteristics after the high-temperature and high-humidity reliability test for the example.
  • the TFT characteristics before the high-temperature and high-humidity reliability test were the same as in FIG. 5A.
  • the TFT size (channel size) has a length (L) and a width (W) of 10 ⁇ m and 480 ⁇ m, respectively.
  • the TFT manufactured by the manufacturing method according to one embodiment of the present invention was good with no change in TFT characteristics even after the high temperature and high humidity reliability test.
  • the TFT characteristics of the TFT manufactured by the conventional process deteriorated after the high temperature and high humidity reliability test. This is presumably because moisture entered from cracks generated in the Pas film due to Al voids in the tapered portion of the S / D electrode.
  • One embodiment of the present invention can be applied to a method for manufacturing a channel-etched thin film transistor in which it is necessary to reduce deterioration of the coverage of the S / D electrode taper portion of the passivation film.
  • TFT Thin film transistor
  • SYMBOLS Substrate 12
  • Gate electrode 14 Gate insulating film 15
  • Channel layer 16 Electrode conductive film 16A
  • Source electrode 16B Drain electrode 17 Passivation film (protective film)

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)

Abstract

A method for manufacturing a channel-etch-type thin film transistor according to one mode of the present invention is a method for manufacturing a channel-etch-type thin film transistor in which at least one electrode from among a source electrode and a drain electrode comprises a non-Al-metal layer/Al layer/non-Al metal layer laminated structure, and which has a channel layer comprising an oxide semiconductor, wherein the method has a step for forming an electrically conductive film for an electrode in which an electrically conductive film for use as the source electrode and the drain electrode is formed, an energy imparting step for imparting energy so as to reduce the volume of the Al layer in the electrically conductive film, an electrode formation step for forming the source electrode and the drain electrode by patterning the electrically conductive film, and a passivation film formation step for forming a passivation film.

Description

チャネルエッチ型薄膜トランジスタの製造方法Manufacturing method of channel etch type thin film transistor
　本発明の一態様は、チャネルエッチ型薄膜トランジスタの製造方法に関する。
　本願は、２０１７年３月２９日に日本に出願された特願２０１７－０６４３３４号について優先権を主張し、その内容をここに援用する。 One embodiment of the present invention relates to a method for manufacturing a channel-etched thin film transistor.
This application claims priority on Japanese Patent Application No. 2017-064334 filed in Japan on March 29, 2017, the contents of which are incorporated herein by reference.
　近年、アクティブマトリクス基板を備える表示装置が広く用いられている。アクティブマトリクス基板は、画素ごとに薄膜トランジスタ（Ｔｈｉｎ　Ｆｉｌｍ　Ｔｒａｎｓｉｓｔｏｒ；以下、「ＴＦＴ」）などのスイッチング素子を備えている。スイッチング素子としてＴＦＴを備えるアクティブマトリクス基板は、ＴＦＴ基板と呼ばれる。 In recent years, display devices including an active matrix substrate have been widely used. The active matrix substrate includes a switching element such as a thin film transistor (hereinafter, “TFT”) for each pixel. An active matrix substrate including TFTs as switching elements is called a TFT substrate.
　液晶表示装置等に用いられるＴＦＴ基板は、例えば、ガラス基板と、ガラス基板に支持された複数のＴＦＴと、ゲート配線およびソース配線と、マトリクス状に配列された画素電極とを有している。各ＴＦＴのゲート電極はゲート配線に、ソース電極はソース配線に、ドレイン電極は画素電極に、それぞれ電気的に接続されている。ＴＦＴ、ソース配線およびゲート配線は、通常、層間絶縁層で覆われており、画素電極は、層間絶縁層上に設けられ、層間絶縁層に形成されたコンタクトホール内で、ＴＦＴのドレイン電極と接続されている。 A TFT substrate used in a liquid crystal display device has, for example, a glass substrate, a plurality of TFTs supported by the glass substrate, gate wirings and source wirings, and pixel electrodes arranged in a matrix. The gate electrode of each TFT is electrically connected to the gate wiring, the source electrode is electrically connected to the source wiring, and the drain electrode is electrically connected to the pixel electrode. The TFT, source wiring and gate wiring are usually covered with an interlayer insulating layer, and the pixel electrode is provided on the interlayer insulating layer, and is connected to the drain electrode of the TFT in a contact hole formed in the interlayer insulating layer. Has been.
　ＴＦＴとしては、従来、アモルファスシリコン膜を活性層とするＴＦＴ（以下、「アモルファスシリコンＴＦＴ」）や多結晶シリコン膜を活性層とするＴＦＴ（以下、「多結晶シリコンＴＦＴ」）が広く用いられている。最近では、ＴＦＴの活性層の材料として、酸化物半導体が注目されている。酸化物半導体ＴＦＴは、アモルファスシリコンＴＦＴよりも高速で動作することが可能である。また、酸化物半導体膜は、多結晶シリコン膜よりも簡便なプロセスで形成されるため、大面積が必要とされる装置にも適用できる。本明細書では、酸化物半導体膜を活性層とするＴＦＴを「酸化物半導体ＴＦＴ」と称することがある。 As TFTs, TFTs using an amorphous silicon film as an active layer (hereinafter referred to as “amorphous silicon TFT”) and TFTs using a polycrystalline silicon film as an active layer (hereinafter referred to as “polycrystalline silicon TFT”) have been widely used. Yes. Recently, an oxide semiconductor has attracted attention as a material for an active layer of a TFT. An oxide semiconductor TFT can operate at a higher speed than an amorphous silicon TFT. In addition, since the oxide semiconductor film is formed by a simpler process than the polycrystalline silicon film, the oxide semiconductor film can be applied to a device that requires a large area. In this specification, a TFT having an oxide semiconductor film as an active layer may be referred to as an “oxide semiconductor TFT”.
　ＴＦＴのソース電極およびソース電極は、一般に、ソース配線とともに、同一の導電膜から形成される。この導電膜の材料としては、高い導電性を有する、アルミニウム（Ａｌ）やＡｌ合金が広く用いられている。また、最近では、いっそう導電性に優れる銅（Ｃｕ）を用いることも提案されている。本明細書では、ソース配線を含む、同一の導電膜から形成される層を「ソース配線層」と称することがある。 The source electrode and the source electrode of the TFT are generally formed from the same conductive film together with the source wiring. As a material of the conductive film, aluminum (Al) or Al alloy having high conductivity is widely used. Recently, it has also been proposed to use copper (Cu) which is more excellent in conductivity. In this specification, a layer including the source wiring and formed of the same conductive film may be referred to as a “source wiring layer”.
　上述したＡｌ等を用いてソース配線層を形成することにより、配線抵抗の小さなソース配線を形成することができる。その一方、Ａｌ膜（あるいはＡｌ合金膜）とＴＦＴの半導体層とを接触させると、半導体層内部にＡｌが拡散し、所望のＴＦＴ特性を得られなくなるおそれがある。Ｃｕを用いてソース配線層を形成する場合にも、半導体層内部にＣｕが拡散し、所望のＴＦＴ特性を得られなくなるおそれがある。また、ＴＦＴ基板の製造工程において、ソース配線層の形成後に熱処理（例えば２００～６００℃程度）を行う場合、Ａｌ層の表面が変形し、ヒロックと呼ばれる突起物を生じることがある。Ａｌ層の表面のヒロックは、層間絶縁層の絶縁性を低下させる。 By forming the source wiring layer using Al or the like described above, a source wiring having a low wiring resistance can be formed. On the other hand, when the Al film (or Al alloy film) and the semiconductor layer of the TFT are brought into contact with each other, there is a possibility that Al diffuses inside the semiconductor layer and desired TFT characteristics cannot be obtained. Even when the source wiring layer is formed using Cu, Cu may diffuse into the semiconductor layer, and desired TFT characteristics may not be obtained. Further, in the TFT substrate manufacturing process, when a heat treatment (for example, about 200 to 600 ° C.) is performed after the source wiring layer is formed, the surface of the Al layer may be deformed to generate a projection called hillock. Hillocks on the surface of the Al layer reduce the insulating properties of the interlayer insulating layer.
　これらのことから、積層膜を用いてソース配線層を形成することが提案されている。例えば特許文献１および２には、モリブデン（Ｍｏ）層、Ａｌ層およびＭｏ層が順に積層された構造を有するソース電極およびドレイン電極が開示されている。特許文献３には、Ａｌ層またはＣｕ層と酸化物半導体層との間にチタン（Ｔｉ）層を形成することが開示されている。特許文献４には、Ｔｉ層、Ａｌ層およびＴｉ層が順に積層された構造を有するソース電極およびドレイン電極が開示されている。 For these reasons, it has been proposed to form a source wiring layer using a laminated film. For example, Patent Documents 1 and 2 disclose a source electrode and a drain electrode having a structure in which a molybdenum (Mo) layer, an Al layer, and a Mo layer are sequentially stacked. Patent Document 3 discloses that a titanium (Ti) layer is formed between an Al layer or a Cu layer and an oxide semiconductor layer. Patent Document 4 discloses a source electrode and a drain electrode having a structure in which a Ti layer, an Al layer, and a Ti layer are sequentially stacked.
特開平１１－２５８６２５号公報Japanese Patent Laid-Open No. 11-258625 特開２００２－１１１００４号公報JP 2002-111004 A 特開２０１０－１２３９２３号公報JP 2010-123923 A 特開２０１０－１２３７４８号公報JP 2010-123748 A
　上述の通り、ＴＦＴの金属配線の材料としては、上下層との密着性や反応性，生産性等を考慮して、Ａｌ層をＴｉ層あるいはＭｏ層などで挟んだ積層構造で形成することが一般的である。近年、パネルの高精細化・大画面化に伴い、配線の抵抗および負荷容量が増大し、配線遅延の問題が顕在化している。配線遅延の問題を低減するには、配線の抵抗を低くすることが有効である。
　しかしながら、現状では開口率を低下させないためには配線の膜厚を厚くするしかなく、配線の膜厚を厚くした場合、配線電極のテーパー部の上層絶縁膜（Pas膜、保護膜）の被覆性の悪化に伴う歩留り低下が問題となる。
　この問題について図１Ａ及び図１Ｂを用いて説明する。 As described above, the metal wiring material of the TFT may be formed in a laminated structure in which an Al layer is sandwiched between a Ti layer or a Mo layer in consideration of adhesion to upper and lower layers, reactivity, productivity, and the like. It is common. In recent years, with the high definition and large screen of the panel, the resistance and load capacity of the wiring have increased, and the problem of wiring delay has become apparent. In order to reduce the wiring delay problem, it is effective to lower the wiring resistance.
However, at present, the only way to prevent the aperture ratio from decreasing is to increase the thickness of the wiring. When the wiring thickness is increased, the coverage of the upper insulating film (Pas film, protective film) of the tapered portion of the wiring electrode Yield reduction due to deterioration of the problem becomes a problem.
This problem will be described with reference to FIGS. 1A and 1B.
　図１Ａ及び図１Ｂは、ＴＦＴについてその主な構成要素を模式的に示す図であり、図１Ａは平面図であり、図１Ｂは、図１ＡのＸ－Ｘ線で切った断面図である。
　図１Ａ及び図１Ｂにおいて、符号１０１はゲート電極、符号１０２はチャネル層、符号１０３及び１０４は、ソース・ドレイン電極（以下、「Ｓ／Ｄ電極」）である。符号１０３及び１０４はＳ／Ｄ電極から配線につながるので、ここでは、Ｓ／Ｄ電極配線ということにする。
　図１Ｂにおいて、Ｓ／Ｄ電極配線１０３、１０４の膜厚をｈで示している。
　図２Ａ及び図２Ｂは、図１Ｂの左側のＳ／Ｄ電極配線１０３及びチャネル層１０２近傍の拡大図であり、図２ＡはＳ／Ｄ電極配線１０３の膜厚がｈ１の場合であり、図２Ｂは図２Ａの場合よりもＳ／Ｄ電極配線１０３の膜厚が厚いｈ２の場合である。図２Ａ及び図２Ｂにおいて、点線を用いて符号１０５で示すのは上層絶縁膜（Pas膜、保護膜）である。
　上層絶縁膜１０５は、Ｓ／Ｄ電極配線１０３からチャネル層１０２の間でＳ／Ｄ電極配線１０３のテーパー部（端面１０３ａを含む）を被覆する。図２Ａ、図２Ｂの上層絶縁膜１０５のテーパー部（端面１０３ａを含む）の被覆部分をそれぞれ、Ａ１，Ａ２で示す。基板に垂直方向に拡がる端面１０３ａの被覆は基板に平行方向に拡がる面１０３ｂの被覆に比べて薄くなる。そのため、その端面１０３ｂの高さすなわち、Ｓ／Ｄ電極配線１０３の膜厚が厚い図２Ｂの場合の被覆部分Ａ２は、図２Ａの場合の被覆部分Ａ１に比べて被覆性が悪化する。 1A and 1B are diagrams schematically showing main components of a TFT, FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line XX in FIG. 1A.
1A and 1B, reference numeral 101 denotes a gate electrode, reference numeral 102 denotes a channel layer, and reference numerals 103 and 104 denote source / drain electrodes (hereinafter referred to as “S / D electrodes”). Since reference numerals 103 and 104 are connected from the S / D electrode to the wiring, they are referred to as S / D electrode wirings here.
In FIG. 1B, the film thicknesses of the S / D electrode wirings 103 and 104 are indicated by h.
2A and 2B are enlarged views of the vicinity of the S / D electrode wiring 103 and the channel layer 102 on the left side of FIG. 1B, and FIG. 2A shows the case where the film thickness of the S / D electrode wiring 103 is h1. Is a case where the thickness of the S / D electrode wiring 103 is thicker than that in the case of FIG. 2A. In FIG. 2A and FIG. 2B, what is indicated by reference numeral 105 using a dotted line is an upper insulating film (Pas film, protective film).
The upper insulating film 105 covers the tapered portion (including the end surface 103 a) of the S / D electrode wiring 103 between the S / D electrode wiring 103 and the channel layer 102. The covering portions of the tapered portion (including the end surface 103a) of the upper insulating film 105 in FIGS. 2A and 2B are denoted by A1 and A2, respectively. The coating of the end surface 103a extending in the direction perpendicular to the substrate is thinner than the coating of the surface 103b extending in the direction parallel to the substrate. Therefore, the covering portion A2 in the case of FIG. 2B in which the height of the end surface 103b, that is, the S / D electrode wiring 103 is thick, is deteriorated as compared with the covering portion A1 in the case of FIG. 2A.
　更に、最近注目されている酸化物半導体ＴＦＴ、特にチャネルエッチ型構造においては、Ｓ／Ｄ電極のテーパー部の被覆性の悪い部分（図２Ａ及び図２Ｂの被覆部分Ａ１，Ａ２）から水分等が侵入すると、特性異常となり、信頼性不良につながる重大な欠陥に至る。 Furthermore, in oxide semiconductor TFTs that have recently been attracting attention, particularly channel etch type structures, moisture or the like is generated from the portions with poor coverage of the tapered portion of the S / D electrode (covered portions A1 and A2 in FIGS. 2A and 2B). Intrusion will result in abnormal characteristics and lead to serious defects leading to poor reliability.
　酸化物半導体ＴＦＴは上層絶縁膜（パッシベーション（Pas）膜（例えばＳｉＯ２膜）、保護膜）成膜後に３００℃以上（例えば、３５０℃で１時間）のアニールを行い、Pas膜から酸素を拡散させることで酸化物半導体中の酸素欠陥を減らす必要があるが、上記Ｓ／Ｄ電極のテーパー部の被覆性悪化は、このアニール時のＡｌの体積変化（シュリンク）量がＴｉやＭｏの体積変化よりも大きいためにＳ／Ｄ電極のテーパー部にＡｌボイドが発生することに起因する。 The oxide semiconductor TFT is annealed at 300 ° C. or higher (eg, 350 ° C. for 1 hour) after forming the upper insulating film (passivation (Pas) film (eg, SiO 2 film), protective film) to diffuse oxygen from the Pas film. It is necessary to reduce the oxygen defects in the oxide semiconductor, but the deterioration of the coverage of the taper portion of the S / D electrode is caused by the volume change (shrink) of Al during the annealing and the volume change of Ti and Mo. This is because Al voids are generated in the tapered portion of the S / D electrode.
　ここで、「チャネルエッチ型ＴＦＴ」を「エッチストップ型ＴＦＴ」と対比して説明する。
　まず、「チャネルエッチ型ＴＦＴ」では、例えば図３に示されるように、チャネル領域（層）上にエッチストップ層が形成されておらず、ソースおよびドレイン電極のチャネル側の端部下面は、チャネル領域（層）を有する酸化物半導体層の上面と接するように配置されている。「チャネルエッチ型ＴＦＴ」は、例えばチャネル領域（層）を形成する酸化物半導体層上にソース・ドレイン電極用の導電膜を形成し、ソース・ドレイン分離を行うことによって形成される。ソース・ドレイン分離工程において、チャネル領域の表面部分がエッチングされる場合がある。
　これに対して、「エッチストップ型ＴＦＴ」すなわち、チャネル領域上にエッチストップ層が形成されたＴＦＴでは、ソースおよびドレイン電極のチャネル側の端部下面は、例えばエッチストップ層上に位置する。「エッチストップ型ＴＦＴ」は、例えば酸化物半導体層のうちチャネル領域となる部分を覆うエッチストップ層を形成した後、酸化物半導体層およびエッチストップ層上にソース・ドレイン電極用の導電膜を形成し、ソース・ドレイン分離を行うことによって形成される。 Here, the “channel etch TFT” will be described in comparison with the “etch stop TFT”.
First, in the “channel etch TFT”, for example, as shown in FIG. 3, the etch stop layer is not formed on the channel region (layer), and the lower surface of the end of the source and drain electrodes on the channel side The oxide semiconductor layer having a region (layer) is disposed in contact with the upper surface. The “channel etch TFT” is formed, for example, by forming a conductive film for a source / drain electrode on an oxide semiconductor layer forming a channel region (layer) and performing source / drain separation. In the source / drain separation step, the surface portion of the channel region may be etched.
In contrast, in an “etch stop type TFT”, that is, a TFT in which an etch stop layer is formed on the channel region, the lower surface of the end of the source and drain electrodes on the channel side is located on the etch stop layer, for example. “Etch-stop type TFT”, for example, forms an etch stop layer that covers the channel region of the oxide semiconductor layer, and then forms a conductive film for the source and drain electrodes on the oxide semiconductor layer and the etch stop layer. However, it is formed by performing source / drain separation.
　本発明の一態様はこのような事情に鑑みてなされたものであって、パッシベーション膜のＳ／Ｄ電極テーパー部の被覆性の悪化を低減できるチャネルエッチ型薄膜トランジスタの製造方法を提供することを目的とする。 One aspect of the present invention has been made in view of such circumstances, and an object of the present invention is to provide a method for manufacturing a channel-etched thin film transistor that can reduce deterioration in the coverage of the S / D electrode taper portion of the passivation film. And
　本発明の一態様に係るチャネルエッチ型薄膜トランジスタの製造方法は、ソース電極及びドレイン電極の少なくとも一方の電極が、Ａｌ以外の金属層／Ａｌ層／Ａｌ以外の金属層の積層構造からなり、かつ、酸化物半導体からなるチャネル層を有するチャネルエッチ型薄膜トランジスタの製造方法において、ソース電極及びドレイン電極用の導電膜を成膜する工程と、前記導電膜中のＡｌ層の体積を縮小させるようにエネルギーを付与する工程と、前記導電膜をパターニングしてソース電極及びドレイン電極を形成する工程と、パッシベーション膜を形成する工程と、有する。 In the method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention, at least one of the source electrode and the drain electrode has a laminated structure of a metal layer other than Al / an Al layer / a metal layer other than Al, and In a method for manufacturing a channel-etched thin film transistor having a channel layer made of an oxide semiconductor, energy is applied so as to reduce a volume of an Al layer in the conductive film and a step of forming a conductive film for a source electrode and a drain electrode. A step of applying, a step of patterning the conductive film to form a source electrode and a drain electrode, and a step of forming a passivation film.
　本発明の一態様に係るチャネルエッチ型薄膜トランジスタの製造方法は、エネルギーを付与する工程は、金属イオン注入工程であってもよい。 In the method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention, the step of applying energy may be a metal ion implantation step.
　本発明の一態様に係るチャネルエッチ型薄膜トランジスタの製造方法は、金属イオン注入工程は、基板温度を１００～２５０℃に加熱して行ってもよい。 In the method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention, the metal ion implantation step may be performed by heating the substrate temperature to 100 to 250 ° C.
　本発明の一態様に係るチャネルエッチ型薄膜トランジスタの製造方法は、前記金属層がＴｉ又はＭｏのいずれかからなってもよい。 In the method for manufacturing a channel etch type thin film transistor according to an aspect of the present invention, the metal layer may be made of either Ti or Mo.
　本発明の一態様によるチャネルエッチ型薄膜トランジスタの製造方法によれば、パッシベーション膜のＳ／Ｄ電極テーパー部の被覆性の悪化を低減できるチャネルエッチ型薄膜トランジスタの製造方法を提供できる。 According to the method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention, a method for manufacturing a channel-etched thin film transistor that can reduce deterioration in the coverage of the S / D electrode taper portion of the passivation film can be provided.
ＴＦＴについてその主な構成要素を模式的に示す平面図である。It is a top view which shows typically the main component about TFT. ＴＦＴについてその主な構成要素を模式的に示す図であり、図１ＡのＸ－Ｘ線で切った断面図である。1B is a diagram schematically showing main components of a TFT, and is a cross-sectional view taken along line XX in FIG. 1A. FIG. 図１Ｂの左側のＳ／Ｄ電極配線１０３及びチャネル層１０２近傍の拡大図であり、Ｓ／Ｄ電極配線１０３の膜厚がｈ１の場合である。1B is an enlarged view of the vicinity of the S / D electrode wiring 103 and the channel layer 102 on the left side of FIG. 1B, and shows a case where the film thickness of the S / D electrode wiring 103 is h1. 図１Ｂの左側のＳ／Ｄ電極配線１０３及びチャネル層１０２近傍の拡大図であり、図２Ａの場合よりもＳ／Ｄ電極配線１０３の膜厚が厚いｈ２の場合である。1B is an enlarged view of the vicinity of the S / D electrode wiring 103 and the channel layer 102 on the left side of FIG. 1B, and is a case where the thickness of the S / D electrode wiring 103 is thicker than that in the case of FIG. 2A. チャネルエッチ型ＴＦＴの典型的な構造を示す断面模式である。It is a cross-sectional model which shows the typical structure of a channel etch type TFT. 本発明の一態様によるチャネルエッチ型薄膜トランジスタの製造方法の一例を示すものであり、チャネルエッチ型薄膜トランジスタの製造方法を説明するための第１の工程断面図である。FIG. 3 is a first process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor. 本発明の一態様によるチャネルエッチ型薄膜トランジスタの製造方法の一例を示すものであり、チャネルエッチ型薄膜トランジスタの製造方法を説明するための第２の工程断面図である。FIG. 7 is a second process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor. 本発明の一態様によるチャネルエッチ型薄膜トランジスタの製造方法の一例を示すものであり、チャネルエッチ型薄膜トランジスタの製造方法を説明するための第３の工程断面図である。FIG. 7 is a third process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor. 本発明の一態様によるチャネルエッチ型薄膜トランジスタの製造方法の一例を示すものであり、チャネルエッチ型薄膜トランジスタの製造方法を説明するための第４の工程断面図である。FIG. 9 is a fourth process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor. 本発明の一態様によるチャネルエッチ型薄膜トランジスタの製造方法の一例を示すものであり、チャネルエッチ型薄膜トランジスタの製造方法を説明するための第５の工程断面図である。FIG. 9 is a fifth process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor. 本発明の一態様によるチャネルエッチ型薄膜トランジスタの製造方法の一例を示すものであり、チャネルエッチ型薄膜トランジスタの製造方法を説明するための第６の工程断面図である。FIG. 10 is a sixth process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor. 本発明の一態様によるチャネルエッチ型薄膜トランジスタの製造方法の一例を示すものであり、チャネルエッチ型薄膜トランジスタの製造方法を説明するための第７の工程断面図である。FIG. 11 is a seventh process cross-sectional view illustrating an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention and illustrating a method for manufacturing a channel-etched thin film transistor. 実施例及び比較例について、温度６０℃、湿度９５％の環境下に１５０時間置いた高温高湿信頼性試験を行う前後のＴＦＴ特性の結果を示すグラフであり、実施例について、高温高湿信頼性試験前のＴＦＴ特性の結果を示すものである。It is a graph which shows the result of the TFT characteristic before and behind performing the high temperature, high humidity reliability test which was placed for 150 hours in the environment of temperature 60 degreeC and humidity 95% about an Example and a comparative example. The result of the TFT characteristic before a property test is shown. 実施例及び比較例について、温度６０℃、湿度９５％の環境下に１５０時間置いた高温高湿信頼性試験を行う前後のＴＦＴ特性の結果を示すグラフであり、比較例について、高温高湿信頼性試験後のＴＦＴ特性の結果を示すものである。It is a graph which shows the result of the TFT characteristic before and after performing the high temperature, high humidity reliability test which was placed in the environment of temperature 60 ° C. and humidity 95% for 150 hours for the example and the comparative example. The result of the TFT characteristic after a property test is shown. 実施例及び比較例について、温度６０℃、湿度９５％の環境下に１５０時間置いた高温高湿信頼性試験を行う前後のＴＦＴ特性の結果を示すグラフであり、実施例について、高温高湿信頼性試験後のＴＦＴ特性の結果を示すものである。It is a graph which shows the result of the TFT characteristic before and behind performing the high temperature, high humidity reliability test which was placed for 150 hours in the environment of temperature 60 degreeC and humidity 95% about an Example and a comparative example. The result of the TFT characteristic after a property test is shown.
　以下、図を参照しながら、本発明の一態様によるチャネルエッチ型薄膜トランジスタの製造方法について説明する。なお、以下の全ての図面においては、図面を見やすくするため、各構成要素の寸法や比率などは適宜異ならせてある。 Hereinafter, a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention will be described with reference to the drawings. In all the drawings below, the dimensions and ratios of the constituent elements are appropriately changed in order to make the drawings easy to see.
　本発明の一実施形態に係るチャネルエッチ型薄膜トランジスタの製造方法は、ソース電極及びドレイン電極の少なくとも一方の電極が、Ａｌ以外の金属層／Ａｌ層／Ａｌ以外の金属層の積層構造からなり、かつ、酸化物半導体からなるチャネル層を有するチャネルエッチ型薄膜トランジスタの製造方法において、ソース電極及びドレイン電極用の導電膜を成膜する電極用導電膜成膜工程と、前記導電膜中のＡｌ層の体積を縮小させるようにエネルギーを付与するエネルギー付与工程と、前記導電膜をパターニングしてソース電極及びドレイン電極を形成する電極形成工程と、パッシベーション膜を形成するパッシベーション膜形成工程と、有する。 In the method of manufacturing a channel etch type thin film transistor according to an embodiment of the present invention, at least one of the source electrode and the drain electrode has a laminated structure of a metal layer other than Al / an Al layer / a metal layer other than Al, and In the method of manufacturing a channel etch type thin film transistor having a channel layer made of an oxide semiconductor, a conductive film forming process for an electrode for forming a conductive film for a source electrode and a drain electrode, and a volume of an Al layer in the conductive film An energy applying step for applying energy so as to reduce the thickness, an electrode forming step for patterning the conductive film to form a source electrode and a drain electrode, and a passivation film forming step for forming a passivation film.
　図４Ａ～図４Ｇを参照して、本発明の一態様によるチャネルエッチ型薄膜トランジスタの製造方法の例を説明する。図４Ａ～図４Ｇは、チャネルエッチ型薄膜トランジスタ１０の製造方法を説明するための工程断面図である。 4A to 4G, an example of a method for manufacturing a channel-etched thin film transistor according to one embodiment of the present invention will be described. 4A to 4G are process cross-sectional views for explaining a method for manufacturing the channel-etched thin film transistor 10.
＜基板の準備＞
　まず、基板１１を用意する。基板１１としては、ガラス基板、シリコン基板、耐熱性を有するプラスチック基板又は樹脂基板等を用いることができる。プラスチック基板又は樹脂基板として、ポリエチレンテレフタレート（ＰＥＴ）、ポリエチレンナフタレート（ＰＥＮ）、ポリエーテルサルフォン（ＰＥＳ）、アクリル、ポリイミド等を用いることができる。
　また、各々の基板にベースコートとして、酸化珪素（ＳｉＯｘ）、窒化珪素（ＳｉＮｘ）、酸化窒化珪素（ＳｉＯｘＮｙ）（ｘ＞ｙ）、窒化酸化珪素（ＳｉＮｘＯｙ）（ｘ＞ｙ）等を適宜用いることもできる。 <Preparation of substrate>
First, the substrate 11 is prepared. As the substrate 11, a glass substrate, a silicon substrate, a heat-resistant plastic substrate, a resin substrate, or the like can be used. As the plastic substrate or the resin substrate, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), acrylic, polyimide, or the like can be used.
Further, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like may be appropriately used as a base coat for each substrate. it can.
＜ゲート電極の形成＞
　次に、図４Ａに示すように、基板１１上にゲート電極１２を形成する。ゲート電極１２は、スパッタリング法等により基板１１上に導電膜を堆積した後、フォトリソグラフィプロセスを用いて導電膜をパターニングすることによって形成することができる。導電膜としては、アルミニウム（Ａｌ）、タングステン（Ｗ）、モリブデン（Ｍｏ）、タンタル（Ｔａ）、クロム（Ｃｒ）、チタン（Ｔｉ）、銅（Ｃｕ）等の金属又はその合金、若しくはその金属窒化物を適宜用いることができる。また、これら複数の層を積層して形成してもよい。例えば、導電膜として、Ｗ／ＴａＮ=３７０ｎｍ／５０ｎｍをスパッタ装置にて堆積した後、フォトリソグラフィー法とドライエッチ法により所望のパターンにパターニングすることができる。 <Formation of gate electrode>
Next, as shown in FIG. 4A, the gate electrode 12 is formed on the substrate 11. The gate electrode 12 can be formed by depositing a conductive film on the substrate 11 by a sputtering method or the like and then patterning the conductive film using a photolithography process. As the conductive film, a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu), or an alloy thereof, or metal nitriding thereof A thing can be used suitably. Further, a plurality of these layers may be stacked. For example, after depositing W / TaN = 370 nm / 50 nm as a conductive film with a sputtering apparatus, it can be patterned into a desired pattern by a photolithography method and a dry etching method.
＜ゲート絶縁膜の成膜＞
　次に、図４Ｂに示すように、ゲート電極１２上にゲート絶縁膜１４を形成する。ゲート絶縁膜１４は例えば、ＣＶＤ法を用いて形成することができる。ゲート絶縁膜は、単層膜であっても複層膜であってもよい。ゲート絶縁膜は、酸化珪素（ＳｉＯｘ）、窒化珪素（ＳｉＮｘ）、酸化窒化珪素（ＳｉＯｘＮｙ）（ｘ＞ｙ）、窒化酸化珪素（ＳｉＮｘＯｙ）（ｘ＞ｙ）等を適宜用いることができる。なお、基板からの不純物等の拡散防止のため、下層側ゲート絶縁膜としては、窒化珪素（ＳｉＮｘ）、窒化酸化珪素（ＳｉＮｘＯｙ）（ｘ＞ｙ）等を用いて形成し、上層側ゲート絶縁膜としては、酸化珪素（ＳｉＯｘ）、酸化窒化珪素（ＳｉＯｘＮｙ）（ｘ＞ｙ）等を用いて形成することが望ましい。さらに低い成膜温度でゲートリーク電流の少ない緻密な絶縁膜を形成するには、アルゴンなどの希ガス元素を反応ガスに含ませて絶縁膜中に混入させるとよい。例えば、ゲート電極１２上にＳｉＮ層（３２５ｎｍ）、ＳｉＯ２層（５０ｎｍ）をＣＶＤ装置にて連続して堆積することができる。 <Deposition of gate insulating film>
Next, as shown in FIG. 4B, a gate insulating film 14 is formed on the gate electrode 12. The gate insulating film 14 can be formed using, for example, a CVD method. The gate insulating film may be a single layer film or a multilayer film. As the gate insulating film, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like can be used as appropriate. In order to prevent diffusion of impurities and the like from the substrate, the lower-layer side gate insulating film is formed using silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x> y) or the like, and the upper-layer side gate insulating film Is preferably formed using silicon oxide (SiOx), silicon oxynitride (SiOxNy) (x> y), or the like. In order to form a dense insulating film with little gate leakage current at a lower deposition temperature, a rare gas element such as argon is preferably contained in the reaction gas and mixed into the insulating film. For example, a SiN layer (325 nm) and a SiO 2 layer (50 nm) can be successively deposited on the gate electrode 12 using a CVD apparatus.
＜酸化物半導体層の形成＞
　次に、図４Ｃに示すように、ゲート絶縁膜１４上に酸化物半導体膜１５を形成する。酸化物半導体膜１５は、スパッタリング法やＣＶＤ法等により、ゲート絶縁膜１４上に酸化物半導体膜用薄膜を成膜した後、フォトリソグラフィプロセスを用いて酸化物半導体膜用薄膜をパターニングすることによって形成することができる。ここで、例えば、ゲート絶縁膜上に酸化物半導体膜をスパッタリング法により３０～１００ｎｍの厚さ堆積した後、フォトリソグラフィ工程でレジストマスクを用いてエッチングを行い、所望の形状にパターニングすることができる。 <Formation of oxide semiconductor layer>
Next, as illustrated in FIG. 4C, the oxide semiconductor film 15 is formed over the gate insulating film 14. The oxide semiconductor film 15 is formed by forming a thin film for an oxide semiconductor film on the gate insulating film 14 by sputtering or CVD, and then patterning the thin film for an oxide semiconductor film using a photolithography process. Can be formed. Here, for example, after an oxide semiconductor film is deposited to a thickness of 30 to 100 nm on the gate insulating film by a sputtering method, etching can be performed using a resist mask in a photolithography process, and the oxide semiconductor film can be patterned into a desired shape. .
　酸化物半導体層１５に含まれる酸化物半導体は、アモルファス酸化物半導体であってもよいし、結晶質部分を有する結晶質酸化物半導体であってもよい。結晶質酸化物半導体としては、多結晶酸化物半導体、微結晶酸化物半導体、ｃ軸が層面に概ね垂直に配向した結晶質酸化物半導体などが挙げられる。
　酸化物半導体層１５は、２層以上の積層構造を有していてもよい。酸化物半導体層１５が積層構造を有する場合には、酸化物半導体層１５は、非晶質酸化物半導体層と結晶質酸化物半導体層とを含んでいてもよい。あるいは、結晶構造の異なる複数の結晶質酸化物半導体層を含んでいてもよい。また、複数の非晶質酸化物半導体層を含んでいてもよい。酸化物半導体層１５が上層と下層とを含む２層構造を有する場合、上層に含まれる酸化物半導体のエネルギーギャップは、下層に含まれる酸化物半導体のエネルギーギャップよりも大きいことが好ましい。ただし、これらの層のエネルギーギャップの差が比較的小さい場合には、下層の酸化物半導体のエネルギーギャップが上層の酸化物半導体のエネルギーギャップよりも大きくてもよい。
　非晶質酸化物半導体および上記の各結晶質酸化物半導体の材料、構造、成膜方法、積層構造を有する酸化物半導体層の構成などは、例えば特開２０１４－００７３９９号公報に記載されている。参考のために、特開２０１４－００７３９９号公報の開示内容の全てを本明細書に援用する。 The oxide semiconductor included in the oxide semiconductor layer 15 may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface.
The oxide semiconductor layer 15 may have a stacked structure of two or more layers. In the case where the oxide semiconductor layer 15 has a stacked structure, the oxide semiconductor layer 15 may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, a plurality of crystalline oxide semiconductor layers having different crystal structures may be included. In addition, a plurality of amorphous oxide semiconductor layers may be included. In the case where the oxide semiconductor layer 15 has a two-layer structure including an upper layer and a lower layer, the energy gap of the oxide semiconductor included in the upper layer is preferably larger than the energy gap of the oxide semiconductor included in the lower layer. However, when the difference in energy gap between these layers is relatively small, the energy gap of the lower oxide semiconductor may be larger than the energy gap of the upper oxide semiconductor.
The material, structure, film forming method, and structure of an oxide semiconductor layer having a stacked structure of the amorphous oxide semiconductor and each crystalline oxide semiconductor described above are described in, for example, Japanese Patent Application Laid-Open No. 2014-007399. . For reference, the entire disclosure of Japanese Patent Application Laid-Open No. 2014-007399 is incorporated herein by reference.
　酸化物半導体層１５は、例えば、Ｉｎ、ＧａおよびＺｎのうち少なくとも１種の金属元素を含んでもよい。酸化物半導体層１５は、例えばＩｎ－Ｇａ－Ｚｎ－Ｏ系の半導体（以下、「Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体」と略する。さらに、「ＩＧＺＯ」と略することもある。）を含む。ここで、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体は、Ｉｎ（インジウム）、Ｇａ（ガリウム）、Ｚｎ（亜鉛）の三元系酸化物であって、Ｉｎ、ＧａおよびＺｎの割合（組成比）は特に限定されず、例えばＩｎ：Ｇａ：Ｚｎ＝２：２：１、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１、Ｉｎ：Ｇａ：Ｚｎ＝１：１：２等を含む。ここでは、酸化物半導体層は、Ｉｎ、Ｇａ、Ｚｎを、例えばＩｎ：Ｇａ：Ｚｎ＝１：１：１の割合で含むＩｎ－Ｇａ－Ｚｎ－Ｏ系半導体層であってもよい。 The oxide semiconductor layer 15 may include at least one metal element of In, Ga, and Zn, for example. The oxide semiconductor layer 15 is, for example, an In—Ga—Zn—O-based semiconductor (hereinafter, abbreviated as “In—Ga—Zn—O-based semiconductor”, and sometimes abbreviated as “IGZO”). Including. Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is It is not specifically limited, For example, In: Ga: Zn = 2: 2: 1, In: Ga: Zn = 1: 1: 1, In: Ga: Zn = 1: 1: 2, etc. are included. Here, the oxide semiconductor layer may be an In—Ga—Zn—O-based semiconductor layer containing In, Ga, and Zn at a ratio of In: Ga: Zn = 1: 1: 1, for example.
　Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体層を有するＴＦＴは、高い移動度（ａ－ＳｉＴＦＴに比べ２０倍超）および低いリーク電流（ａ－ＳｉＴＦＴに比べ１００分の１未満）を有しているので、駆動ＴＦＴおよび画素ＴＦＴとして好適に用いられる。Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体層を有するＴＦＴを用いれば、表示装置の消費電力を大幅に削減することが可能になる。 A TFT having an In—Ga—Zn—O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one hundredth of that of an a-Si TFT). It is suitably used as a drive TFT and a pixel TFT. When a TFT having an In—Ga—Zn—O-based semiconductor layer is used, power consumption of the display device can be significantly reduced.
　Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体は、アモルファスでもよいし、結晶質部分を有していてもよい。結晶質Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体としては、ｃ軸が層面に概ね垂直に配向した結晶質Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体が好ましい。このようなＩｎ－Ｇａ－Ｚｎ－Ｏ系半導体の結晶構造は、例えば、特開２０１２－１３４４７５号公報に開示されている。 The In—Ga—Zn—O based semiconductor may be amorphous or may have a crystalline part. As the crystalline In—Ga—Zn—O-based semiconductor, a crystalline In—Ga—Zn—O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable. Such a crystal structure of an In—Ga—Zn—O-based semiconductor is disclosed in, for example, Japanese Patent Laid-Open No. 2012-134475.
　酸化物半導体層は、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体の代わりに、他の酸化物半導体を含んでいてもよい。例えばＩｎ―Ｓｎ―Ｚｎ―Ｏ系半導体（例えばＩｎ２Ｏ３－ＳｎＯ２－ＺｎＯ）、Ｉｎ－Ａｌ－Ｚｎ－Ｏ系半導体、Ｚｎ－Ｏ系半導体（ＺｎＯ）、Ｉｎ－Ｚｎ－Ｏ系半導体（ＩＺＯ（登録商標））、Ｚｎ－Ｔｉ－Ｏ系半導体（ＺＴＯ）、Ｃｄ－Ｇｅ－Ｏ系半導体、Ｃｄ－Ｐｂ－Ｏ系半導体、ＩｎＧａＯ３（ＺｎＯ）５、酸化マグネシウム亜鉛（ＭｇｘＺｎ１－ｘＯ）、酸化カドミウム亜鉛（ＣｄｘＺｎ１－ｘＯ）、酸化カドニウム（ＣｄＯ）、Ｍｇ－Ｚｎ－Ｏ系半導体、Ｉｎ－Ｇａ－Ｓｎ－Ｏ系半導体等を含んでいてもよい。Ｚｎ－Ｏ系半導体としては、１族元素、１３族元素、１４族元素、１５族元素または１７族元素等のうち一種、または複数種の不純物元素が添加されたＺｎＯの非晶質（アモルファス）状態、多結晶状態または非晶質状態と多結晶状態が混在する微結晶状態のもの、または何も不純物元素が添加されていないものを用いることができる。 The oxide semiconductor layer may include another oxide semiconductor instead of the In—Ga—Zn—O-based semiconductor. For example, an In—Sn—Zn—O based semiconductor (eg, In 2 O 3 —SnO 2 —ZnO), an In—Al—Zn—O based semiconductor, a Zn—O based semiconductor (ZnO), an In—Zn—O based semiconductor ( IZO (registered trademark)), Zn—Ti—O based semiconductor (ZTO), Cd—Ge—O based semiconductor, Cd—Pb—O based semiconductor, InGaO 3 (ZnO) 5 , magnesium zinc oxide (Mg x Zn 1 − x O), cadmium zinc oxide (Cd x Zn 1-x O), cadmium oxide (CdO), Mg—Zn—O-based semiconductor, In—Ga—Sn—O-based semiconductor, and the like may be included. As the Zn—O-based semiconductor, ZnO is amorphous in which one or more impurity elements of Group 1 element, Group 13 element, Group 14 element, Group 15 element or Group 17 element are added. A state, a polycrystalline state, a microcrystalline state in which an amorphous state and a polycrystalline state are mixed, or a state in which no impurity element is added can be used.
＜電極用導電膜の形成（電極用導電膜成膜工程）＞
　次に、図４Ｄに示すように、酸化物半導体層１５及びゲート絶縁膜１４の全面にソース電極及びドレイン電極形成用の導電膜１６を形成する。導電層１６は、アルミニウム（Ａｌ）層を、Ａｌ以外の金属層で挟んだ積層構造である。アルミニウム（Ａｌ）層の上下に配置する、Ａｌ以外の金属層の材料としては、チタン（Ｔｉ)あるいはモリブデン（Ｍｏ）等の金属又はその合金、若しくはその金属窒化物を適宜用いることができる。導電層１６としては例えば、Ｔｉ層（５０ｎｍ）／Ａｌ層（３００ｎｍ）／Ｔｉ層（３０ｎｍ）をスパッタリングによって成膜することができる。 <Formation of Electrode Conductive Film (Electrode Conductive Film Forming Process)>
Next, as illustrated in FIG. 4D, a conductive film 16 for forming a source electrode and a drain electrode is formed on the entire surface of the oxide semiconductor layer 15 and the gate insulating film 14. The conductive layer 16 has a laminated structure in which an aluminum (Al) layer is sandwiched between metal layers other than Al. As a material of the metal layer other than Al disposed above and below the aluminum (Al) layer, a metal such as titanium (Ti) or molybdenum (Mo), an alloy thereof, or a metal nitride thereof can be used as appropriate. As the conductive layer 16, for example, a Ti layer (50 nm) / Al layer (300 nm) / Ti layer (30 nm) can be formed by sputtering.
＜電極用導電膜中のＡｌ層へのエネルギー付与（エネルギー付与工程）＞
　次に、図４Ｅに示すように、アルミニウム（Ａｌ）層を、Ａｌ以外の金属層で挟んだ積層構造である電極用導電膜中のＡｌ層へエネルギーを付与してＡｌ層の体積を縮小（シュリンク）させる。エネルギー付与の方法としてはＡｌ層の体積を縮小することができる方法であればよく、特に限定するわけではないが、例えば、金属のイオン注入、電子線の注入、希ガスのイオン注入、水素イオン注入などがある。金属のイオン注入を行う場合には、Ａｌ層の上に配置する金属層を透過し、Ａｌ層の下に配置する金属層に到達しない加速エネルギーでイオン注入し（例えば、１５０ｋｅＶ、１０１６個／ｃｍ２）、そのエネルギー付与によりＡｌ層を予め体積変化（シュリンク）させる。イオン注入の加速エネルギーとしては例えば、８０～２００ｋｅＶ、密度としては例えば、１０１５～１０１７個／ｃｍ２とすることができる。
　このとき、エネルギー付与のためのイオン注入金属元素としては、種々が可能であるが、アルミニウム（Ａｌ）は一般的に不純物元素を含むと電気伝導度が低下するため、アルミニウム（Ａｌ）が好ましい。
　また、例えば、Ｓ／Ｄ電極用導電膜の積層構造がＴｉ層／Ａｌ層／Ｔｉ層である場合、この基板を１００～２５０℃（例えば、２００℃）に加熱することが好ましい。これにより、Ａｌ層の下のＴｉ層と酸化物半導体層（例えば、ＩＧＺＯ層）が反応することなく、Ａｌ膜の体積変化が起こり易くなり、イオン注入量を少なくでき、プロセス時間を短縮できる。
　なお、この基板温度を３００℃とした場合には、Ａｌ層の下のＴｉ層と酸化物半導体層（例えば、ＩＧＺＯ層）とは反応して変質層を形成してしまう。 <Energy application to the Al layer in the electrode conductive film (energy application process)>
Next, as shown in FIG. 4E, energy is applied to the Al layer in the electrode conductive film having a laminated structure in which an aluminum (Al) layer is sandwiched between metal layers other than Al to reduce the volume of the Al layer ( Shrink). Any method can be used as long as it can reduce the volume of the Al layer. For example, metal ion implantation, electron beam implantation, rare gas ion implantation, hydrogen ion There are injections. In the case of performing ion implantation of metal, ion implantation is performed with acceleration energy that passes through the metal layer disposed on the Al layer and does not reach the metal layer disposed below the Al layer (for example, 150 keV, 10 16 / cm 2 ), and by applying the energy, the volume of the Al layer is changed (shrinked) in advance. The acceleration energy for ion implantation can be, for example, 80 to 200 keV, and the density can be, for example, 10 15 to 10 17 ions / cm 2 .
At this time, various ion-implanted metal elements for imparting energy can be used, but aluminum (Al) is preferable because aluminum (Al) generally includes an impurity element and thus the electrical conductivity is lowered.
For example, when the laminated structure of the conductive film for S / D electrodes is Ti layer / Al layer / Ti layer, it is preferable to heat this substrate to 100 to 250 ° C. (eg, 200 ° C.). Thereby, the Ti layer under the Al layer and the oxide semiconductor layer (for example, IGZO layer) do not react, so that the volume change of the Al film easily occurs, the ion implantation amount can be reduced, and the process time can be shortened.
Note that when the substrate temperature is set to 300 ° C., the Ti layer under the Al layer and the oxide semiconductor layer (for example, the IGZO layer) react to form a deteriorated layer.
＜ソース電極及びドレイン電極の形成（Ｓ／Ｄ電極形成工程）＞
　次に、図４Ｆに示すように、フォトリソグラフィ工程でレジストマスクを用いて電極用導電膜１６を所望の形状に加工し、ソース電極１６Ａ又はドレイン電極１６Ｂを形成する。 <Formation of source electrode and drain electrode (S / D electrode formation step)>
Next, as illustrated in FIG. 4F, the electrode conductive film 16 is processed into a desired shape using a resist mask in a photolithography process, thereby forming the source electrode 16A or the drain electrode 16B.
＜パッシベーション膜（Ｐａｓ膜、保護膜）の形成（パッシベーション膜形成工程）＞
　次に、図４Ｇに示すように、形成してきた構造の全体を覆うように、絶縁膜であるパッシベーション膜（Ｐａｓ膜）１７を形成する。パッシベーション膜の厚さとしては例えば、３００～５００ｎｍ程度形成する。この絶縁膜は、プラズマＣＶＤ法又はスパッタリング法などの薄膜形成法を用い、窒化珪素、酸化珪素、窒化酸化珪素、酸化窒化珪素等の絶縁性材料を用いて形成することができる。
　次いで、パッシベーション膜（Ｐａｓ膜）から酸素を拡散させることで、酸化物半導体膜中の酸素欠陥を減らすために、２００～４００℃程度の温度で０．５～２時間程度、アニールを行う。例えば、３５０℃、１時間とすることができる。
　なお、Ｓ／Ｄ電極形成のパターニングを行う前のＳ／Ｄ電極用導電膜で表面全体を覆った状態で、この酸化物半導体膜中の酸素欠陥を低減するためのアニールと同じ条件（例えば、３５０℃、１時間）でアニールを行うと、Ｓ／Ｄ電極用導電膜の最下層のＴｉ層やＭｏ層と酸化物半導体層とが反応し、チャネル領域の酸化物半導体層が変質することで、良好な特性のＴＦＴが得られない。本発明の一態様による方法では、適切なエネルギー範囲のイオン注入を行うことで、エネルギー付与される層をＳ／Ｄ電極用導電膜でのＡｌ層のみとすることが可能であり、そのため上記のようなＳ／Ｄ電極用導電膜の最下層のＴｉ層やＭｏ層と酸化物半導体層との反応は起こらない。 <Formation of Passivation Film (Pas Film, Protective Film) (Passivation Film Formation Step)>
Next, as shown in FIG. 4G, a passivation film (Pas film) 17 that is an insulating film is formed so as to cover the entire structure that has been formed. The thickness of the passivation film is, for example, about 300 to 500 nm. This insulating film can be formed using an insulating material such as silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxynitride using a thin film formation method such as a plasma CVD method or a sputtering method.
Next, annealing is performed at a temperature of about 200 to 400 ° C. for about 0.5 to 2 hours in order to reduce oxygen defects in the oxide semiconductor film by diffusing oxygen from the passivation film (Pas film). For example, it can be set to 350 ° C. for 1 hour.
In addition, in the state where the entire surface is covered with the conductive film for S / D electrode before patterning for S / D electrode formation, the same conditions as the annealing for reducing oxygen defects in the oxide semiconductor film (for example, When annealing is performed at 350 ° C. for 1 hour, the lowermost Ti layer or Mo layer of the S / D electrode conductive film reacts with the oxide semiconductor layer, and the oxide semiconductor layer in the channel region changes in quality. Therefore, a TFT having good characteristics cannot be obtained. In the method according to an embodiment of the present invention, by performing ion implantation in an appropriate energy range, the layer to which energy is applied can be only the Al layer in the conductive film for the S / D electrode. Such a reaction between the lowermost Ti layer or Mo layer of the S / D electrode conductive film and the oxide semiconductor layer does not occur.
　その後、パッシベーション膜（Ｐａｓ膜）上にフォトリソグラフィ工程でレジストマスクを形成し、コンタクトホール用のエッチングを行い、基板全面に対して熱処理を行う。
なおパッシベーション膜（Ｐａｓ膜）は単層に限らず、２層であってもよいし、３層以上であってもよいが、酸化物半導体層（例えば、ＩＧＺＯ膜）と接する膜には酸素が含まれることが好ましい。また、パッシベーション膜（Ｐａｓ膜）上に、有機絶縁材料から形成された平坦化膜をさらに形成してもよい。 Thereafter, a resist mask is formed on the passivation film (Pas film) by a photolithography process, etching for contact holes is performed, and heat treatment is performed on the entire surface of the substrate.
Note that the passivation film (Pas film) is not limited to a single layer, and may be two layers or three or more layers. However, the film in contact with the oxide semiconductor layer (for example, the IGZO film) contains oxygen. It is preferably included. Further, a planarizing film made of an organic insulating material may be further formed on the passivation film (Pas film).
＜共通電極形成＞
　次いで、パッシベーション膜（Ｐａｓ膜）が形成された基板表面全体に、例えばスパッタリング法によりＩＴＯやＩＺＯ膜等の透明導電膜を成膜した後に、その透明導電膜に対して、フォトリソグラフィ、ウエットエッチング及びレジストの剥離洗浄を行うことにより、透明電極を形成する。 <Common electrode formation>
Next, a transparent conductive film such as ITO or IZO film is formed on the entire surface of the substrate on which the passivation film (Pas film) is formed, for example, by sputtering, and then photolithography, wet etching, and A transparent electrode is formed by removing and cleaning the resist.
　この後は一般的な液晶表示装置の製造方法と同じく、対向基板との間に液晶層を挟んで保持する表示装置になる。 After this, as in a general method for manufacturing a liquid crystal display device, a display device is obtained in which a liquid crystal layer is sandwiched and held between a counter substrate.
　以下に本発明を実施例により説明するが、本発明はこれらの実施例に限定されるものではない。 Hereinafter, the present invention will be described by way of examples, but the present invention is not limited to these examples.
[実施例]
　基板としてガラス（旭硝子株式会社製ＡＮ１００）を用い、この基板上に、導電膜として、Ｗ（３７０ｎｍ）／ＴａＮ（５０ｎｍ）の積層膜をスパッタ装置にて堆積した後、フォトリソグラフィー法とドライエッチ法により所望のパターンに加工してゲート電極を形成した。
　次いで、ゲート電極上にＳｉＮ（３２５ｎｍ）、ＳｉＯ２（５０ｎｍ）をＣＶＤ装置にて連続して堆積してゲート絶縁膜を形成した。
　次いで、ゲート電極上にＩＧＺＯからなるチャネル層を形成した。
　次いで、Ｓ／Ｄ電極用導電膜として、Ｔｉ層（５０ｎｍ）／Ａｌ層（３００ｎｍ）／Ｔｉ層（３０ｎｍ）の３層積層構造をスパッタ装置によって成膜した。
　次いで、基板を２００℃にして、Ａｌイオン注入（１５０ｋｅＶ、１０１６個／ｃｍ２）を１時間行った。その後、Ｓ／Ｄ電極用導電膜をフォトリソグラフィー法とドライエッチ法により所望のパターンに加工してＳ／Ｄ電極を形成した。
　次いで、パッシベーション膜として、ＳｉＯ２（３００ｎｍ）／ＳｉＮ（３００ｎｍ）を堆積し、ＩＧＺＯからなるチャネル層中の酸素欠陥を低減するためのアニール（３５０℃、１時間）を行った。
　この後、有機平坦化膜を成膜し、更に共通電極としてＩＴＯ透明電極を形成して、チャネルエッチ型ＴＦＴを作製した。 [Example]
Glass (AN100 manufactured by Asahi Glass Co., Ltd.) is used as the substrate, and a laminated film of W (370 nm) / TaN (50 nm) is deposited as a conductive film on this substrate using a sputtering apparatus, and then a photolithography method and a dry etching method. To form a gate electrode by processing into a desired pattern.
Next, SiN (325 nm) and SiO 2 (50 nm) were successively deposited on the gate electrode by a CVD apparatus to form a gate insulating film.
Next, a channel layer made of IGZO was formed on the gate electrode.
Next, a three-layer laminated structure of Ti layer (50 nm) / Al layer (300 nm) / Ti layer (30 nm) was formed as a conductive film for S / D electrodes by a sputtering apparatus.
Next, the substrate was set to 200 ° C., and Al ion implantation (150 keV, 10 16 ions / cm 2 ) was performed for 1 hour. Thereafter, the S / D electrode conductive film was processed into a desired pattern by a photolithography method and a dry etching method to form an S / D electrode.
Next, SiO 2 (300 nm) / SiN (300 nm) was deposited as a passivation film, and annealing (350 ° C., 1 hour) was performed to reduce oxygen defects in the channel layer made of IGZO.
Thereafter, an organic flattening film was formed, and an ITO transparent electrode was further formed as a common electrode to produce a channel etch type TFT.
[比較例]
　比較例は、実施例と比較すると、Ａｌイオン注入工程を行わなかった点を除いて、実施例と同様にして、チャネルエッチ型ＴＦＴを作製した。 [Comparative example]
As compared with the example, the comparative example produced a channel etch type TFT in the same manner as the example except that the Al ion implantation step was not performed.
　図５Ａ～図５Ｃに、実施例及び比較例について、温度６０℃、湿度９５％の環境下に１５０時間置いた高温高湿信頼性試験を行う前後のＴＦＴ特性の結果を示す。
　図５Ａは、実施例について、高温高湿信頼性試験前のＴＦＴ特性の結果を示すものであり、図５Ｂは、比較例について、高温高湿信頼性試験後のＴＦＴ特性の結果を示すものであり、図５Ｃは、実施例について、高温高湿信頼性試験後のＴＦＴ特性の結果を示すものである。なお、比較例も、高温高湿信頼性試験前のＴＦＴ特性は図５Ａと同様であった。
　ＴＦＴサイズ（チャネルサイズ）は、長さ（Ｌ）及び幅（Ｗ）はそれぞれ、１０μｍ、４８０μｍである。
　また、ＴＦＴ特性測定は、セミオートプローバ(４１５６Ｃ)装置を使用して、室温で、ゲートスキャン電圧Ｖｇ=－１０～＋３０Ｖ、ドレインステップ電圧Ｖｄ=０．１，５，１０Ｖで行った。 5A to 5C show the results of TFT characteristics before and after conducting a high-temperature and high-humidity reliability test for 150 hours in an environment of a temperature of 60 ° C. and a humidity of 95% for the examples and comparative examples.
FIG. 5A shows the result of TFT characteristics before the high-temperature and high-humidity reliability test for the example, and FIG. 5B shows the result of TFT characteristics after the high-temperature and high-humidity reliability test for the comparative example. FIG. 5C shows the results of TFT characteristics after the high-temperature and high-humidity reliability test for the example. In the comparative example, the TFT characteristics before the high-temperature and high-humidity reliability test were the same as in FIG. 5A.
The TFT size (channel size) has a length (L) and a width (W) of 10 μm and 480 μm, respectively.
The TFT characteristics were measured using a semi-auto prober (4156C) at room temperature with a gate scan voltage Vg = −10 to +30 V and a drain step voltage Vd = 0.1, 5, 10 V.
　本発明の一態様による製造方法により製造されたＴＦＴは、高温高湿信頼性試験後もＴＦＴ特性に変化はなく、良好であった。一方、従来プロセスで製造されたＴＦＴは、高温高湿信頼性試験後、ＴＦＴ特性は悪化した。これは、Ｓ／Ｄ電極テーパー部のＡｌボイドによりＰａs膜に発生したクラックから水分が浸入したためと考えられる。 The TFT manufactured by the manufacturing method according to one embodiment of the present invention was good with no change in TFT characteristics even after the high temperature and high humidity reliability test. On the other hand, the TFT characteristics of the TFT manufactured by the conventional process deteriorated after the high temperature and high humidity reliability test. This is presumably because moisture entered from cracks generated in the Pas film due to Al voids in the tapered portion of the S / D electrode.
　本発明の一態様は、パッシベーション膜のＳ／Ｄ電極テーパー部の被覆性の悪化を低減することが必要なチャネルエッチ型薄膜トランジスタの製造方法などに適用することができる。 One embodiment of the present invention can be applied to a method for manufacturing a channel-etched thin film transistor in which it is necessary to reduce deterioration of the coverage of the S / D electrode taper portion of the passivation film.
　１０　薄膜トランジスタ（ＴＦＴ）
　１１　基板
　１２　ゲート電極
　１４　ゲート絶縁膜
　１５　チャネル層
　１６　電極用導電膜
　１６Ａ　ソース電極
　１６Ｂ　ドレイン電極
　１７　パッシベーション膜（保護膜） 10 Thin film transistor (TFT)
DESCRIPTION OF SYMBOLS 11 Substrate 12 Gate electrode 14 Gate insulating film 15 Channel layer 16 Electrode conductive film 16A Source electrode 16B Drain electrode 17 Passivation film (protective film)

Claims (4)

  1. 　ソース電極及びドレイン電極の少なくとも一方の電極が、Ａｌ以外の金属層／Ａｌ層／Ａｌ以外の金属層の積層構造からなり、かつ、酸化物半導体からなるチャネル層を有するチャネルエッチ型薄膜トランジスタの製造方法において、
    　ソース電極及びドレイン電極用の導電膜を成膜する工程と、
    　前記導電膜中のＡｌ層の体積を縮小させるようにエネルギーを付与する工程と、
    　前記導電膜をパターニングしてソース電極及びドレイン電極を形成する工程と、
    　パッシベーション膜を形成する工程と、有するチャネルエッチ型薄膜トランジスタの製造方法。     A method of manufacturing a channel etch type thin film transistor in which at least one of the source electrode and the drain electrode has a laminated structure of a metal layer other than Al / Al layer / a metal layer other than Al and has a channel layer made of an oxide semiconductor In
    Forming a conductive film for the source and drain electrodes;
    Applying energy so as to reduce the volume of the Al layer in the conductive film;
    Patterning the conductive film to form a source electrode and a drain electrode;
    A step of forming a passivation film, and a method of manufacturing a channel etch type thin film transistor.
  2. 　前記エネルギーを付与する工程は、金属イオン注入工程である請求項１に記載のチャネルエッチ型薄膜トランジスタの製造方法。 2. The method of manufacturing a channel etch type thin film transistor according to claim 1, wherein the step of applying energy is a metal ion implantation step.
  3. 　金属イオン注入工程は、基板温度を１００～２５０℃に加熱して行う請求項２に記載のチャネルエッチ型薄膜トランジスタの製造方法。 3. The method of manufacturing a channel-etched thin film transistor according to claim 2, wherein the metal ion implantation step is performed by heating the substrate temperature to 100 to 250 ° C.
  4. 　前記金属層がＴｉ又はＭｏのいずれかからなる請求項１～３のいずれか一項に記載のチャネルエッチ型薄膜トランジスタの製造方法。 The method for manufacturing a channel-etched thin film transistor according to any one of claims 1 to 3, wherein the metal layer is made of Ti or Mo.
PCT/JP2018/012407 2017-03-29 2018-03-27 Method for manufacturing channel-etch-type thin film transistor WO2018181296A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-064334 2017-03-29
JP2017064334 2017-03-29

Publications (1)

Publication Number Publication Date
WO2018181296A1 true WO2018181296A1 (en) 2018-10-04

Family

ID=63677436

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/012407 WO2018181296A1 (en) 2017-03-29 2018-03-27 Method for manufacturing channel-etch-type thin film transistor

Country Status (1)

Country Link
WO (1) WO2018181296A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007242848A (en) * 2006-03-08 2007-09-20 Mitsubishi Electric Corp Manufacturing method and treating apparatus for substrate
JP2015046613A (en) * 2009-12-04 2015-03-12 株式会社半導体エネルギー研究所 Semiconductor device
JP2015097272A (en) * 2009-12-04 2015-05-21 株式会社半導体エネルギー研究所 Semiconductor device
JP2015149489A (en) * 2008-09-01 2015-08-20 株式会社半導体エネルギー研究所 Oxide semiconductor film and semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007242848A (en) * 2006-03-08 2007-09-20 Mitsubishi Electric Corp Manufacturing method and treating apparatus for substrate
JP2015149489A (en) * 2008-09-01 2015-08-20 株式会社半導体エネルギー研究所 Oxide semiconductor film and semiconductor device
JP2015046613A (en) * 2009-12-04 2015-03-12 株式会社半導体エネルギー研究所 Semiconductor device
JP2015097272A (en) * 2009-12-04 2015-05-21 株式会社半導体エネルギー研究所 Semiconductor device

Similar Documents

Publication Publication Date Title
TWI496197B (en) Wiring structure
US10297694B2 (en) Semiconductor device and method for manufacturing same
TWI538210B (en) Semiconductor device and manufacturing method thereof
KR101175085B1 (en) Semiconductor device, liquid crystal display device equipped with semiconductor device, and process for production of semiconductor device
US20150295092A1 (en) Semiconductor device
WO2014020892A1 (en) Thin film transistor and method for manufacturing same
JP2004273614A (en) Semiconductor device and its fabricating process
KR20100027377A (en) Thin film transistor array substrate and method of fabricating the same
TW201005950A (en) Thin film transistor and method of manufacturing the same
CN110246900B (en) Semiconductor device and method for manufacturing the same
WO2018061969A1 (en) Semiconductor device and method for manufacturing same
KR20160073923A (en) Array Substrate For Thin Film Transistor
US9508544B2 (en) Semiconductor device and method for manufacturing same
US10593809B2 (en) Semiconductor device including oxide semiconductor thin-film transistor having multilayer structure oxide semiconductor layer
TW201626580A (en) Semiconductor device and manufacturing method thereof
WO2017018271A1 (en) Semiconductor device and method for manufacturing same
KR20140106042A (en) Thin film transistor substrate and method of manufacturing the same
US10332968B2 (en) Semiconductor device and method for manufacturing the same
US20190131322A1 (en) Method for manufacturing thin-film transistor and thin-film transistor
US10340390B2 (en) Semiconductor device and method for producing the same
US10700210B2 (en) Semiconductor device, and manufacturing method for same
WO2018181296A1 (en) Method for manufacturing channel-etch-type thin film transistor
TW201349507A (en) Semiconductor device and manufacturing method thereof
CN110808289A (en) Top gate Schottky oxide thin film transistor and preparation method thereof
US10164118B2 (en) Semiconductor device and method for producing same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18778143

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18778143

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP