JPS61185724A - Production for thin film transistor - Google Patents

Abstract

PURPOSE:To simplify the production process and improve the productivity by reducing the number of times of the use of a mask only two and reducing that of the mask alignment operation to one when individual layers constituting a thin film transistor TR are patterned after being laminated. CONSTITUTION:A gate electrode bar 11', a gate insulating film 12', a semiconductor film 13', and an electrode film 14' are laminated continuously on a glass substrate 10. Thereafter, a photoresist film 18 is applied, and first mask is used to perform exposure and development. This four-layered film is etched to be patterned. Next, the anodic oxidation of pattern edge parts of the Al film 11' to be the gate electrode bar is performed. A transparent electrode film 17 is accumulated on all of the surface including an electrode film 14, and a photoresist 19 is applied, and the second mask is used to perform exposure and development in accordance with shapes of a source electrode bar 16 and a drain electrode 17. The mask alignment operation is performed only once in this stage. The transparent electrode film 17 is formed by etching in accordance with the photoresist 19, and the source electrode bar 16 and the drain electrode 17 are patterned, and the electrode film 14 is etched.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a thin film transistor (TPT) that can be used in active materials, IJ socks liquid crystal display devices, etc.
The present invention relates to a manufacturing method.

<Summary of the Invention> The present invention aims to improve the yield by simplifying the mask alignment operation in the TPT manufacturing process.
It makes full use of unique technical means in the PT manufacturing process, and by incorporating pattern etching technology, lift-off method, and anodizing method of gate electrode members into the TPT patterning proscenium, TET can be manufactured with fewer mask alignment operations.
The purpose is to provide a manufacturing technology that can manufacture PT.

<Prior art> IJ socks liquid crystal display device (active polymer in which TFTs are arranged in a matrix on a display cell substrate) is a display device that enables high-quality, large-capacity display, and is actively being applied to televisions and other applications. It is.

Hereinafter, a method for manufacturing a TFT array substrate used in a conventional liquid crystal television will be described with reference to FIGS. 7(A) and 7(B). Figures 7(A) and 7(B) are schematic plan views of one pixel of a TFT array manufactured using three mask layers, and x
-x' sectional view. A metal film is deposited on a transparent insulating substrate (70) and patterned by photoetching to form a gate electrode bar (71) made of A1 or the like.

Next, a gate insulating film (72) made of an oxide film or a nitride film,
It is continuously laminated with a semiconductor film (73) made of Si, CdS, etc. Thereafter, the semiconductor film (73) is patterned by etching, and a transparent conductive film is deposited thereon. This transparent conductive film is etched to form a pattern of a source electrode (76) and a human train/display electrode (77). Through the above steps, a TFT for one picture element is manufactured.

<Problems to be Solved by the Invention> As described above, in the conventional TFT array substrate, since three layers of masks are used during etching, at least two mask alignment operations are required.

This results in problems such as a complicated manufacturing process, increased manufacturing cost, and decreased yield.

<Means for Solving the Problems> In view of the above-mentioned problems, the present invention uses a mask only twice when patterning is performed after laminating each layer constituting a TF'T. It is characterized by simplifying the manufacturing process and improving productivity by interposing an anodic oxidation method for the metal layer for the gate electrode and making the mask alignment operation into one diagram.

<Example> Figure 1 (A) (B? is the TF manufactured according to the present invention)
FIG. 2 is a schematic plan view and a cross-sectional view taken along line X-X′ of one picture element of the T-array substrate. The masks used are the gate electrode bar (11),
A gate insulating film (12), a semiconductor film (13), and an electrode film (1) forming an ohmic contact with the semiconductor film (13).
4) and a first mask for patterning the source electrode layer (16L drain electrode/display electrode (17) and the electrode film (14) forming ohmic contact with the semiconductor film (13)). There are only two layers in total, including the mask No. 2.Hereinafter, Fig. 2 (A) (B) to Fig. 7
The manufacturing process and specific structure of the TFT array will be described in detail with reference to the plan view and xx' cross-sectional view of each manufacturing process shown in FIGS.

O process I [see FIGS. 2(A) and 2(B)] First, an Al film (11 mm thick), which will become the gate electrode bar, is deposited on the glass substrate (10) by sputtering to a thickness of 200 OA.Next, plasma By CVD method, 5i3N4 (
12, amorphous hydrogenated silicon (a-
Si:H)(13').

Phosphorus-doped a-5i:H(n”a-Si
: H) (14') are laminated continuously. The film thickness is set to a certain degree. After forming these four layers, photoresist (18
) is applied, exposed and developed using the first mask.

Step 0 (see FIGS. 3(A) and 3(B)): The four-layer film obtained in step (2) above is etched and patterned. At this time, n'' a -S i : H(14') and a -S
i:H(13') etchant is HF and HN O3
Using a mixed solution of 5i3N4 (12mm etchant, use 5ΦHF aqueous solution. Also, A[film (11mm etchant) use H3PO4 aqueous solution. Each layer is treated with the substrate (10) in the order described above. Dip and etch the four layers in the same pattern.

0 process ■ [See Figure 4 (A) and (B)] In this process,
Anodizing is performed on the AI film (11 pattern edge portions) that will become gate electrode bars.

The purpose of this process is to form a source electrode bar, a drain electrode/display electrode, and a gate electrode bar (which will be patterned in the subsequent process V).
11) to prevent electrical continuity between the two. Al film (
The anodic oxidation of the pattern edge portion of the Al film (11') is carried out at a voltage of 40 V in an aqueous ammonium borate solution.
This is done by forming A1203 (15) on the edge of the pattern.

In this embodiment, AI is used as the gate electrode bar (11).
and use AJl'203(15) on the pattern edge.
However, as the gate electrode bar material, other so-called valve metals such as Ta, Nb, Hf, etc., which form an insulating film by anodic oxidation, can be used. However, in the case of Ta, in order to prevent damage to the glass substrate (10) during etching, prior to the deposition of Ta,
It may be necessary to deposit a Ta205 film.

0 Step IV [See Figures 5 (A) and (B) 3 Next, in order to form the source electrode bar and the drain electrode/display electrode, a transparent conductive film (17 mm) was deposited using a vacuum evaporation method.
:H (deposited to a thickness of about 3000A on the entire surface including the 14-layer surface. After that, photoresist (19) is applied and exposed and developed using a second mask to correspond to the shapes of the source electrode bar, drain electrode and display electrode. The mask alignment operation is performed only once in this process, so the operation is simple and greatly contributes to lowering the cost of the product.

O process V [see Figure 6 (A) and (B)] In this process,
A transparent conductive film (17') is formed by etching along the photoresist (18), and a source electrode bar (16) and a drain electrode/display electrode (17) are patterned and an ohmic contact is formed.na-5i :H(1
4') Etching is performed. In addition, the above transparent conductive film (1
7') Etchant is HC1 aqueous solution, na-3i:
A mixed solution of HF and HN 03 was used as the etchant for H(14').

In the above-mentioned order, each layer is immersed together with the substrate 10 in each eratint, and the transparent conductive film (17') is connected to the source electrode bar (16) and the drain electrode/display electrode! (17) Form a tube turn and a hissose/drain gap. In addition, an electrode film (14) for ohmic contact between the na-Si:H(14') and υa-5i:H semiconductor layer (13) and the source electrode bar (16) and the human train electrode (17) is formed.
) is molded.

0 process W photoresist) (19) is removed and Figure 1 (A) (B)
Fabricated as shown in .

Place the above TPT on the substrate (10), extend the gate electrode bar (11) and source electrode bar (16) in the row and column direction, and connect the gate electrode and source of each TPT in the same row and column. TFT by connecting electrodes in common
An array substrate is configured.

If this TFT array substrate is used as one cell substrate of a liquid crystal display device or the like, a large amount of display information can be generated as a clear image on the display screen.

<Effects of the Invention> As explained in detail above, in the present invention, TPT can be achieved with only a mask 2M.
The most troublesome mask alignment operation in manufacturing a TPT play substrate that can be manufactured can be reduced to one operation. Therefore, there is a great effect in reducing the cost and increasing the yield of the TFT array substrate.

[Brief explanation of the drawing]

FIGS. 1(A) and 1(B) are a plan view and a cross-sectional view taken along the line xx' of a TPT for explaining one embodiment of the present invention. Figure 2 (A) (B) to Figure 6 (A) (B) are the first
A plan view and x-x explaining the manufacturing process of TPT shown in the figure.
'Cross section] Bode. Figure 7 (A) (B) shows the conventional TP
FIG. 2 is a plan view and a cross-sectional view taken along line xx′ for explaining a T-array substrate. 10...Glass substrate 11...Gate electrode bar 1
2... Gate insulating film 13 Semiconductor layer 14... Electrode film 15... Anodic oxide film 16... Source electrode bar 17... Drain electrode and pixel electrode agent Patent attorney Aihiko Fukushi ( 2 others) (A) CB) (,4) (A) Figure 3 (A) Figure 4 (A) 1q (B) (A)

Claims (1)

[Scope of Claims] 1. A metal film serving as a gate electrode, a first insulating film serving as a gate insulating film, a semiconductor film, and an electrode film for forming an ohmic contact with the semiconductor film are successively formed on an insulating substrate. a step of stacking to form a four-layer film; a step of successively etching and patterning the four-layer film; a step of anodizing a pattern edge portion of the metal film to form a second insulating film; A step of depositing a transparent conductive film to become a source/drain electrode and a display electrode, and a step of successively etching the transparent conductive film and the electrode film in that order to separate them into a source electrode and a drain electrode. 1. A method of manufacturing a thin film transistor, characterized by comprising: