KR100939918B1 - Liquid crystal display panel and fabricating method thereof - Google Patents

Abstract

The present invention provides a liquid crystal display panel and a method of manufacturing the same, which can improve the crystallization efficiency of the active layer and can prevent a short circuit between the gate electrode and the source / drain electrode of the active layer.

The liquid crystal display panel according to the present invention has an active layer having a partially oxidized gate electrode, a source region and a drain region having a width less than or equal to the gate electrode, and insulated from each other with an oxidized region of the gate electrode and a gate insulating layer interposed therebetween. And a source electrode in contact with the source region of the active layer and a drain electrode in contact with the drain region of the active layer.

Description

Liquid crystal display panel and manufacturing method therefor {LIQUID CRYSTAL DISPLAY PANEL AND FABRICATING METHOD THEREOF}             

1 is a plan view illustrating a liquid crystal display panel having a conventional polysilicon thin film transistor.

FIG. 2 is a cross-sectional view illustrating the liquid crystal display panel taken along the line “II-II ′” in FIG. 1.

3A to 3F are cross-sectional views illustrating a method of manufacturing the liquid crystal display panel illustrated in FIG. 2.

FIG. 4 is a cross-sectional view of a liquid crystal display panel capable of preventing an open phenomenon of an active layer generated in a stepped portion of the gate electrode illustrated in FIG. 2.

5 is a plan view illustrating a liquid crystal display panel having a polysilicon thin film transistor according to the present invention.

FIG. 6 is a cross-sectional view illustrating the liquid crystal display panel taken along the line “VI-VI ′” in FIG. 5.

7 is a plan view and a cross-sectional view for explaining a first mask process according to the present invention.                 

FIG. 8 is a cross-sectional view for describing the first mask process illustrated in FIG. 7 in detail.

9 is a plan view and a cross-sectional view for explaining a second mask process according to the present invention.

10 is a plan view and a cross-sectional view for explaining a third mask process according to the present invention.

11 is a plan view and a cross-sectional view for explaining a fourth mask process according to the present invention.

12 is a plan view and a cross-sectional view for explaining a fifth mask process according to the present invention.

13 is a plan view and a cross-sectional view for explaining a sixth mask process according to the present invention.

<Description of Main Parts of Drawing>

2,102: Gate line 4,104: Data line

6,106: gate electrode 8,108: source electrode

10,110 drain electrode 12112 gate insulating film

14,114 active layer 16,116 buffer layer

18,118: protective film 20,120: contact hole

22,122: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device using polysilicon, and in particular, to improve the crystallization efficiency of the active layer and to prevent a short circuit between the gate electrode and the source / drain regions of the active layer, and a manufacturing method thereof. It is about.

In general, a liquid crystal display (LCD) displays an image corresponding to a video signal on a liquid crystal panel in which liquid crystal cells are arranged in a matrix by adjusting light transmittance of liquid crystal cells according to a video signal. In this case, a thin film transistor (TFT) is commonly used as a device for switching liquid crystal cells.

The thin film transistor used in the liquid crystal display device uses amorphous silicon or polysilicon as the semiconductor layer. The amorphous silicon thin film transistor has the advantage that the characteristics of the amorphous silicon film are relatively good and the characteristics are stable. However, the amorphous silicon thin film transistor has a disadvantage in that the response speed is low due to low charge mobility. Accordingly, the amorphous silicon thin film transistor has a disadvantage in that it is difficult to apply to a driving device of a high resolution display panel, a gate driver, and a data driver that require fast response speed.

The polysilicon thin film transistor is suitable for a high resolution display panel requiring fast response speed due to high charge mobility, and has the advantage of embedding peripheral driving circuits in the display panel. Accordingly, liquid crystal displays using polysilicon thin film transistors have emerged.

1 and 2 are a plan view and a cross-sectional view of a liquid crystal display panel having a conventional polysilicon thin film transistor.

Referring to FIGS. 1 and 2, a liquid crystal display panel having a conventional polysilicon thin film transistor is formed to intersect with a gate line 2 and a gate line 2 and a gate insulating layer 12 interposed therebetween. Pixels formed in the pixel region defined by the intersection of the line 4, the gate line 2 and the data line 4 with the TFT 30 and the gate line 2 and the data line 4, respectively. An electrode 22 is provided.

The gate line 2 supplies a gate signal to the gate electrode 6 of the thin film transistor 30.

The data line 4 supplies the pixel signal to the pixel electrode 22 through the drain electrode 10 of the thin film transistor 30.

The TFT 30 has a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a contact hole penetrating through the pixel electrode 22 and the passivation layer 18. A drain electrode 10 connected through 20 is provided.

 The gate electrode 6 is formed on the buffer film 16 and overlaps the channel region 14C of the active layer with the gate insulating film interposed therebetween. The source electrode 8 is formed to be insulated with the gate electrode 6 and the gate insulating film 12 interposed therebetween so as to be in direct contact with the source region 14S of the active layer. The drain electrode 10 is formed to be insulated with the gate electrode 6 and the gate insulating film 26 interposed therebetween, so that the drain electrode 10 is in direct contact with the drain region 14D of the active layer. Here, the ions implanted into the active layer 14 vary depending on the channel of the TFT 30. That is, when the TFT 30 is an N channel, at least one of n + and n− ions is implanted into the active layer. The active layer implanted with n- ions becomes an LED region to reduce a relatively high off current, and the active layer implanted with n + ions becomes a source region and a drain region, and the active layer without implantation of n-, n + ions Becomes the channel region. When the TFT 30 is a P channel, p + ions are implanted into the active layer. The active layer implanted with p + ions becomes a source region and a drain region, and the active layer without implanted p + ions becomes a channel region.

This TFT 30 causes the liquid crystal cell to charge the video signal from the data line 4, that is, the pixel signal, in response to the scan pulse from the gate line 2. Accordingly, the liquid crystal cell adjusts the light transmittance according to the charged pixel signal.

The pixel electrode 22 is connected to the drain electrode 10 of the TFT 30 through the contact hole 20 penetrating the protective film 18 and is formed in the pixel region.

Accordingly, an electric field is formed between the pixel electrode 22 supplied with the pixel signal through the TFT 30 and the common electrode (not shown). This electric field causes the liquid crystal molecules to rotate by dielectric anisotropy. According to the degree of rotation of the liquid crystal molecules, the light transmittance passing through the pixel region is changed, thereby realizing an image.

3A to 3F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device using a conventional polysilicon thin film transistor.                         

First, the buffer layer 16 is formed as shown in FIG. 3A by entirely depositing an insulating material such as SiO ₂ on the lower substrate 1. After the gate metal layer is entirely deposited on the lower substrate 1 on which the buffer layer 16 is formed, the gate electrode 6 is formed by patterning the gate metal layer by an etching process and a photolithography process including an exposure and development process. . Here, an aluminum-based metal including aluminum (Al), aluminum / nedium (Al / Nd), or the like is used as the gate metal layer.

As the insulating material of SiO ₂ is deposited on the lower substrate 1 on which the gate electrode 6 is formed, the gate insulating film 12 is formed as shown in FIG. 3B. After the amorphous silicon film is deposited on the lower substrate 1 on which the gate insulating film 12 is formed, the amorphous silicon film is crystallized by a laser to become a polysilicon film. The polysilicon film is patterned by a photolithography process and an etching process including an exposure and development process to form an active layer 14.

After the photoresist is entirely deposited on the lower substrate 1 on which the active layer 14 is formed, the photoresist is patterned by a photolithography process including an exposure and development process, thereby forming a photoresist pattern. By using the photoresist pattern as a mask, predetermined impurity ions are implanted into regions other than the channel region 14C of the active layer, thereby forming the source region 14S and the drain region 14D of the active layer, as shown in FIG. 3C. do.

In the case of the N-type TFT, n + ions are implanted into the active layer using a first photoresist pattern as a mask, and n-ions are implanted into the active layer using a second photoresist pattern having a narrower width than the first photoresist pattern. do. Accordingly, in the active layer of the N-type TFT, the region where n + and n-ions are not implanted is a channel region, the region where n-ions are implanted is an LDD region, and the region implanted with n + ions is a source region and a drain. It becomes an area.

In the case of the P-type TFT, p + ions are implanted into the active layer using the third photoresist pattern as a mask. Accordingly, in the active layer of the P-type TFT, the region where p + ions are not implanted is a channel region, and the region where p + ions are implanted is a source region and a drain region.

Photolithography and etching including the exposure and development processes after the data metal layer is entirely deposited on the lower substrate 1 on which the active layer including the channel region 14C, the source region 14S, and the drain region 14D is formed. The data metal layer is patterned by the process to form the data line 4, the source electrode 8, and the drain electrode 10 as shown in FIG. 3D.

An insulating material is deposited on the lower substrate 1 on which the data line 4, the source electrode 8, and the drain electrode 10 are formed to form a protective film 18 as shown in FIG. 3E. Thereafter, the protective film 18 is patterned by a photolithography process and an etching process including an exposure and development process to form a contact hole 20 exposing the drain electrode 10.

After the transparent conductive material is entirely deposited on the lower substrate 1 on which the protective film 18 is formed, the transparent conductive material is patterned by an etching process and a photolithography process including an exposure and development process, as shown in FIG. 3F. The pixel electrode 22 is formed. The pixel electrode 22 is electrically connected to the drain electrode 10 through the contact hole 20.

In the amorphous silicon film formed on the gate electrode 6 and the stepped gate insulating film 12 of the conventional TFT, the amorphous silicon film turns into a liquid state in a crystallization process by a laser and flows to a stepped portion, or an active phenomenon occurs due to lifting. There is a problem that the opening of layer 14 occurs.

In order to solve this problem, as shown in FIG. 4, the width of the gate electrode 6 is relatively wide, and the active layer 14 is formed on the gate insulating film 12 to overlap the plane of the gate electrode 6. The source electrode 8 and the drain electrode 10 are formed. In this case, since there is no active layer on the stepped portion of the gate electrode 6, the open phenomenon of the active layer 6 by the crystallization process is prevented. However, when the thickness of the gate insulating film 12 is relatively thin, the gate electrode 6 and the source region 14S of the active layer; A short phenomenon occurs between the gate electrode 6 and the drain region 14D of the active layer, and a short phenomenon occurs between the gate electrode 6 and the source 8 and the drain electrode 10. A gate electrode 6 and a source electrode 8; The capacitance of the parasitic capacitors Cgs and Cgd between the gate electrode 6 and the drain electrode 10 increases, which causes a problem of deterioration of the TFT characteristics.

Accordingly, an object of the present invention is to provide a liquid crystal display panel and a method of manufacturing the same, which can improve the crystallization efficiency of the active layer and can prevent a short circuit between the gate electrode and the source / drain regions of the active layer.

In order to achieve the above object, the liquid crystal display panel according to the present invention has a partially oxidized gate electrode, a source having a width less than the gate electrode, and a source overlapping the oxidized region of the gate electrode with the gate insulating film interposed therebetween. And an active layer having a region and a drain region, a source electrode in contact with a source region of the active layer, and a drain electrode in contact with a drain region of the active layer.

The gate electrode may include an oxide layer overlapping the source region and the drain region of the active layer to be insulated, and a gate layer overlapping the channel region of the active layer.

The oxide layer is formed using at least one of O ₂ and UV.

The liquid crystal display panel may further include a pixel electrode in contact with the drain electrode.

The active layer is characterized in that the polysilicon.

In order to achieve the above object, a method of manufacturing a liquid crystal display panel according to the present invention comprises the steps of forming a partially oxidized gate electrode on a substrate, forming a gate insulating film on the substrate on which the gate electrode is formed; Forming an active layer on the gate insulating layer, the active layer including a source region and a drain region having a width less than the gate electrode and overlapping the oxidized region of the gate electrode, a source electrode in contact with the source region of the active layer; And forming a drain electrode in contact with the drain region of the active layer.

The forming of the partially oxidized gate electrode may include forming a gate metal layer on the substrate, forming a stepped photoresist pattern on the gate metal layer, and patterning the metal layer using the photoresist pattern. And exposing the metal layer overlapping the source region and the drain region by ashing the photoresist pattern, and oxidizing the exposed gate metal layer.

Oxidizing the gate metal layer comprises oxidizing the gate metal layer using at least one of O ₂ and UV in the exposed gate metal layer.

The active layer is characterized in that the polysilicon.

The manufacturing method of the liquid crystal display panel may include forming a passivation layer exposing the drain electrode, and forming a pixel electrode on the passivation layer in contact with the drain electrode.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 13.

FIG. 5 is a plan view illustrating a liquid crystal display panel using a polysilicon thin film transistor according to the present invention, and FIG. 6 is a cross-sectional view illustrating a liquid crystal display panel taken along the line “VI-VI ′” in FIG. 5.

5 and 6, a liquid crystal display panel according to the present invention includes a data line 104 formed to cross a gate line 102, a gate line 102 and a gate insulating layer 112 therebetween; A TFT 130 positioned at an intersection of the gate line 102 and the data line 104, and a pixel electrode 122 formed in the pixel region defined by the intersection of the gate line 102 and the data line 104. do.

The gate line 102 supplies a gate signal to the gate electrode 106 of the thin film transistor 130.

The data line 104 supplies the pixel signal to the pixel electrode 122 through the drain electrode 110 of the thin film transistor 130.

The TFT 130 includes pixels through a gate electrode 106 connected to the gate line 102, a source electrode 108 connected to the data line 104, and a contact hole 120 penetrating through the passivation layer 118. A drain electrode 110 is connected to the electrode 122.

The gate electrode 106 is formed on the buffer layer 116 so as to overlap the active layer 114 with the gate insulating layer 112 therebetween. The gate electrode 106 includes a gate layer 126 overlapping the channel region 114C of the active layer, and an oxide layer 128 overlapping the source region 114S and the drain region 114D of the active layer.

The gate layer 126 is formed to have a width similar to that of the conventional gate electrode shown in FIGS. 1 and 2. The gate layer 126 and the source electrode 108; Since the distance between the gate layer 126 and the drain electrode 110 is similar to the conventional, the capacitance value of the parasitic capacitor formed between them is similar to the conventional. Accordingly, the TFT characteristic change can be prevented.

The oxide layer 128 is formed to have a relatively wide width to surround the source region 114S and the drain region 114D of the active layer. Accordingly, since the active layer 114 is not formed on the stepped region of the gate electrode 106, the open phenomenon of the active layer 114 can be prevented.

The source electrode 108 is formed to overlap the oxide layer 128 of the gate electrode 106 with the gate insulating film 112 interposed therebetween, and is in direct contact with the source region 114S of the active layer. The drain electrode 110 is formed to overlap the oxide layer 128 of the gate electrode 106 with the gate insulating film 126 interposed therebetween, and directly contacts the drain region 114D of the active layer. Here, the ions implanted into the active layer 114 vary depending on the channel of the TFT 130. That is, when the TFT 130 is an N channel, at least one of n + and n− ions is implanted into the active layer. The active layer implanted with n- ions becomes an LED region to reduce a relatively high off current, and the active layer implanted with n + ions becomes a source region and a drain region, and the active layer without implantation of n-, n + ions Becomes the channel region. When the TFT 130 is a P channel, p + ions are implanted into the active layer. The active layer implanted with p + ions becomes a source region and a drain region, and the active layer without implanted p + ions becomes a channel region.

The TFT 130 causes the liquid crystal cell to charge the video signal, that is, the pixel signal, from the data line 104 in response to the scan pulse from the gate line 102. Accordingly, the liquid crystal cell adjusts the light transmittance according to the charged pixel signal.

The pixel electrode 122 is connected to the drain electrode 110 of the TFT 130 through the contact hole 120 penetrating the passivation layer 118 and is formed in the pixel area.

Accordingly, an electric field is formed between the pixel electrode 122 supplied with the pixel signal through the TFT 130 and the common electrode (not shown). This electric field causes the liquid crystal molecules to rotate by dielectric anisotropy. According to the degree of rotation of the liquid crystal molecules, the light transmittance passing through the pixel region is changed, thereby realizing an image.

7 is a plan view and a cross-sectional view for explaining a first mask process of a liquid crystal display panel using a polysilicon thin film transistor according to the present invention in detail.

Referring to FIG. 7, a buffer layer 116 is formed on the lower substrate 101 through a deposition method such as PECVD or sputtering. As the material of the buffer film 116, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. The gate electrode 106 having the gate layer 126 and the oxide layer 128 is formed on the buffer film 116. The process of forming the gate electrode 106 is described in detail with reference to FIGS. 8A to 8E as follows.

The gate metal layer 160 is deposited on the buffer layer 116 through a deposition method such as sputtering as shown in FIG. 8A. Here, the gate metal layer 160 is an aluminum metal. Then, after the photoresist 158 is entirely deposited on the gate metal layer 160, the partial exposure mask 150 is aligned on the lower substrate 101. The partial exposure mask 150 may include a mask substrate 152 formed of a transparent material and having an exposed area forming an exposure area S1, a blocking part 154 formed in a blocking area S3 of the mask substrate 152, The diffraction exposure part 156 (or semi-transmissive part) formed in the partial exposure area S2 of the mask substrate 152 is provided. The photoresist film using the partial exposure mask 150 is exposed and then developed to correspond to the blocking portion 154 and the diffraction exposure portion 156 of the partial exposure mask 150 as shown in FIG. 8B. In step S3 and the partial exposure area S2, a photoresist pattern 162 having a step is formed. That is, the photoresist pattern 162 formed in the partial exposure region S2 has a second height lower than the photoresist pattern 162 having the first height formed in the blocking region S3.

The gate metal layer 160 is patterned by a wet etching process using the photoresist pattern 162 as a mask to form the gate electrode 106 as shown in FIG. 8C.

Subsequently, the photoresist pattern 162 having the second height in the partial exposure area S2 is removed by an ashing process using plasma, and the first height is removed in the blocking area S3 as illustrated in FIG. 8D. The photoresist pattern 162 has a state in which the height is lowered. The exposed gate electrode 106 is oxidized using the photoresist pattern 162. That is, the gate electrode 106 is oxidized by irradiating at least one of O ₂ and UV to the exposed gate electrode 106 as shown in FIG. 8D. Accordingly, the gate electrode 106 is partially oxidized as shown in FIG. 8E to be divided into the oxide layer 128 and the gate layer 126. The gate layer 126 overlaps with the photoresist pattern 162 and is not oxidized, and the oxide layer 128 is oxidized without overlapping with the photoresist pattern 162. Then, the photoresist pattern 162 remaining on the gate layer 126 of the gate electrode 106 is removed by a strip process.

9 is a plan view and a cross-sectional view for explaining in detail the second mask process of the liquid crystal display panel using a polysilicon thin film transistor according to the present invention.

Referring to FIG. 9, a gate insulating film 112 is formed by depositing an insulating material of SiO ₂ on the lower substrate 101 on which the gate electrode 106 is formed. After the amorphous silicon film is deposited on the lower substrate 101 on which the gate insulating film 112 is formed, the amorphous silicon film is crystallized by a laser to become a polysilicon film. The polysilicon film is patterned by a photolithography process and an etching process including an exposure and development process to form an active layer 114. In this case, the active layer is formed in the region overlapping with the gate electrode 106 on the gate insulating film 112.

10 is a plan view and a cross-sectional view for explaining a third mask process of a liquid crystal display panel using a polysilicon thin film transistor according to the present invention in detail.

After the photoresist is entirely deposited on the lower substrate 101 on which the active layer 114 is formed, the photoresist is patterned by a photolithography process including an exposure and development process to form a photoresist pattern. Using this photoresist pattern as a mask, predetermined impurity ions are implanted into regions other than the region overlapping with the gate layer of the gate electrode. Accordingly, the region into which the predetermined impurity ions are implanted is formed of the source region 114S and the drain region 114D of the active layer, and the region from which the impurity ions are not implanted is formed of the channel region 114C.

In the case of the N-type TFT, n + is implanted into the active layer using a photoresist pattern as a mask, and n-ion is implanted into the active layer using a photoresist pattern having a narrower width than the photoresist pattern. Accordingly, in the active layer of the N-type TFT, the region where n + and n-ions are not implanted is a channel region, the region where n-ions are implanted is an LDD region, and the region implanted with n + ions is a source region and a drain. It becomes an area.

In the case of the P-type TFT, p + ions are implanted into the active layer using the photoresist pattern as a mask. Accordingly, in the active layer of the P-type TFT, the region where p + ions are not implanted is a channel region, and the region where p + ions are implanted is a source region and a drain region.

11 is a plan view and a cross-sectional view for describing a fourth mask process of a liquid crystal display panel using a polysilicon thin film transistor according to the present invention in detail.

Referring to FIG. 11, the source electrode 108 and the drain electrode 110 are formed on the lower substrate 101 on which the active layer 114 is formed by a fourth mask process.

In detail, the data metal layer is entirely deposited on the lower substrate 101 on which the active layer is formed through a deposition method such as sputtering. After the photoresist is entirely deposited on the data metal layer, the photoresist is patterned by a photolithography process using a fourth mask to form a photoresist pattern. The data metal layer is patterned by an etching process using the photoresist pattern as a mask to form the source electrode 108 and the drain electrode 110. The source electrode 108 and the drain electrode 110 are in direct contact with the source region 114S and the drain region 114D of the active layer.

12 is a plan view and a cross-sectional view for describing a fifth mask process of a liquid crystal display panel using a polysilicon thin film transistor according to the present invention in detail.                     

Referring to FIG. 12, the passivation layer 118 having the pixel contact hole 120 is formed on the lower substrate 101 on which the source electrode 108 and the drain electrode 110 are formed by using a fifth mask process.

In detail, the passivation layer 118 is formed by depositing an insulating material on the lower substrate 101 on which the source electrode 108 and the drain electrode 110 are formed by a deposition method such as PECVD or sputtering. The protective film 118 may be formed of an inorganic insulating material or an organic insulating material including SiO ₂ , SiNx, or the like. A photoresist is deposited on the lower substrate 101 on which the passivation layer 118 is formed. Thereafter, the photoresist is patterned by a photolithography process using a fifth mask to form a photoresist pattern. The protective layer 118 is patterned by an etching process using the photoresist pattern as a mask to form a contact hole 120 exposing the drain electrode 110.

FIG. 13 is a plan view and a cross-sectional view for describing a sixth mask process of a liquid crystal display panel using a polysilicon thin film transistor according to the present invention in detail.

Referring to FIG. 13, a pixel electrode 122 positioned on the image display unit is formed on the lower substrate 101 on which the passivation layer 118 is formed using the sixth mask process.

In detail, the transparent conductive material and the photoresist are sequentially deposited on the lower substrate 101 on which the protective film 118 is formed through a deposition method such as sputtering. The transparent conductive material may be any one of indium tin oxide, indium zinc oxide, and indium tin zinc oxide. Thereafter, the photoresist is patterned by a photolithography process using a mask to form a photoresist pattern. The transparent metal layer is patterned by an etching process using the photoresist pattern as a mask to form the pixel electrode 122. The pixel electrode 122 is formed through the pixel contact hole 120 to contact the drain electrode 110 of the N-type TFT positioned in the image display unit.

On the other hand, the active layer according to the present invention; The data pattern including the source electrode and the drain electrode may be formed using the same mask. That is, after implanting impurity ions into the active layer to form a source region, a drain region, and a channel region, depositing a data metal layer on the active layer, and simultaneously patterning the active layer and the data metal layer using a diffraction mask or a semi-transmissive mask. Done. Accordingly, the source electrode and the drain electrode; It is possible to form an active layer formed along them below these.

As described above, the liquid crystal display and the method of manufacturing the same according to the present invention oxidize the gate electrode overlapping the source region and the drain region of the active layer. Accordingly, the gate electrode and the source electrode; It is possible to prevent the fluctuation of the parasitic capacitor capacitance value between the gate electrode and the drain electrode. In addition, a short phenomenon between the gate electrode, the source region and the drain region of the active layer can be prevented, and a short phenomenon between the gate electrode, the source electrode and the drain electrode can be prevented. In addition, since the gate electrode and the active layer are completely overlapped, it is possible to prevent the open phenomenon of the active layer overlapping at the stepped portion of the conventional gate electrode.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A gate electrode comprising a gate layer and an oxide layer in contact with a side of the gate layer; An active layer having a source region and a drain region on the gate electrode; A source electrode in contact with the source region of the active layer; And A drain electrode in contact with the drain region of the active layer, The area of the bottom surface of the active layer is smaller than the area of the upper surface of the gate electrode. The method of claim 1, And the oxide layer is insulated from the source region and the drain region of the active layer, and the gate layer is insulated from the channel region of the active layer. The method of claim 2, The oxide layer is formed using O ₂ or UV. The method of claim 1, And a pixel electrode in contact with the drain electrode. The method of claim 1, And the active layer is made of polysilicon. Forming a gate electrode on the substrate, the gate electrode including a gate layer and an oxide layer in contact with a side of the gate layer; Forming a gate insulating film on the substrate on which the gate electrode is formed; Forming an active layer including a source region and a drain region on the gate insulating layer; And Forming a source electrode in contact with the source region of the active layer and a drain electrode in contact with the drain region of the active layer, The forming of the active layer may include forming an area of a bottom surface of the active layer smaller than an area of an upper surface of the gate electrode. The method of claim 6, Forming the gate electrode, Forming a gate metal layer on the substrate; Forming a stepped photoresist pattern on the gate metal layer; Patterning the gate metal layer using the photoresist pattern; Etching the photoresist pattern to expose the gate metal layer corresponding to the source and drain regions; And oxidizing the exposed gate metal layer. The method of claim 7, wherein Oxidizing the gate metal layer, And oxidizing the gate metal layer by using O ₂ or UV on the exposed gate metal layer. The method of claim 6, And the active layer is made of polysilicon. The method of claim 6, Forming a protective film exposing the drain electrode; And forming a pixel electrode in contact with the drain electrode on the passivation layer.

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