KR100989253B1 - Liquid crystal display panel and fabricating method thereof - Google Patents

Abstract

The present invention provides a liquid crystal display panel and a method of manufacturing the same that can simplify the process.

The liquid crystal display panel of the present invention comprises the steps of forming a storage lower electrode overlapping the first active layer of the thin film transistor, the second active layer of the storage capacitor, the second active layer on the substrate; Forming a gate insulating film on the substrate on which the storage lower electrode and the first and second active layers are formed; Forming a gate electrode and a storage upper electrode overlapping the storage lower electrode on the gate insulating layer; Forming an interlayer insulating film on a substrate on which the gate electrode and the storage upper electrode are formed; And forming a drain electrode connected to the storage lower electrode and a source electrode facing the drain electrode on the interlayer insulating layer.

Description

Liquid crystal display panel and manufacturing method therefor {LIQUID CRYSTAL DISPLAY PANEL AND FABRICATING METHOD THEREOF}             

1 is a plan view schematically illustrating a configuration of a conventional poly liquid crystal display device.

FIG. 2 is a plan view illustrating a lower array substrate including the image display unit and the driver illustrated in FIG. 1.

FIG. 3 is a cross-sectional view illustrating a lower array substrate taken along lines "III1-III1 '" and "III2-III2'" in FIG.

4A to 4I are cross-sectional views illustrating a method of manufacturing the lower array substrate illustrated in FIG. 3.

5 is a plan view illustrating a liquid crystal display panel according to a first exemplary embodiment of the present invention.

FIG. 6 is a cross-sectional view of the liquid crystal display panel taken along the lines "VI1-VI1" and "VI2-VI2 '" in FIG. 5.

7A and 7B are plan and cross-sectional views illustrating in detail a first mask process of a liquid crystal display panel according to the present invention.

8A to 8D are cross-sectional views illustrating in detail the first mask process illustrated in FIGS. 7A and 7B.                 

9A and 9B are plan and cross-sectional views illustrating in detail a second mask process of the liquid crystal display panel according to the present invention.

10A to 10C are cross-sectional views illustrating in detail the second mask process illustrated in FIGS. 9A and 9B.

11A and 11B are plan and cross-sectional views illustrating in detail a third mask process of the liquid crystal display panel according to the present invention.

12A to 12C are cross-sectional views for describing in detail the third mask process illustrated in FIGS. 11A and 11B.

13A and 13B are plan and cross-sectional views illustrating in detail a fourth mask process of a liquid crystal display panel according to the present invention.

14A to 14C are cross-sectional views illustrating in detail the fourth mask process illustrated in FIGS. 13A and 13B.

15A and 15B are plan and cross-sectional views illustrating a fifth mask process of the liquid crystal display panel according to the present invention in detail.

16A and 16B are plan and cross-sectional views illustrating a sixth mask process of a liquid crystal display panel according to the present invention in detail.

17A and 17B are plan and cross-sectional views illustrating a seventh mask process of a liquid crystal display panel according to the present invention in detail.

18A and 18B are plan and cross-sectional views illustrating in detail an eighth mask process of a liquid crystal display panel according to the present invention.                 

19 is a plan view illustrating a liquid crystal display panel according to a second exemplary embodiment of the present invention.

20A to 20D are plan and cross-sectional views illustrating in detail a first mask process of the liquid crystal display panel illustrated in FIG. 19.

<Description of Main Parts of Drawing>

1,101: substrate 2,102: gate line

4,104 data line 6,66,106,166 gate electrode

8,68,108,168 Source electrode 10,70,110,170 Drain electrode

12,112: gate insulating film 14,74,114,174: active layer

16,166: buffer layer 18,118: protective film

22,122: pixel electrode

The present invention relates to a liquid crystal display panel using polysilicon, and more particularly, to a liquid crystal display panel and a method of manufacturing the same which can simplify the process.

In general, a liquid crystal display (LCD) displays an image corresponding to a video signal on a liquid crystal panel in which liquid crystal cells are arranged in a matrix by adjusting the light transmittance of the liquid crystal cells according to the video signal. In this case, a thin film transistor (TFT) is commonly used as a device for switching liquid crystal cells.

The thin film transistor used in the liquid crystal display device uses amorphous silicon or polysilicon as the semiconductor layer. The amorphous silicon thin film transistor has the advantage that the characteristics of the amorphous silicon film are relatively good and the characteristics are stable. However, the amorphous silicon thin film transistor has a disadvantage in that the response speed is low due to low charge mobility. Accordingly, the amorphous silicon thin film transistor has a disadvantage in that it is difficult to apply to a driving device of a high resolution display panel, a gate driver, and a data driver that require fast response speed.

The polysilicon thin film transistor is suitable for a high resolution display panel requiring fast response speed due to high charge mobility, and has the advantage of embedding peripheral driving circuits in the display panel. Accordingly, liquid crystal displays using polysilicon thin film transistors have emerged.

1 is a plan view illustrating a liquid crystal display using a conventional polysilicon thin film transistor.

Referring to FIG. 1, a liquid crystal display using a conventional polysilicon thin film transistor includes an image display unit 96 including a pixel matrix, and a data driver 92 for driving data lines 4 of the image display unit 96. ) And a gate driver 94 for driving the gate lines 2 of the image display unit 96.                         

In the image display unit 96, liquid crystal cells LC are arranged in a matrix to display an image. Each of the liquid crystal cells LC is a switching element connected to the intersection of the gate line 2 and the data line 4 and is a thin film transistor using polysilicon implanted with N-type impurities. 30).

As shown in Figs. 2 and 3, the N-type TFT 30 of the image display portion includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, The drain electrode 10 is connected through the pixel contact hole 20 penetrating the pixel electrode 22 and the passivation layer 18.

The gate electrode 6 is formed to overlap the channel region 14C of the active layer formed on the buffer film 16 with the gate insulating film 12 interposed therebetween. The source electrode 8 is formed to be insulated with the gate electrode 6 and the interlayer insulating layer 26 interposed therebetween, so that the source electrode 8 contacts the source region 14S of the active layer implanted with n + ions through the source contact hole 24S. The drain electrode 14D is formed to be insulated with the gate electrode 6 and the interlayer insulating film 26 interposed therebetween, and contacts the drain region 14D and the drain contact hole 24D of the active layer to which n + ions are implanted. Herein, an LED having n-ion implanted between the channel region 14C and the drain region 14D, the channel region 14C, and the source region 14S of the active layer (hereinafter referred to as “LDD”) Region 14L is formed to reduce the relatively high off current.

The N-type TFT 30 causes the liquid crystal cell LC to charge the video signal from the data line 4, that is, the pixel signal, in response to the scan pulse from the gate line 2. Accordingly, the liquid crystal cell LC adjusts the light transmittance according to the charged pixel signal.                         

The storage capacitor 60 is connected to the pixel electrode 22 and has a story upper portion overlapping the storage lower electrode 50 in which PH 3 is injected into the active layer, and the story lower electrode 50 and the gate insulating layer 26 interposed therebetween. It consists of an electrode 52. The storage capacitor 60 allows the pixel signal charged in the pixel electrode 22 to remain stable until the next pixel signal is charged.

The gate driver 94 drives the gate lines 2 sequentially in the horizontal period for each frame by the gate control signals. The gate driver 94 sequentially turns on the thin film transistors in horizontal line units to connect the data line 4 to the liquid crystal cell.

The data driver 92 samples a plurality of digital data signals every horizontal period and converts them into analog data signals. The data driver 92 supplies an analog data signal to the data lines 4. Accordingly, the liquid crystal cells connected to the turned-on thin film transistors adjust the light transmittance in response to data signals from each of the data lines 4.

The gate driver 94 and the data driver 92 include a plurality of driving P-type TFTs 90 and driving N-type TFTs 80 connected in a CMOS structure as shown in FIGS. 2 and 3. In the driving P-type TFT 90, boron impurities are implanted into the source and drain regions 74S and 74D of the active layer. The driving N-type TFT 80 injects phosphorous or arsenic impurities into the source and drain regions 44S and 44D of the active layer. In addition, the driving N-type TFT 80 is provided with an LDD region 44L in order to reduce the high off-current compared with the driving P-type TFT 90.                         

Each of the driving N-type and P-type TFTs 80 and 90 has an active layer 44 and 74 formed on the lower substrate 1 with a buffer film 16 therebetween, and a gate insulating film 12 therebetween. Gate electrodes 36 and 66 formed to overlap the active layers 44 and 74, and source and drain electrodes 38 and 68 and insulated from the gate electrodes 36 and 66 and in contact with the active layer. 40,70).

4A to 4I are cross-sectional views illustrating a method of manufacturing a liquid crystal display device using a conventional polysilicon thin film transistor.

First, the buffer layer 16 is formed as shown in FIG. 4A by entirely depositing an insulating material such as SiO ₂ on the lower substrate 1. After the amorphous silicon film is deposited on the lower substrate 1 on which the buffer film 16 is formed, the amorphous silicon film is crystallized by a laser to become a polysilicon film, and the polysilicon film is subjected to a photolithography process and an etching process using a first mask. N-type TFTs patterned by the image TFTs of the image display unit and the N-type TFTs of the driving unit, the P-type TFTs of the driving unit (hereinafter referred to as " P-type TFTs &quot;), and the active capacitors 14 and 44 of the storage capacitors. An active pattern including 74 is formed.

After the photoresist is entirely deposited on the lower substrate 1 having the active pattern formed thereon, the photoresist is patterned by a photolithography process using a second mask to form a photoresist pattern. The photoresist pattern is formed to expose the active layer 44 of the storage capacitor and completely cover the active layers 14 and 74 of the N-type and P-type TFTs. Using the photoresist pattern as a mask, PH ₃ ions are implanted into the active layer 44 of the storage capacitor to form the storage lower electrode 50 as shown in FIG. 4B.

As the insulating material of SiO ₂ is deposited on the lower substrate 1 on which the storage lower electrode 50 is formed, the gate insulating layer 12 is formed as shown in FIG. 4C. After the gate metal layer is entirely deposited on the lower substrate 1 on which the gate insulating layer 12 is formed, the gate metal layer is patterned by a photolithography process and an etching process using a third mask, so that the gate electrodes of the N-type and P-type TFTs, respectively. (6,66) and the storage upper electrode 52 of the storage capacitor are formed. Here, an aluminum-based metal including aluminum (Al), aluminum / nedium (Al / Nd), or the like is used as the gate metal layer. By using the gate electrodes 6 and 66 as masks, n-ions are implanted into the active layers 14 and 74 of the N and P type TFTs, and the gate electrodes 6 and 66 of the N and P type TFTs The overlapping active layers 14 and 74 are channel regions 14C, 44C and 74C. The active layers 14 and 74 which do not overlap the gate electrodes 6 and 66 of the N-type and P-type TFTs are LDD regions. (14L, 74L).

Then, after the photoresist is entirely deposited on the lower substrate 1, the photoresist is patterned by a photolithography process using a fourth mask to form a photoresist pattern. The photoresist pattern partially exposes the active layer 14 of the N-type TFT and is formed to completely cover the upper storage electrode 52 of the storage capacitor and the active layer 74 of the P-type TFT. Using this photoresist pattern as a mask, n + ions are implanted into the active layer 14 of the N-type TFT, so as to show the source region 14S and the drain region 14D of the active layers 14 and 44 as shown in FIG. 4D. ) Is formed.

After the photoresist is entirely deposited on the lower substrate 1 having the active layer 14 implanted with n + ions, the photoresist is patterned by a photolithography process using a fifth mask to form a photoresist pattern. This photoresist pattern is formed so as to cover an area except for the active layer 74 of the P-type TFT. Using the photoresist pattern as a mask, p + ions are implanted into the active layer 74 of the P-type TFT so that the source region 74S and the drain region of the active layer 74 of the P-type TFT as shown in FIG. 74D) is formed.

As the insulating material is entirely deposited on the lower substrate 1 having the active layer 74 implanted with p + ions, an interlayer insulating layer 26 is formed as shown in FIG. 4F. Thereafter, the interlayer insulating film 26 and the gate insulating film 12 are patterned by a photolithography process and an etching process using a sixth mask. As a result, a source contact hole 24S and a drain contact hole 24D exposing the source region 14S and the drain region 14D of the N-type TFT, respectively, are formed, and the source region 74S and the drain of the P-type TFT are formed. Source contact holes 84S and drain contact holes 84D exposing regions 74D, respectively, are formed.

After the data metal layer is entirely deposited on the lower substrate 1 on which the source contact hole and the drain contact hole are formed, the data metal layer is patterned by a photolithography process and an etching process using a seventh mask. A data pattern is formed that includes the source and drain electrodes 8 and 10 of the type TFT and the source and drain electrodes 68 and 70 of the P type TFT. Each of the source and drain electrodes 8, 68, 10, and 70 included in the data pattern includes source regions 14S and 74S of the active layer through source contact holes 24S and 84S and drain contact holes 24D and 84D. It is in contact with the drain regions 14D and 74D.

As the insulating material is entirely deposited on the lower substrate 1 on which the data pattern is formed, the protective film 18 is formed as shown in FIG. 4H. Thereafter, the protective film 18 is patterned by a photolithography process and an etching process using an eighth mask to form a pixel contact hole 20 exposing the drain electrode 10 of the N-type TFT of the image display unit.

After the transparent conductive material is entirely deposited on the lower substrate 1 on which the protective layer 18 is formed, the transparent conductive material is patterned by a photolithography process and an etching process using a ninth mask, thereby as shown in FIG. 4I. (22) is formed. The pixel electrode 22 is electrically connected to the drain electrode 10 of the image TFT through the pixel contact hole 20.

As described above, the conventional manufacturing method of the liquid crystal display device having the polysilicon thin film transistor has a limitation in cost reduction due to the complicated manufacturing process by employing a 9 mask process. This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process. Accordingly, in recent years, a method of further simplifying the manufacturing process to further reduce the manufacturing cost is required.

Accordingly, an object of the present invention is to provide a liquid crystal display panel and a method of manufacturing the same that can simplify the process.

In order to achieve the above object, a method of manufacturing a liquid crystal display panel according to the present invention includes a first active layer 114 of a thin film transistor, a second active layer 144 of a storage capacitor, and a second active layer 144 on a substrate. Forming a storage lower electrode (150) overlapping with the entirety; Forming a gate insulating film on the substrate on which the storage lower electrode (150), the first active layer (114) and the second active layer (144) are formed; Forming a storage upper electrode 152 overlapping the gate electrode and the storage lower electrode 150 on the gate insulating layer; Forming an interlayer insulating film on a substrate on which the gate electrode and the storage upper electrode 152 are formed; And forming a drain electrode 110 connected to the storage lower electrode 150 and a source electrode 108 facing the drain electrode 110 on the interlayer insulating layer.

Forming the first active layer 114 of the thin film transistor, the second active layer 144 of the storage capacitor, and the storage lower electrode 150 overlapping the entirety of the second active layer 144 on the substrate may be formed. Sequentially depositing an active material and a metal material on the substrate, forming a stepped photoresist pattern on the metal material, and patterning the active material and the metal material by using the stepped photoresist pattern. And etching the stepped photoresist pattern, and etching the metal material in the region corresponding to the thin film transistor by using the ashed photoresist pattern. In addition, the stepped photoresist pattern is formed using the first mask 210 including three regions having different transmittances. The first mask including three regions having different transmittances may include a blocking portion 214 and a diffraction exposure portion 216 (or a semi-transmissive portion) formed to correspond to the blocking region S1 and the partial exposure region S3. And a portion corresponding to the exposure area S2.
The method of manufacturing the liquid crystal display panel may further include forming an insulating pattern 250 positioned between the second active layer 144 and the storage lower electrode 150.

delete

In the manufacturing method of the liquid crystal display panel, a first impurity is injected into the first active layer 114 using the gate electrode, and a second impurity is injected into the first active layer 114 into which the first impurity is injected. It characterized in that it further comprises the step of injecting.

The manufacturing method of the liquid crystal display panel may include forming a passivation layer to cover the source electrode 108 and the drain electrode 110; And forming a pixel electrode 122 connected to the drain electrode 110 on the passivation layer.

The storage lower electrode 150 is formed of a material containing a conductive metal.

In order to achieve the above object, the liquid crystal display panel according to the present invention is formed on the gate insulating film so as to be insulated from the first active layer 114 formed on the substrate, the first active layer 114 and the first active layer A gate electrode overlapping the channel region 114C of 114, and formed on the interlayer insulating layer so as to be insulated from the gate electrode, and connected to the source region 114S and the drain region 114D of the first active layer 114. A thin film transistor having a source electrode 108 and a drain electrode 110; A pixel electrode 122 connected to the drain electrode 110 of the thin film transistor; The second active layer 144 disposed on the same plane as the first active layer 114 and the storage lower electrode formed in the same pattern as the second active layer 144 and connected to the drain electrode 110 ( 150, a storage capacitor having a storage upper electrode 152 formed on the gate insulating layer so as to be insulated from and overlapped with the storage lower electrode 150.

The second active layer 144 and the storage lower electrode 150 are in contact with each other.

The liquid crystal display panel further includes an insulating pattern 250 formed between the second active layer 144 and the storage lower electrode 150.

The liquid crystal display panel further includes a contact hole 142 that exposes the storage lower electrode 150 through the interlayer insulating layer and the gate insulating layer so that the storage lower electrode 150 contacts the drain electrode 110. Characterized in that.

An LDD region is formed between the channel region 114C and the source region 114S of the first active layer 114 and between the channel region 114C and the drain region 114D of the first active layer 114. It is characterized by.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 20.

FIG. 5 is a plan view illustrating a liquid crystal display device using a polysilicon thin film transistor according to the present invention, and FIG. 6 is a view illustrating a liquid crystal display device taken along lines “VI1-VI1 ′” and “VI2-VI2 ′” in FIG. 5. It is sectional drawing to show.

5 and 6, a liquid crystal display using a polysilicon thin film transistor according to the present invention drives an image display unit 196 including a pixel matrix and data lines 104 of the image display unit 196. And a gate driver 194 for driving the gate lines 102 of the image display unit 196.                     

The image display unit 196 includes an insulated gate line 102 and a data line 104, an image TFT 130 positioned at an intersection of the gate line 102 and the data line 104, and a gate line ( And a pixel electrode 122 formed in an area defined by the intersection of the 102 and data lines 104 and connected to the N-type TFT 130.

The N-type TFT 130 of the image display unit includes a gate electrode 106 connected to the gate line 102, a source electrode 108 connected to the data line 104, a pixel electrode 122 and a protective film 118. And a drain electrode 110 connected through the pixel contact hole 120 penetrating the through hole. In addition, the N-type TFT 130 of the image display unit further includes a first active layer 114 that forms a channel between the source electrode 108 and the drain electrode 110 while overlapping the gate electrode 106 on the gate insulating film. Equipped. The first active layer 114 includes a channel region 114C overlapping the gate electrode 106, a source region 114S contacted through the source electrode 108 and the source contact hole 124S, and implanted with n + ions; And a drain region 114D contacted through the drain electrode 110 and the drain contact hole 124D and implanted with n + ions, a channel region 114C, a drain region 114D, a channel region 114C, and a source region ( LDD region 114L formed between 114S is included. Here, n-ion is implanted into the LDD 114L region to reduce a relatively high off current.

The N-type TFT 130 of such an image display portion causes the liquid crystal cell LC to charge the video signal from the data line 104, that is, the pixel signal, in response to the scan pulse from the gate line 102. Accordingly, the liquid crystal cell LC adjusts the light transmittance according to the charged pixel signal.

The storage capacitor 160 includes a storage lower electrode 150 connected to the drain electrode 110 and the storage contact hole 142 of the N-type TFT 130 of the image display unit positioned in the image display unit, and the storage lower electrode ( The upper portion of the story upper electrode 152 overlaps with the gate insulating layer 112 therebetween. Here, the storage lower electrode 150 is formed in the same pattern as the second active layer 144 and is electrically connected to the pixel electrode 122 through the drain electrode 110 of the image TFT 130. The storage capacitor 160 allows the pixel signal charged in the pixel electrode 122 to be stably maintained until the next pixel signal is charged.

The gate driver 194 sequentially drives the gate lines 102 by a horizontal period for each frame by the gate control signals. The gate driver 194 sequentially turns on the thin film transistors in horizontal line units to connect the data line 104 to the liquid crystal cell.

The data driver 192 samples a plurality of digital data signals every horizontal period and converts the digital data signals into analog data signals. The data driver 192 supplies an analog data signal to the data lines 104. Accordingly, the liquid crystal cells connected to the turned-on thin film transistors adjust light transmittance in response to data signals from each of the data lines 104.

The gate driver 194 and the data driver 192 include a plurality of driving P-type TFTs 190 and driving N-type TFTs 180 connected in a CMOS structure. In the driving P-type TFT 190, boron impurities are implanted into the source and drain regions 174S and 174D of the active layer. The driving N-type TFT 180 injects phosphorous or arsenic impurities into the source and drain regions 154S and 154D of the active layer. In addition, the driving N-type TFT 180 is provided with an LDD region 154L in order to reduce a high off current compared to the driving P-type TFT 190.

Each of the driving N-type and P-type TFTs 180 and 90 is active with the active layer 174 and 154 formed on the lower substrate 101 with the buffer film 106 interposed therebetween, and the gate insulating film 102 interposed therebetween. Gate electrodes 136 and 166 overlapping with the layers 174 and 154, and source electrodes 138 and 168 and drain electrodes 140 and 170 which are insulated from the gate electrodes 136 and 166 and are in contact with the active layer.

7A and 7B are a plan view and a cross-sectional view for describing in detail a first mask process of a liquid crystal display device using the polysilicon thin film transistor illustrated in FIG. 6.

7A and 7B, a buffer layer 116 is formed on the lower substrate 101 through a deposition method such as PECVD or sputtering. As the material of the buffer film 116, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. On the buffer film 116, a first active layer 114, a second active layer 144, and a third active layer 174 of each of the N-type TFT, the storage capacitor, and the P-type TFT are included in the first mask process. An active pattern; The storage lower electrode 150 of the same pattern as the second active layer 144 of the storage capacitor is formed. The first mask process will be described in detail with reference to FIGS. 8A to 8D as follows.

As shown in FIG. 8A, an amorphous silicon film is deposited on the buffer film 116 through a deposition method such as PECVD or sputtering. The amorphous silicon film is crystallized by a laser to form a polysilicon film 206. Subsequently, the storage metal layer 208 and the photoresist 218 are entirely formed on the polysilicon film 206. Here, the storage metal layer 208 may be a conductive metal, for example, a gate metal layer, a data metal layer, or a transparent conductive material.

Next, the first mask 210 is aligned on the lower substrate 101 on which the photoresist 218 is formed. The first mask 210 is formed of a transparent material, and a mask substrate 212 in which an exposed area forms an exposure area S2, a blocking part 214 formed in a blocking area S1 of the mask substrate 212, and The diffraction exposure part 216 (or semi-transmissive part) formed in the partial exposure area S3 of the mask substrate 212 is provided. By exposing and developing the photoresist film using the first mask 210, the blocking region S1 corresponds to the blocking portion 214 and the diffraction exposure portion 216 of the first mask 210 as illustrated in FIG. 8B. ) And the photoresist pattern 204 having a step in the partial exposure area S3 is formed. That is, the photoresist pattern 204 formed in the partial exposure region S3 has a second height lower than the photoresist pattern 204 having the first height formed in the blocking region S1.

The storage metal layer 208 is patterned by a wet etching process using the photoresist pattern 204 as a mask to form a storage pattern including the upper storage electrode 150. The polysilicon layer 206 is patterned by a dry etching process using the photoresist pattern 204 as a mask, so that the first active layer 114 and the second active layer 144 are formed along the storage pattern as shown in FIG. 8B. ) And a third active layer 174 are formed.

Subsequently, in the ashing process using an oxygen (O ₂ ) plasma, the photoresist pattern 204 having the second height in the partial exposure region S3 is removed as shown in FIG. 8C, and the blocking region S1 is removed. The photoresist pattern 204 having the first height is in a state where the height is lowered. The etching process using the photoresist pattern 204 removes the storage patterns of the partial exposure region S3, that is, the N-type and P-type TFT regions.

As shown in FIG. 8D, the photoresist pattern 204 remaining on the storage lower electrode 150 is removed by a strip process.

9A and 9B are a plan view and a cross-sectional view for explaining the second mask process of the present invention in detail.

9A and 9B, PECVD on the lower substrate 101 on which the first active layer 114, the second active layer 144, the third active layer 174, and the storage lower electrode 150 are formed is performed. The gate insulating film 112 is formed through a deposition method such as sputtering. As the gate insulating film 112, an inorganic insulating material or an organic insulating material such as SiO ₂ or SiNx is used. On the gate insulating film 112, a storage upper electrode 152 and gate electrodes 106 and 166 of N-type and P-type TFTs are formed in a second mask process, and the N-type TFT is formed using the gate electrodes 106 and 166 as masks. The first active layer 114 of and the third active layer 174 of the P-type TFT are divided into channel regions 114C and 174C and LED regions 114L and 174L. This will be described in detail with reference to FIGS. 10A to 10C.

First, a gate metal layer is deposited on the gate insulating film 112 by a deposition method such as sputtering. Here, the gate metal layer is an aluminum-based metal. Then, the gate metal layer is patterned by a photolithography process and an etching process using a second mask, so that the gate electrodes 106 and 166 of the N-type and P-type TFTs and the storage upper electrode 152 of the storage capacitor as shown in FIG. 10A. ) Is formed.

Then, using the gate electrodes 106 and 166 of the N-type and P-type TFTs as masks, as shown in FIG. 10B, the first active layer 114 of the N-type TFT and the third active layer 174 of the P-type TFT are shown. N- ions are implanted in the. Accordingly, as shown in FIG. 10C, the channel regions 114C and 174C and the LED regions 114L and 174L of the first active layer 114 of the N-type TFT and the third active layer 174 of the P-type TFT are formed. Is formed. The channel regions 114C and 174C of the first active layer 114 of the N-type TFT and the third active layer 174 of the P-type TFT overlap the gate electrodes 106 and 166, and the LED regions 114L and 174L Non-overlapping with the gate electrodes 106 and 166, n-ion is implanted.

11A and 11B are a plan view and a cross-sectional view for explaining the third mask process of the present invention in detail.

11A and 11B, the first active layer 114 of the N-type TFT divided into the LED region 114L and the channel region 114C is subjected to the LED region 114L and the channel region by a third mask process. 114C, the source region 114S, and the drain region 114D. This will be described in detail with reference to FIGS. 12A to 12C.

First, after the photoresist 226 is entirely deposited on the lower substrate 101 on which the gate electrodes 106 and 166 are formed, the third mask 220 is aligned on the lower substrate 101 as shown in FIG. 12A. The third mask 220 may be formed of a transparent material, and may include a mask substrate 222 having an exposed area forming an exposure area S2, and a blocking part 224 formed in the blocking area S1 of the mask substrate 222. Equipped. The photoresist 226 is patterned by the photolithography process using the third mask 220 to form the photoresist pattern 228 as shown in FIG. 12B. The photoresist pattern 228 is formed on the gate insulating film 112 so as not to overlap with the LED region 114L and part of the N-type TFT. By implanting n + ions into the LED region 114L of the N-type TFT using the photoresist pattern 228 as a mask, as shown in FIG. 12C, the source region 114S of the first active layer 114 of the N-type TFT is shown. And the drain region 114D is formed.

13A and 13B are a plan view and a cross-sectional view for describing a fourth mask process during the manufacturing process of a liquid crystal display according to the present invention.

13A and 13B, the third active layer 174 of the P-type TFT divided into the LED region 174L and the channel region 174C is subjected to the channel region 174C and the source region (3) by a third mask process. 174S) and the drain region 174D. This will be described in detail with reference to FIGS. 14A to 14C.

After the photoresist 236 is formed on the lower substrate 101 on which the first active layer 114, the second active layer 144, and the third active layer 174 are implanted, n-, n + ions are formed, FIG. 14A. As shown in FIG. 4, the fourth mask 230 is aligned on the lower substrate 101. The fourth mask 230 may include a mask substrate 232 formed of a transparent material and an exposed region forming an exposure region S2, and a blocking portion 234 formed in the blocking region S1 of the mask substrate 232. Equipped. The photoresist 236 is patterned by the photolithography process using the fourth mask 230 to form the photoresist pattern 238 as shown in FIG. 14B. The photoresist pattern 238 is formed to overlap the N-type TFT region and the storage capacitor region. By using the photoresist pattern 238 and the gate electrode 166 of the P-type TFT as a mask, p + ions are implanted into the third active layer 174 of the P-type TFT so that the channel region of the third active layer 174 ( P + ions are implanted into the region 174C). Accordingly, as shown in FIG. 14C, the third active layer 174 of the P-type TFT is non-overlapping with the channel region 174C overlapping the gate electrode 166, the gate electrode 166, and the p + ion is implanted. The source region 174S and the drain region 174D.

15A and 15B are a plan view and a cross-sectional view for describing a fifth mask process in the method of manufacturing the liquid crystal display device according to the present invention.

15A and 15B, the source and drain contact holes 124S of the N-type and P-type TFTs are formed by a fifth mask process on the lower substrate 101 on which the third active layer 174 implanted with p + ions is formed. And an interlayer insulating film 126 having 184S, 124D, and 184D and storage contact holes 142 are formed.

In detail, the interlayer insulating film 126 is formed by depositing an insulating material on the lower substrate 101 having the third active layer 174 implanted with p + ions through a deposition method such as PECVD or sputtering. After the photoresist is entirely deposited on the lower substrate 101 on which the interlayer insulating layer 126 is formed, the photoresist is patterned by a photolithography process using a fifth mask to form a photoresist pattern. The interlayer insulating film 126 and the gate insulating film 112 are patterned by an etching process using the photoresist pattern as a mask, so that the source and drain contact holes 124S, 184S, 124D, and 184D and the storage capacitor of the N-type and P-type TFTs are patterned. The storage contact hole 142 is formed. The source and drain contact holes 124S, 184S, 124D, and 184D of the N-type and P-type TFTs respectively pass through the interlayer insulating film 126 and the gate insulating film 112 to form an active layer 114 and a P-type TFT of the N-type TFT. Source and drain regions 114S, 174S, 114D, and 174D of the active layer 174 are exposed. The storage contact hole 142 of the storage capacitor passes through the interlayer insulating layer 126 and the gate insulating layer 112 to expose the storage lower electrode 150.

16A and 16B are a plan view and a cross-sectional view for describing a sixth mask process of a liquid crystal display according to the present invention in detail.

16A and 16B, an N-type is formed on the lower substrate 101 on which the source contact holes 124S and 184S, the drain contact holes 124D and 184D, and the storage contact holes 142 are formed. And source electrodes 108 and 168 and drain electrodes 110 and 170 of the P-type TFT are formed.

In detail, the data metal layer is deposited on the entire surface of the lower substrate 101 on which the source contact holes 124S and 184S, the drain contact holes 124D and 184D, and the storage contact holes 142 are formed by sputtering. do. After the photoresist is entirely deposited on the data metal layer, the photoresist is patterned by a photolithography process using a sixth mask to form a photoresist pattern. The data metal layer is patterned by an etching process using the photoresist pattern as a mask to form source electrodes 108 and 168 and drain electrodes 110 and 170 of the N-type and P-type TFTs, respectively. The source electrodes 108 and 168 and the drain electrodes 110 and 170 of the N-type and P-type TFTs respectively include the source regions 114S of the first active layer 114 of the N-type TFT and the third active layer 174 of the P-type TFT. 174S) and the drain regions 114D and 174D, and the source contact holes 124S and 184S and the drain contact holes 124D and 184D. Here, the drain electrode 110 of the N-type TFT positioned in the image display unit is electrically connected to the storage lower electrode 150 through the storage contact hole 142.

17A and 17B are a plan view and a cross-sectional view for describing a seventh mask process in detail during a manufacturing process of a liquid crystal display according to the present invention.

17A and 17B, a passivation layer 118 having pixel contact holes 120 is formed on a lower substrate 101 on which source electrodes 108 and 168 and drain electrodes 110 and 170 are formed using a seventh mask process. do.

In detail, the protective layer 118 is formed by depositing an insulating material on the lower substrate 101 on which the source electrodes 108 and 168 and the drain electrodes 110 and 170 are formed by a deposition method such as PECVD or sputtering. The protective film 118 may be formed of an inorganic insulating material or an organic insulating material including SiO ₂ , SiNx, or the like. A photoresist is deposited on the lower substrate 101 on which the passivation layer 118 is formed. Thereafter, the photoresist is patterned by a photolithography process using a seventh mask to form a photoresist pattern. The protective film 118 is patterned by an etching process using the photoresist pattern as a mask to form a pixel contact hole 120 exposing the drain electrode 110 of the N-type TFT positioned in the image display unit.

18A and 18B are plan and cross-sectional views illustrating in detail an eighth mask process of a liquid crystal display according to the present invention.

18A and 18B, the pixel electrode 122 positioned on the image display unit is formed on the lower substrate 101 on which the passivation layer 118 is formed by using an eighth mask process.

In detail, the transparent conductive material and the photoresist are sequentially deposited on the lower substrate 101 on which the protective film 118 is formed through a deposition method such as sputtering. Herein, indium tin oxide, indium zinc oxide, indium tin zinc oxide, etc. may be used as the transparent conductive material. Thereafter, the photoresist is patterned by a photolithography process using an eighth mask to form a photoresist pattern. The transparent metal layer is patterned by an etching process using the photoresist pattern as a mask to form the pixel electrode 122. The pixel electrode 122 is formed through the pixel contact hole 120 to contact the drain electrode 110 of the N-type TFT positioned in the image display unit.

19 is a cross-sectional view of a liquid crystal display according to a second exemplary embodiment of the present invention.

Referring to FIG. 19, the liquid crystal display according to the second exemplary embodiment of the present invention is formed along the storage lower electrode 150 under the storage lower electrode 150 of the storage capacitor as compared to the liquid crystal display shown in FIG. 6. Except for further comprising a second active layer 144 and the insulating pattern 250 is provided with the same components.

The storage capacitor 160 includes a storage lower electrode 150 connected through the drain electrode 110 and the storage contact hole 142 of the image TFT 130 positioned in the image display unit, the storage lower electrode 150 and the gate thereof. It consists of the story upper electrode 152 which overlaps with the insulating film 112 interposed.

Here, the storage lower electrode 150 is formed in the same pattern as the insulating pattern 250 and the second active layer 144 and is electrically connected to the pixel electrode 122 through the drain electrode 110 of the image TFT 130. do. In this case, the insulating pattern 250 serves to prevent deterioration of device characteristics generated when the storage lower electrode 150 is in contact with the second active layer 144 made of a polysilicon layer.

The storage capacitor 160 allows the pixel signal charged in the pixel electrode 122 to be stably maintained until the next pixel signal is charged.

20A through 20D are cross-sectional views illustrating in detail a first mask process of a liquid crystal display according to a second exemplary embodiment of the present invention.

First, as shown in FIG. 20A, a buffer film 116 and an amorphous silicon film are sequentially formed on the lower substrate 101 through a deposition method such as PECVD or sputtering. As the material of the buffer film 116, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. Then, the amorphous silicon film is crystallized by a laser to form the polysilicon film 206. The insulating film 250, the storage metal layer 208, and the photoresist 268 are formed on the polysilicon film 206. Here, SiO ₂ , SiN x, and the like are used for the insulating layer 250, and the storage metal layer 208 is made of a conductive metal, for example, a gate metal layer, a data metal layer, or a transparent conductive material.

Next, the first mask 260 is aligned on the lower substrate 101 on which the photoresist 268 is formed. The first mask 260 may be formed of a transparent material, and may include a mask substrate 262 in which an exposed area forms an exposure area S2, a blocking part 264 formed in a blocking area S1 of the mask substrate 262, and The diffraction exposure part 266 (or semi-transmissive part) formed in the partial exposure area S3 of the mask substrate 262 is provided. After exposing and developing the photoresist film using the first mask 260, as illustrated in FIG. 20B, the blocking region S1 corresponds to the blocking portion 264 and the diffraction exposure portion 266 of the first mask 260. ) And the photoresist pattern 270 having a step in the partial exposure area S3 is formed. That is, the photoresist pattern 270 formed in the partial exposure region S3 has a second height lower than that of the photoresist pattern 270 having the first height formed in the blocking region S1.

The storage metal layer 208 is patterned by a wet etching process using the photoresist pattern 270 as a mask to form a storage pattern including the upper storage electrode 150 and the metal pattern. The insulating layer 250 and the polysilicon layer 206 are patterned by a dry etching process using the photoresist pattern 270 as a mask to form the insulating pattern 250, the first active layer 114, and the second active layer along the storage pattern. The active layer 144 and the third active layer 174 are formed.

Subsequently, in the ashing process using an oxygen (O ₂ ) plasma, the photoresist pattern 270 having the second height in the partial exposure region S3 is removed as shown in FIG. 20C, and the blocking region S1 is removed. The photoresist pattern 270 having the first height is in a state where the height is lowered. In the etching process using the photoresist pattern 270, the metal pattern 270 and the insulating pattern 250 of the partial exposure region S3, that is, the N-type and P-type TFT regions are removed.

As shown in FIG. 20D, the photoresist pattern 270 remaining on the storage lower electrode 150 is removed by a strip process.

As described above, the liquid crystal display panel and the method of manufacturing the same according to the present invention sequentially deposit the active layer and the metal layer, and simultaneously form the storage lower electrode and the active layer by a photolithography process and an etching process including diffraction exposure. do. Accordingly, the liquid crystal display panel and the method of manufacturing the same according to the present invention can manufacture the lower array substrate of the liquid crystal display panel in an eight mask process in the conventional nine mask process, thereby simplifying the structure and process of the lower array substrate. In addition to cost savings, manufacturing yields can be improved. Further, in order to use a conventional active layer as a lower electrode of a storage capacitor, PH ₃ ions are implanted into the active layer, whereas in the present invention, a separate ion implantation process can be reduced by forming the lower electrode of the storage capacitor as a metal layer.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (11)

Forming a storage lower electrode overlapping the first active layer of the thin film transistor, the second active layer of the storage capacitor, and the entirety of the second active layer on the substrate; Forming a gate insulating film on a substrate on which the first active layer, the second active layer, and the storage lower electrode are formed; Forming a storage upper electrode overlapping the gate electrode and the storage lower electrode on the gate insulating layer; Forming an interlayer insulating film on a substrate on which the gate electrode and the storage upper electrode are formed; And And forming a drain electrode on the interlayer insulating layer and a source electrode connected to the storage lower electrode and a source electrode facing the drain electrode. The method of claim 1, The forming of the first active layer, the second active layer, and the storage lower electrode comprises using a first mask including three regions having different transmittances. The method of claim 1, And forming an insulating pattern between the second active layer and the storage lower electrode. The method of claim 1, Implanting a first impurity into the first active layer by using the gate electrode; And And injecting a second impurity into the first active layer into which the first impurity is implanted. The method of claim 1, Forming a protective film to cover the source electrode and the drain electrode; And And forming a pixel electrode connected to the drain electrode on the passivation layer. The method of claim 5, And the storage lower electrode is made of a material including a conductive metal. A first active layer formed on the substrate, a gate electrode formed on the gate insulating layer to be insulated from the first active layer, and a gate electrode overlapping the channel region of the first active layer, and formed on the interlayer insulating layer to be insulated from the gate electrode; A thin film transistor having source and drain electrodes connected to the source and drain regions of the first active layer; A pixel electrode connected to the drain electrode of the thin film transistor; And A second active layer positioned on the same plane as the first active layer, a storage lower electrode overlapping the same pattern as the second active layer, and connected to the drain electrode; And a storage capacitor having a storage upper electrode formed on the liquid crystal display panel. The method of claim 7, wherein And the second active layer and the lower storage electrode are in contact with each other. The method of claim 7, wherein And a dielectric pattern interposed between the second active layer and the storage lower electrode. The method of claim 7, wherein And a contact hole penetrating the interlayer insulating film and the gate insulating film to expose the storage lower electrode so that the storage lower electrode and the drain electrode contact each other. The method of claim 7, wherein And an LDD region is formed between the channel region and the source region of the first active layer and between the channel region and the drain region of the first active layer.

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