KR20050046164A - Thin film transistor array substrate and manufacturing method of the same - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate capable of improving device characteristics by reducing resistance generated in the device, and a method of manufacturing the same.

The present invention provides a source electrode and a drain electrode of a thin film transistor formed on a substrate; An active layer in contact with the substrate and formed over the source electrode and the drain electrode; An ohmic contact layer formed in an overlapping portion of the active layer with the source electrode and the drain electrode; A gate electrode formed to be insulated from the active layer with a gate insulating film interposed therebetween; And a pixel electrode connected to the drain electrode.

Description

      Thin Film Transistor Array Substrate and Manufacturing Method Thereof {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD OF THE SAME}

The present invention relates to a thin film transistor array substrate and a method for manufacturing the same, and more particularly, to a thin film transistor array substrate and a method for manufacturing the same can be improved by reducing the resistance generated in the device.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor array substrate and a color filter array substrate facing each other, a spacer positioned to maintain a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap.

The thin film transistor array substrate includes a gate line and a data line, a thin film transistor formed of a switch element at each intersection of the gate lines and the data lines, a pixel electrode formed of a liquid crystal cell and connected to the thin film transistor, and the like. It consists of the applied alignment film. The gate lines and the data lines receive signals from the driving circuits through the respective pad parts. The thin film transistor supplies the pixel signal supplied to the data line to the pixel electrode in response to the scan signal supplied to the gate line.

The color filter array substrate includes color filters formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal cells in common, and an alignment layer applied thereon. It consists of.

The liquid crystal panel is completed by separately manufacturing a thin film transistor array substrate and a color filter array substrate, and then injecting and encapsulating a liquid crystal.

1 is a cross-sectional view showing a portion of a conventional thin film transistor array substrate.

The thin film transistor of the thin film transistor array substrate illustrated in FIG. 1 is in contact with the lower substrate 142 and is connected to the data line with the source electrode 10, the drain electrode 12 facing the source electrode 10, and the source electrode ( 10 and on the drain electrode 12 to form an ohmic contact layer 13 for ohmic contact with the active layer 14, an ohmic contact layer 10, and a source electrode 10 and a drain electrode 12. An active layer 14 forming a channel therebetween, and a gate electrode 6 formed to be insulated from the active layer 14 with the gate insulating film 44 interposed therebetween, and connected to the gate line.

The thin film transistor allows the pixel signal supplied to the data line to be charged and held in the pixel electrode 18 in response to the gate signal supplied to the gate line.

The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor through a contact hole 20 penetrating through the passivation layer 50. The pixel electrode 18 generates a potential difference from the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor substrate and the upper substrate rotates by dielectric anisotropy, and transmits light incident through the pixel electrode 18 from the light source (not shown) toward the upper substrate.

2A to 2E are schematic diagrams illustrating a method of manufacturing a conventional thin film transistor array substrate in stages.

First, the source / drain metal layer and the n + amorphous silicon layer are sequentially formed on the lower substrate 42 by a deposition method such as PECVD or sputtering, and then the source / drain metal layer and n + by a photolithography process and an etching process using a mask. An amorphous silicon layer is patterned. Accordingly, as shown in FIG. 2A, an ohmic contact layer 13 is formed on the source / drain pattern including the source electrode 10 and the drain electrode 12. Here, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy) and the like are used as the sp / drain metal.

After the amorphous silicon layer is deposited on the lower substrate 42 on which the source / drain electrodes 10 and 12 and the ohmic contact layer 13 are formed by PECVD or sputtering, a photolithography process and an etching process using a mask The amorphous silicon layer is patterned by. As a result, the active layer 14 is formed as shown in FIG. 2B.

The gate insulating film 44 is formed on the lower substrate 44 on which the active layer 14 is formed. As the material of the gate insulating film 44, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. In addition, an organic insulating material such as BCB or acrylic resin may be used.

After the gate metal layer is deposited on the lower substrate 42 on which the gate insulating layer 44 is formed through a deposition method such as a sputtering method, the gate metal layer is patterned by a photolithography process and an etching process using a mask. As a result, the gate electrode 6 is formed as shown in FIG. 2C. Here, as the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, or the like is used in a single layer or double layer structure.

The passivation layer 50 is entirely formed on the lower substrate 42 on which the gate electrode 6 is formed by a deposition method such as PECVD. Thereafter, the protective film 50 is patterned by a photolithography process and an etching process using a mask. Accordingly, the contact hole 20 is formed as shown in FIG. 2D. The contact hole 20 is formed to pass through the passivation layer 50, the gate insulating layer 44, the active layer 14, and the ohmic contact layer 13 to expose the drain electrode 12. Here, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the protective film 50.

The transparent electrode material is deposited on the entire surface of the lower substrate 42 on which the passivation layer 50 is formed by sputtering or the like. Subsequently, the transparent electrode material is patterned through a photolithography process and an etching process using a mask. Accordingly, the pixel electrode 18 is formed as shown in FIG. 2E. The pixel electrode 18 is electrically connected to the drain electrode 12 through the contact hole 20. Herein, indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

Meanwhile, in the conventional thin film transistor, as shown in FIG. 3, the channel path A is disposed on the drain electrode 12 via the ohmic contact layer 13 and the active layer 14 stacked on the source electrode 10. A channel is formed between the source electrode 10 and the drain electrode 10 via the ohmic contact layer 13 and the active layer 14 stacked thereon. However, such a conventional structure causes a problem that the device characteristics such as the charge mobility is reduced due to the resistance generated in the device and the response speed of the device is lowered.

Specifically, after the source / drain metal layer and the n + amorphous silicon layer are sequentially deposited, the source / drain electrodes 10 and 12 and the ohmic contact layer 13 are simultaneously formed using a mask process. Here, the ohmic contact layer 13 is exposed to the atmosphere to react with silicon (Si) of the ohmic contact layer 13 and oxygen (O ₂ ) in the atmosphere. As a result, the silicon oxide film (SiOx) is formed on the ohmic contact layer 13, thereby reducing the charge mobility.

In addition, the ohmic contact layer 13 and the active layer 14 overlapping the source electrode 10 and the ohmic contact layer 13 and the active layer 14 overlapping the drain electrode 12 become a channel path. As such, the mobility decreases due to self resistance in the ohmic contact layer 13 and the active layer 14.

As described above, the structure of the thin film transistor of the conventional thin film transistor array substrate has device characteristics such as a decrease in charge mobility due to the generation of contact resistance and self resistance in the active layer by the silicon oxide film, resulting in a slow response time of the device. The problem of deterioration arises.

       Accordingly, it is an object of the present invention to provide a thin film transistor array substrate and a method for manufacturing the same, which can improve device characteristics by reducing resistance generated in the device.

In order to achieve the above object, the thin film transistor array substrate according to the present invention includes a source electrode and a drain electrode of the thin film transistor formed on the substrate; An active layer in contact with the substrate and formed over the source electrode and the drain electrode; An ohmic contact layer formed in an overlapping portion of the active layer with the source electrode and the drain electrode; A gate electrode formed to be insulated from the active layer with a gate insulating film interposed therebetween; And a pixel electrode connected to the drain electrode.

And a dummy insulating pattern formed between the active layer and the gate insulating layer to expose the ohmic contact layer.

The ohmic contact layer may be formed by doping n + ions into the active layer.

And a passivation layer formed to cover the thin film transistor, wherein the pixel electrode is in contact with the drain electrode through a through hole passing through the passivation layer, the gate insulating layer, and the ohmic contact layer.

A method of manufacturing a thin film transistor array substrate according to the present invention includes forming a source electrode and a drain electrode of a thin film transistor on a substrate; Forming an active layer in contact with the substrate and formed on the source electrode and the drain electrode, and a dummy insulating pattern formed on the channel region of the active layer; Forming an ohmic contact layer by implanting impurities into the active layer using the dummy insulating pattern as a mask; Forming a gate insulating film on the substrate on which the ohmic contact layer is formed; Forming a gate electrode on the gate insulating film; Forming a passivation layer on the gate electrode; Exposing the drain electrode on the gate insulating layer through a through hole passing through the ohmic contact layer, the gate insulating layer, and the passivation layer; And forming a pixel electrode connected to the exposed drain electrode.

The forming of the active layer and the dummy insulating pattern may include sequentially depositing an amorphous silicon layer and an insulating material on the substrate on which the source and drain electrodes are formed; Forming a photoresist on the insulating material; Patterning the amorphous silicon layer and an insulating material using the photoresist as a mask to form an active layer; Leaving the photoresist in a region overlapping the channel region of the active layer; Patterning the insulating material using the remaining photoresist as a mask; Removing the remaining photoresist.

The remaining photoresist is formed using an oxygen plasma.

The ohmic contact layer may be formed by implanting impurities into an active layer that is not overlapped with the dummy insulating pattern.

The impurity is characterized in that the n + ion.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 7.

4 is a plan view illustrating a portion of a thin film transistor array substrate according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 4 taken along line II ′.

The thin film transistor array substrate illustrated in FIGS. 4 and 5 includes a gate line 102 and a data line 104 intersecting on the lower substrate 142, a thin film transistor formed at each intersection thereof, and a cell having a cross structure. The pixel electrode 118 formed in the area is provided.

The thin film transistor is in contact with the lower substrate 142 and is connected to the data line 104, the source electrode 110, the drain electrode 112 facing the source electrode 110, and the first and second gate insulating layers 143 and 144. A gate electrode 106 formed to be insulated from the source electrode 110 and the drain electrode 112 with a gap therebetween and overlapping with the first gate insulating layer 143 along a lower portion of the first gate insulating layer 143. Impurities, for example, in the active layer 114 and the active layer 114 formed over the source electrode 110 and the drain electrode 112 to form a channel between the source electrode 110 and the drain electrode 112. An ohmic contact layer 113 formed on the source electrode 110 and the drain electrode 112 and connected to the same layer as the active layer 114 which is doped with n + ions to which impurities are not implanted is provided.

The ohmic contact layer 113 is formed by doping n + ions using the first gate insulating layer 143 as a mask in a region not overlapped with the first gate insulating layer 143. As described above, the ohmic contact layer 113 is not formed at the same time as the source / drain metal layer but is formed by implanting ions into the active layer 114 so that the ohmic contact layer 113 is not exposed to the air. As a result, generation of the silicon oxide film is prevented.

In addition, as shown in FIG. 6, an ohmic contact layer 113 is formed on the source electrode 110 and the drain electrode 112, so that the channel proceeds over the source electrode 110 and the drain electrode 112 as compared with the related art. The path will be reduced. The resistance of the ohmic contact layer 113 and the active layer 114 in the ohmic contact layer 113 and the active layer 114 is reduced by this reduced channel path (B), and the mobility becomes faster by the reduced resistance. As described above, as the silicon oxide film is prevented from being produced and the channel path is shortened, the resistance of the ohmic contact layer 113 and the active layer 114 decreases its own resistance, thereby increasing the rate of charge mobility through the channel. Device characteristics are improved.

The thin film transistor allows the pixel signal supplied to the data line 104 to be charged and held in the pixel electrode 118 in response to the gate signal supplied to the gate line 102.

The pixel electrode 118 is connected to the drain electrode 112 of the thin film transistor through the contact hole 120 passing through the passivation layer 150. The pixel electrode 118 generates a potential difference with the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. This potential difference causes the liquid crystal located between the thin film transistor substrate and the upper substrate to rotate by dielectric anisotropy, and transmits light incident through the pixel electrode 118 from the light source (not shown) toward the upper substrate.

7A to 7G are cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor array substrate according to the present invention shown in FIG. 5.

First, the source / drain metal layer is deposited on the lower substrate 142 by a deposition method such as PECVD or sputtering, and then the source / drain metal layer is patterned by a photolithography process and an etching process using a mask. As a result, as shown in FIG. 7A, a source / drain pattern including the source electrode 110 and the drain electrode 112 is formed. Here, as the source / drain metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy) and the like are used.

After the amorphous silicon layer and the first gate insulating layer 143a are sequentially deposited on the lower substrate 142 on which the source / drain patterns are formed by PECVD or sputtering, a photolithography process using a mask is performed. The resist pattern 155 is formed. Thereafter, the amorphous silicon layer and the first gate insulating layer 143a are patterned by an etching process using the photoresist pattern 155 as a mask, thereby forming the active layer 114 as shown in FIG. 7B. Subsequently, a part of the photoresist pattern 155 remains in a region overlapping with the channel region of the thin film transistor by an ashing process using oxygen (O ₂ ) plasma or the like. Thereafter, the remaining photoresist pattern 155 is used as a mask to pattern the first gate insulating layer 143a to expose the active layer 114 in the region except for the channel region as shown in FIG. 7C. The gate insulating film 143 is formed. Thereafter, n + ions are doped into the exposed active layer 114 using the first gate insulating layer 143 as a mask to form an ohmic contact layer 113 as shown in FIG. 7D. Thereafter, the remaining photoresist pattern 155 is removed by the strip process. Here, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the first gate insulating layer 143.

The second gate insulating layer 144 is formed on the lower substrate 142 on which the ohmic contact layer 113 is formed. As the material of the second gate insulating layer 144, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

After the gate metal layer is deposited on the lower substrate 42 on which the second gate insulating layer 144 is formed through a deposition method such as a sputtering method, the gate metal layer is patterned by a photolithography process and an etching process using a mask. As a result, the gate electrode 106 is formed as shown in FIG. 7E. Here, as the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, or the like is used in a single layer or double layer structure.

The passivation layer 150 is entirely formed on the lower substrate 142 on which the gate electrode 106 is formed by a deposition method such as PECVD. Thereafter, the passivation layer 150 is patterned by a photolithography process and an etching process using a mask. Accordingly, the contact hole 120 is formed as shown in FIG. 7F. The contact hole 120 is formed through the passivation layer 150, the first and second gate insulating layers 143 and 144, and the ohmic contact layer 113 to expose the drain electrode 112. Here, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the protective film 150. In addition, an organic insulating material such as BCB or acrylic resin may be used as the material of the protective film.

The transparent electrode material is deposited on the entire surface of the lower substrate 142 on which the passivation layer 150 is formed by sputtering or the like. Subsequently, the transparent electrode material is patterned through a photolithography process and an etching process using a mask. Accordingly, the pixel electrode 118 is formed as shown in FIG. 7G. The pixel electrode 118 is electrically connected to the drain electrode 112 through the contact hole 120. Herein, indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

As described above, in the thin film transistor array substrate and the method of manufacturing the same, the first gate insulating layer 143 is formed in the channel region of the active layer 114 and the active layer is formed using the first gate insulating layer 143 as a mask. The ohmic contact layer 113 is formed by doping n + ions on the 114. Accordingly, it is possible to prevent the generation of the silicon oxide film generated by exposing the ohmic contact layer to the atmosphere during the simultaneous patterning of the conventional source / drain metal layer and the ohmic contact layer. In addition, the channel path is shortened by forming an ohmic contact layer doped with n + ions in a portion of the active layer instead of the ohmic contact layer formed by the pattern as compared with the conventional art.

As such, the generation of the silicon oxide film is prevented and the channel path is shortened, thereby reducing the resistance generated in the device as compared with the conventional method, thereby increasing the charge mobility. As a result, device characteristics such as response speed of the device are improved.

As described above, the thin film transistor array substrate and the method of manufacturing the same according to the present invention do not n n ions in a predetermined region of the active layer to form an ohmic contact layer to prevent the formation of a silicon oxide film on the ohmic contact layer and the channel path Becomes shorter. Accordingly, the resistance generated in the device can be reduced, thereby improving the device characteristics such as the charge mobility.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a cross-sectional view showing a part of a conventional thin film transistor array substrate.

2A to 2E are diagrams illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 1.

3 is a diagram illustrating a channel path of the thin film transistor illustrated in FIG. 1.

4 is a plan view showing a portion of a thin film transistor array substrate according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor array substrate of FIG. 4 taken along the line II ′. FIG.

6 illustrates a channel path of a thin film transistor array substrate according to the present invention.

7A to 7G are cross-sectional views illustrating a step in manufacturing a thin film transistor array substrate illustrated in FIG. 5.

<Explanation of symbols for the main parts of the drawings>

102: gate line 104: data line

6,106: gate electrode 20,120: contact hole

10,110 source electrode 12112 drain electrode

13,113: ohmic contact layer 14,114: active layer

18,118 pixel electrode 155 photoresist pattern

Claims (9)

A source electrode and a drain electrode of the thin film transistor formed on the substrate; An active layer in contact with the substrate and formed over the source electrode and the drain electrode; An ohmic contact layer formed in an overlapping portion of the active layer with the source electrode and the drain electrode; A gate electrode formed to be insulated from the active layer with a gate insulating film interposed therebetween; And a pixel electrode connected to the drain electrode. The method of claim 1, And a dummy insulating pattern formed between the active layer and the gate insulating layer to expose the ohmic contact layer. The method of claim 1, The ohmic contact layer is a thin film transistor array substrate, characterized in that the active layer is doped with n + ions. The method of claim 1, Further provided with a protective film formed to cover the thin film transistor, And the pixel electrode is in contact with the drain electrode through a through hole passing through the passivation layer, the gate insulating layer, and the ohmic contact layer. Forming a source electrode and a drain electrode of the thin film transistor on the substrate; Forming an active layer in contact with the substrate and formed on the source electrode and the drain electrode, and a dummy insulating pattern formed on the channel region of the active layer; Forming an ohmic contact layer by implanting impurities into the active layer using the dummy insulating pattern as a mask; Forming a gate insulating film on the substrate on which the ohmic contact layer is formed; Forming a gate electrode on the gate insulating film; Forming a passivation layer on the gate electrode; Exposing the drain electrode on the gate insulating layer through a through hole passing through the ohmic contact layer, the gate insulating layer, and the passivation layer; And forming a pixel electrode connected to the exposed drain electrode. The method of claim 5, wherein Forming the active layer and the dummy insulating pattern Sequentially depositing an amorphous silicon layer and an insulating material on the substrate on which the source and drain electrodes are formed; Forming a photoresist on the insulating material; Patterning the amorphous silicon layer and an insulating material using the photoresist as a mask to form an active layer; Leaving the photoresist in a region overlapping the channel region of the active layer; Patterning the insulating material using the remaining photoresist as a mask; And removing the remaining photoresist. The method of claim 6, The remaining photoresist is formed using an oxygen plasma method of manufacturing a thin film transistor array substrate. The method of claim 5, wherein The ohmic contact layer is a method of manufacturing a thin film transistor array substrate, characterized in that the impurity is injected into the active layer that is not overlapped with the dummy insulating pattern. The method of claim 5, wherein And the impurity is n + ions.