KR101136410B1 - Array substrate for Liquid Crystal Display Device and method of fabricating the same - Google Patents

Abstract

The present invention relates to an array substrate for a liquid crystal display device using polysilicon and a method of manufacturing the same.

The array substrate for a liquid crystal display device using polysilicon according to the present invention is a polysilicon and a transparent conductive material that transmits light to the first and second storage electrodes in a storage region where a storage capacitor is formed. The present invention provides an array substrate for a liquid crystal display device and a method of manufacturing the same, wherein an electrode is formed in a layer for forming a semiconductor layer and the second storage electrode is formed in a layer for forming a pixel electrode.

Description

Array substrate for liquid crystal display device and method for manufacturing same {Array substrate for Liquid Crystal Display Device and method of fabricating the same}

1 is a schematic diagram of an array substrate for a liquid crystal display device integrated with a general driving circuit.

2 is a plan view of one pixel region inside an array substrate for a liquid crystal display device using polysilicon;

3 is a cross-sectional view taken along the line III-III of FIG. 2;

4 is a plan view of one pixel area of an array substrate for a liquid crystal display device using polysilicon according to an embodiment of the present invention.

5 is a cross-sectional view taken along the line V-V of FIG. 4.

6 is a cross-sectional view taken along the line VI-VI of FIG. 4.

7 is a plan view briefly showing only the shape of the first storage electrode in one pixel area as a first modification of the embodiment of the present invention;

FIG. 8 is a plan view schematically showing only the shape of the first storage electrode in one pixel area as a second modification of the embodiment of the present invention; FIG.

FIG. 9 is a cross-sectional view of a portion similar to a portion cut along a cutting line V-V of FIG. 4 as a cross-sectional view of a third modification of the embodiment of the present invention; FIG.

Fig. 10 is a sectional view of a third section of the embodiment of the present invention and the same section as the section cut along the line VI-VI in Fig. 4;

11A to 11I are cross-sectional views illustrating a manufacturing process of a method of manufacturing an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, taken along the line VV of FIG. 4.

12A to 12I are cross-sectional views illustrating a manufacturing process of a method of manufacturing an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, taken along the line VV of FIG. 4.

<Description of Symbols for Main Parts of Drawings>

101 substrate 105 buffer layer

110: semiconductor layer 110a: active layer

110b: ohmic contact layer 114: first storage electrode

114a: first storage electrode portion disposed in parallel with the gate wiring

117: gate insulating film 120: first storage electrode contact hole

125: gate wiring 127: gate electrode

130: common wiring 135: interlayer insulating film

137 and 139: semiconductor layer contact hole 145: data wiring

147: source electrode 149: drain electrode

155: interlayer insulating film 157: drain contact hole

159: gate insulating film exposed groove 165: pixel electrode

167: second storage electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a substrate for a liquid crystal display device with a driving circuit unit and a manufacturing method thereof.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, technology-intensive, and high added value.

The liquid crystal display device injects a liquid crystal between an array substrate including a thin film transistor (TFT) and a color filter substrate to obtain an image effect by using a difference in refractive index of light according to the anisotropy of the liquid crystal. Means an image display device by a non-light emitting element.

Currently, an active matrix liquid crystal display (AM-LCD) in which the thin film transistor and the pixel electrode are arranged in a matrix manner has been attracting the most attention because of its excellent resolution and video performance. Hydrogenated amorphous silicon (a-Si: H) is mainly used because low-temperature processing is possible, so that an inexpensive insulating substrate can be used.

However, since hydrogenated amorphous silicon (a-Si: H) is disordered in its atomic arrangement, weak Si-Si bonds and dangling bonds exist, and thus, in a state of quasi-stable state when light irradiation or electric field is applied. It is difficult to use as a driving circuit because the stability is a problem when it is used as a thin film transistor element and its electrical characteristics (low field effect mobility: 0.1∼1.0㎠ / V? S) are not good.

Therefore, in general, a driving device manufactured separately is connected to the liquid crystal panel, and as a representative example, the driving device is manufactured in TCP (Tape Carrier Package) and attached to the liquid crystal panel. Accordingly, in the TCP, a plurality of circuit parts are attached between a PCB (Printed Circuit Board) substrate and a liquid crystal panel to receive a signal input from the PCB substrate and transfer the signal to the liquid crystal panel. However, such a configuration occupies a large part of the cost of the actual equipment of the driver IC, and as the resolution of the liquid crystal panel increases, the pad pitch outside the substrate connecting the gate wiring and the data wiring of the thin film transistor substrate with the TCP is short. TCP bonding itself is becoming difficult.

On the other hand, polysilicon (poly-Si) is superior to amorphous silicon (a-Si), and excellent electrical characteristics such as field effect mobility, even if the driving circuit is formed on the substrate. Accordingly, by forming the driving circuit directly on the substrate using the polysilicon, the driving IC cost can be reduced and the mounting is simplified.

1 is a schematic view of an array substrate for a liquid crystal display device integrated with a general driving circuit unit.

As shown, the driving circuit portion 5 and the pixel portion 3 are formed on the insulating substrate 1 together. The pixel portion 3 is positioned at the center of the substrate 1, and gate and data driving circuit portions 5a and 5b are positioned at one side of the pixel portion 3 and the other side not parallel thereto. In the pixel portion 3, a plurality of gate lines 7 connected to the gate driving circuit part 5a and a plurality of data lines 9 connected to the data driving circuit part 5b cross each other, and the two wires cross each other. The pixel electrode 10 is formed in the pixel region P defined by the pixel region, and the thin film transistor T connected to the pixel electrode 10 is positioned at the intersection of the two wires.

In addition, the gate and data driving circuit unit are connected to an external signal input terminal 12.

The gate and data driver circuits 5a and 5b internally adjust an external signal input through the external signal input terminal 12 to control the display to the pixel unit 3 through the gate and data lines 7 and 9, respectively. Apparatus for supplying signals and data signals.

Accordingly, the gate and data driving circuits 5a and 5b are thin film transistors (complementary metal-oxide semiconductor), NMOS, or PMOS structures as inverters to properly output the input signals. Is formed inside the driving circuit portion.

FIG. 2 is a plan view of one pixel portion inside an array substrate for a liquid crystal display device in which driving and switching elements are constructed using a conventional polysilicon.

As shown, data lines 45 are formed in the vertical direction in the active region displaying the image of the array substrate 15, and gate lines 30 and the common wiring 32 are formed in the horizontal direction. The thin film transistor Tr, which is a switching element, is formed at a portion where the gate wiring 30 and the data wiring 45 cross each other.

In addition, the data line 45 and the gate line 30 cross each other to define one pixel area P. In the one pixel area P, a thin film transistor Tr and a backlight (not shown) are switched. A part of the pixel region P of the common wiring 32 formed at a predetermined interval from the opening OA, which is an area for displaying an image by passing the incident light from the light source, and the common wiring 32. A storage capacitor StgC having a width wider than the width of 32 and forming the second storage electrode 33 is formed.

3 is a view showing the shape of the cross section taken along the cutting line III-III of FIG. Hereinafter, the cross-sectional structure of the array substrate for a liquid crystal display device using the aforementioned polysilicon will be described.

As shown, the buffer layer 18 is formed on the substrate 15, and the first and second semiconductor layers 23 and 25 formed of polysilicon are formed on the portion TrA (hereinafter, referred to as a switching element). And a portion StgA (hereinafter, referred to as a storage region) in which a switching region is formed and a storage capacitor is formed. In this case, the first semiconductor layer 23 of the switching region TrA includes an active layer 23a made of pure polysilicon at the center and an ohmic contact layer 23b doped to both sides of the active layer 23a. .

Next, a gate insulating film 28 is formed on the entire surface of the first and second semiconductor layers 23 and 25, and an active layer 23a in the center of the first semiconductor layer 23 is formed on the gate insulating film 28. Is overlapped with the second semiconductor layer 25 in the storage region StgA, and the second storage electrode 40 is formed. In this case, the second storage electrode 40 includes a first storage electrode 25 formed by n + doping the second semiconductor layer 25 below and a conductive material, and the first and second storage electrodes 25 and 40. The first storage capacitor StgC1 is formed together with the gate insulating layer 28 serving as a dielectric disposed between the layers.

Next, an interlayer insulating layer 43 formed thicker than the gate insulating layer 28 is formed on the entire surface of the gate insulating layer 28 on which the gate electrode 35 and the second storage electrode 40 are formed. In addition, the source and drain electrodes 48 and 53 contacting the first semiconductor layer 23, more specifically, the ohmic contact layer 23b formed by being doped in the first semiconductor layer 23 are disposed on the interlayer insulating layer 43. Formed. In this case, the drain electrode 53 extends long and part of the drain electrode 53 overlaps with the second storage electrode 40 to form the third storage electrode 55 by itself, and the interlayer insulating layer 43 is formed as a dielectric. As a result, a second storage capacitor StgC2 is formed together with the second storage electrode 40 below. Therefore, the first and second storage capacitors StgC1 and StgC2 are formed in a parallel structure.

Next, a passivation layer 60 is formed on the entire surface of the source and drain electrodes 48 and 53, the third storage electrode 55, and the exposed interlayer insulating layer 43, and a drain contact is formed on the passivation layer 60. The pixel electrode 65 is formed in contact with the third storage electrode 55 connected to the drain electrode 53 through the hole 63.

In the above-described conventional array substrate 15, first and second storage capacitors StgC1 and StgC2 are formed as parallel structures in order to improve the capacitance, and the regions in which the storage capacitors StgC1 and StgC2 are formed are Since the second and third storage electrodes 40 and 55 are formed of a metal material, light incident from a lower backlight (not shown) is blocked, thereby lowering the aperture ratio. There is a falling problem.

The reason why the storage capacitor should be formed in each pixel area in the array substrate is that in each pixel area, the voltage applied to the liquid crystal by one signal is kept constant at the pixel electrode to maintain a constant voltage state until the next signal is applied. This is because the storage capacitor plays a role in supplying a voltage. Therefore, in order to maintain a constant voltage for the pixel electrode in the pixel region for a predetermined time, a storage capacitor having a corresponding capacitance must be formed and reflect the array. An active region including a plurality of pixel regions in a substrate is designed. Accordingly, as shown in the drawing, a relatively wide portion of the pixel region is occupied by the storage electrode for forming the storage capacitor, and thus, the area of the opening may be relatively small.

Accordingly, an object of the present invention is to change the structure of a storage capacitor in an array substrate for a liquid crystal display device using polysilicon to form first and second storage electrodes made of polysilicon and a transparent conductive material which are light transmitting materials. Accordingly, an object of the present invention is to improve an aperture ratio and brightness by providing an array substrate for a liquid crystal display device having a structure that transmits light emitted from a lower portion to the storage capacitor region in a pixel region.

In order to achieve the above object, an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention includes a switching region in which a pixel region is defined by crossing gate lines and data lines, and a thin film transistor is formed in the pixel region, and a storage capacitor. A substrate on which a storage area in which is formed is defined; A semiconductor layer formed of polysilicon in the switching region on the substrate, and a first storage electrode formed in the storage region of the same material as the material of the semiconductor layer; A gate insulating layer having a storage electrode contact hole exposing a portion of the first storage electrode over the semiconductor layer and the first storage electrode; A common wiring formed over the gate insulating layer and in contact with the first storage electrode through the storage electrode contact hole; A gate electrode formed on the gate insulating layer and overlapping with a central portion of the semiconductor layer; An interlayer insulating film formed with a semiconductor layer contact hole exposing the semiconductor layers on both sides of the gate electrode over the gate electrode and the common wiring, and a first storage groove exposing a gate insulating film corresponding to the first storage electrode; Source and drain electrodes spaced apart from each other and in contact with the semiconductor layer through the semiconductor layer contact hole on the interlayer insulating film; A protective layer formed on the source and drain electrodes to expose the drain electrode and simultaneously have a second storage groove connected to the first storage groove to expose the gate insulating layer in the storage region; A pixel electrode contacting the drain electrode through the drain contact hole over the passivation layer, and a second storage electrode extending from the pixel electrode to a gate insulating layer exposed to the first and second storage grooves connected to each other; .

In this case, the first storage electrode is formed to be spaced apart from the semiconductor layer.

"), 기역자 형태("ㄱ"), 미러된 기역자 형태("┌"), 영문 대문자 에이치 형태("H"), 한글 모음 중 아형태("ㅏ") 또는 한글 모음 중 어형태("ㅓ") 중 하나의 형태로 형성된 것이 특징이다. In addition, the first storage electrode is formed in a vertical shape that rotates while being spaced apart from the gate line and the data line along an edge of the pixel area.

"), Translator form (" ㄱ "), mirrored translator form (" ┌ "), capital letter H form (" H "), subtypes of Korean vowels (" ㅏ "), or Korean forms of vowels (" ㅓ ") ") Is characterized by being formed in one of the forms.

In addition, the first and second storage grooves are formed in the entire pixel area except for the switching area.

In addition, the first storage electrode is characterized in that the conductive material containing a high amount of impurities.

The pixel electrode and the second storage electrode may be made of a transparent conductive material.

In addition, the semiconductor layer in contact with the source and drain electrodes, respectively, is characterized in that the ohmic contact layer containing an impurity amount of n + or p +.

In addition, a buffer layer is further formed between the semiconductor layer and the first storage electrode and the substrate.

In the method of manufacturing an array substrate for a liquid crystal display according to the present invention, a pixel region is defined by crossing gate lines and data lines, a switching region in which a thin film transistor is formed in the pixel region, and a storage region in which a storage capacitor is formed. Forming a semiconductor layer of polysilicon in the switching region on the substrate and a first storage electrode of the same material as the semiconductor layer in the storage region; Forming a gate insulating layer having a storage electrode exposed groove exposing the first storage electrode over the semiconductor layer and the first storage electrode; Forming a common wiring on the gate insulating layer in contact with a center of the semiconductor layer and in contact with a first storage electrode exposed through the storage electrode exposure groove; Forming an interlayer insulating film having semiconductor layer contact holes respectively exposing the semiconductor layers on both sides of the gate electrode over the gate electrode and the common wiring; Forming source and drain electrodes on the interlayer insulating layer, the source and drain electrodes being in contact with and spaced apart from each other; A storage groove for patterning the drain electrode and the drain contact hole in the switching area over the source and drain electrodes, and in the storage area, successively patterning an interlayer insulating film corresponding to the first storage electrode to expose a lower gate insulating film. Forming a protective layer; Forming a pixel electrode in contact with the drain electrode with a transparent conductive material over the passivation layer, and a second storage electrode extending to the storage area and overlapping the first storage electrode.

"), 기역자 형태("ㄱ"), 미러된 기역자 형태("┌"), 영문 대문자 에이치 형태("H"), 한글 모음 중 아형태("ㅏ") 또는 한글 모음 중 어형태("ㅓ") 중 하나의 형태로 형성되는 것이 바람직하다. In this case, the first storage electrode may be rotated apart from the gate line and the data line along an edge of the pixel area (").

"), Translator form (" ㄱ "), mirrored translator form (" ┌ "), capital letter H form (" H "), subtypes of Korean vowels (" ㅏ "), or Korean forms of vowels (" ㅓ ") It is preferably formed in the form of one of ").

The method may further include forming a photoresist pattern covering the semiconductor layer after forming the semiconductor layer and the first storage electrode; And performing storage doping of the first storage electrode by implanting a high amount of ions using the photoresist pattern as a doping mask.

In addition, after the gate electrode and the common electrode are formed, the gate electrode is used as a doping mask, and doping is performed by ion implantation of a high dose of n + or p + into a semiconductor layer region other than the region overlapping the gate electrode. And forming a semiconductor layer as a doped ohmic contact layer and an undoped active layer between the ohmic contact layer.

Hereinafter, an array substrate for a liquid crystal display device using polysilicon according to an embodiment of the present invention and a method of manufacturing the same will be described with reference to the drawings.

FIG. 4 is a plan view illustrating one pixel area of an array substrate for a liquid crystal display device using polysilicon according to an exemplary embodiment of the present invention, and FIGS. 5 and 6 show cut lines VV and VI-VI, respectively. It is a cross section which cut along. For convenience of description, a region where a thin film transistor as a switching element is to be formed in each pixel region is defined as a switching region TrA and a region where a storage capacitor is to be formed as a storage region StgA.

First, referring to FIG. 4, which shows a planar structure in a pixel region, as shown in FIG. The gate wiring 125 intersects with the gate wiring 125 in the direction, and the data wiring 145 is formed in the vertical direction.

"형태로 형성된 제 1 스토리지 전극(114)과 중첩하며 접촉하며 형성된 것이 특징이다. In addition, the common wiring 130 has the same wiring width and is spaced apart from the gate wiring 125 by a predetermined distance in parallel with the gate wiring 125. In this case, a part of the common wiring 130 is formed of the same material on the same layer when the semiconductor layer 110 of polysilicon is formed, and the data wiring 145 on both sides of the pixel region P and the two data wiring 145. The upper gate wiring 125 that crosses the inner side of the pixel region P is surrounded by a circular shape, that is, "

And overlapping and in contact with the first storage electrode 114 formed in the form.

In this case, the line width of the first storage electrode 114 connected to the common wiring 130 and formed in the shape of a recess rotated in the pixel area P may be formed differently according to the capacitance of the storage capacitor. One of the first storage electrode portions 114b and 144c formed in parallel with the data line 145 is omitted except for the first storage electrode portion 114a which overlaps and contacts the wiring 130. And as shown in Figure 8, it can be formed in the form of 'translator (a)' or 'mirror mirrored (┌)'. Although not shown in the drawing, as a modification, the common wiring may be formed to cross the central portion of the pixel region, as shown in FIG. 4. In this case, the first storage electrode may be 'H'. Form or '├' or '┤' shape.

Also, a thin film transistor Tr, which is a switching element, is formed at a portion where the gate and the data lines 125 and 145 cross each other. In this case, the thin film transistor Tr may include a source electrode 147 branched from the data line 145, a drain electrode 149 spaced apart from the source electrode 147 by a predetermined interval, and the gate electrode 127. The source and drain electrodes 147 and 149 are in contact with the semiconductor layer 110 through the semiconductor layer contact holes 137 and 139. In this case, a portion of the semiconductor layer 110 also overlaps with the gate electrode 127.

Next, except for the source electrode 147 and the gate electrode 127 of the thin film transistor Tr as a transparent conductive material, the drain region 149 and the drain contact hole 157 are formed in the pixel region P. The pixel electrode 165 is formed in contact with each other, and a portion of the pixel electrode 165 overlapping with the first storage electrode 114 formed along the edge of the pixel area P is the second storage electrode. It is characterized by forming 167.

Next, a cross-sectional structure of an array substrate for a liquid crystal display device according to the present invention will be described with reference to FIGS. 5 and 6.

5 and 6, a buffer layer 105 is formed on the substrate 101, and a polysilicon semiconductor layer 110 is formed in the switching region TrA on the buffer layer 105. In the storage area StgA, a first storage electrode 114 made of the same material, that is, polysilicon, in which the semiconductor layer 110 is formed in the form of a digital device in which the pixel area P is rotated, is formed. In this case, the semiconductor layer 110 and the first storage electrode 114 are formed by being disconnected without contacting each other in the pixel region P. FIG. At this time, the portion of the semiconductor layer 110 corresponding to the gate electrode 127 formed on the upper portion of the active layer 110a made of pure polysilicon, which is not doped, and a high amount of ions on both sides of the active layer 110a The n + or p + doped ohmic contact layer 110b is formed by implantation, and the first storage electrode 114 is storage-doped and conductorized by ion implantation having a high dose.

In addition, although not shown in the drawing, when the ohmic contact layer 110b is n + doped between the ohmic contact layer 110b and the active layer 110a to form an n-type ohmic contact layer, a hot carrier An n-doped LDD layer (not shown) may be further formed between the active layer 110a and the ohmic contact layer 110b by the ion implantation of low dose to prevent deterioration by the ion.

Next, a gate insulating layer 117 is formed on the semiconductor layer 110 and the first storage electrode 114. In this case, the gate insulating layer 117 is parallel to the gate wiring 125 in a plan view of the first storage electrode 114. For example, the gate insulating layer 117 may be removed from a portion of the portion formed in the pixel region P to have the storage electrode contact hole 120 exposing the first storage electrode 114.

Next, the gate wiring 125, which is an element defining the pixel region P, is formed on the gate insulating layer 117 by being spaced apart from each other in the horizontal direction by a predetermined distance from each gate wiring 125. The common wiring 130 is formed to be in contact with the first storage electrode 114 exposed by removing a portion of the gate insulating layer 117 and to be parallel to the gate wiring 125.

In the switching region TrA, a gate electrode 127 branched from the gate line 125 is partially overlapped with the semiconductor layer 110 with the gate insulating layer 117 interposed therebetween.

Next, an interlayer insulating layer 135 is formed on the gate wiring 125, the gate electrode 127, and the common wiring 130. In this case, the active layer (eg, the active layer) is formed in the switching region TrA of the interlayer insulating layer 135. Semiconductor layer contact holes 137 and 139 are formed to expose the respective ohmic contact layers 110b separated by the 110a.

Next, the data lines 145 defining the pixel regions P are formed on the interlayer insulating layer 135 to be spaced apart from each other by a predetermined distance, and in the switching region TrA. Branched from the data line 145 to contact the underlying ohmic contact layer 110b through the semiconductor layer contact hole 137 to form a source electrode 147, spaced apart from the source electrode 147 by a predetermined interval A drain electrode 149 is formed in contact with the ohmic contact layer 110b through another semiconductor layer contact hole 139.

Next, a passivation layer 155 is formed on the source and drain electrodes 147 and 149 and the data line 145. In this case, the passivation layer 155 is disposed in the switching region TrA. ) Is provided, and a drain contact hole 157 is provided. The gate insulating layer 117 corresponding to the first storage electrode 114 is etched by including the lower interlayer insulating layer 135 in the storage region StgA. The storage groove 159 is formed to expose the.

Next, a pixel electrode 165 is formed on the passivation layer 155 to be independent of each pixel region P and is in contact with the drain electrode 149 through the drain contact hole 157. In this case, the protective layer 155 and the interlayer insulating layer 135 of the pixel electrode 165 are removed, and the pixel electrode 165 formed in the portion of the storage groove 159 exposing the lower gate insulating layer 117 is formed. A second storage electrode 167 is formed to correspond to the lower first storage electrode 114 and the storage capacitor StgC is formed in addition to the gate insulating layer 117 thereon, which serves as the dielectric layer and the first storage electrode 114. ) Is characteristic.

In the embodiment of the present invention, in the storage region StgA, the first storage electrode 114 is made of polysilicon forming the semiconductor layer 110, and the second storage electrode 167 is formed of the pixel electrode 165. It is characterized by the fact that the polysilicon and the transparent conductive material transmits light by forming it as a transparent conductive material, and thus, although not shown in the drawing, when the liquid crystal display device is completely configured, incident from a backlight disposed below the array substrate is performed. Since light can pass through the storage region StgA, the aperture ratio is improved, thereby improving the luminance.

In addition, the interlayer insulating layer 135 and the protective layer 155 may be removed between the first storage electrode 114 and the second storage electrode 167 to form a gap between the first and second storage electrodes 114 and 167. It is another feature to increase the storage capacity of the storage capacitor (StgC) by forming a thinner.

In the above-described embodiment, the protective layer 155 and the interlayer insulating film 135 are removed only in the storage region StgA. However, as a modification of the embodiment of the present invention, FIGS. As illustrated, the protective layer 455 and the interlayer insulating film 435 may be removed in the entire pixel area P, including the storage area StgA, except for the switching area TrA. . In this case, it is preferable that the gate insulating layer 417 is formed of an inorganic insulating material, and the interlayer insulating layer 435 and the protective layer 455 formed thereon are formed of an organic insulating material to facilitate uniformity during the etching process. .

Although not shown in the drawings, as another modification, the protective layer and the interlayer insulating film may be formed on the entire surface of the substrate as in the related art. In this case, in the storage area, both the gate insulating film, the interlayer insulating film, and the protective layer are formed between the first and second storage electrodes, so that the gap between the first and second storage electrodes is equal to that of the embodiment of the present invention. Although the storage capacity of the storage capacitor is smaller than that of the case formed only, the modified example can be sufficiently applied depending on the model of the liquid crystal display device.

Next, a method of manufacturing an array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 11A to 11I and 12A to 12I.

11A to 11H are cross-sectional views illustrating a manufacturing process of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a portion cut along the cutting line V-V. 12h is a cross sectional view of the production process of the portion taken along the line VI-VI of FIG. 4.

First, as shown in FIGS. 11A and 12A, a buffer layer 105 is formed by depositing silicon nitride (SiNx) or silicon oxide (SiO ₂ ), which is an inorganic insulating material, on the transparent insulating substrate 101. When the amorphous silicon is recrystallized from polysilicon, the buffer layer 105 is formed of alkali ions, for example, potassium ions (K +) and sodium ions, which are present in the substrate 101 due to heat generated by laser irradiation or heat treatment. (Na +) and the like may occur, in order to prevent the film properties of the semiconductor layer made of polysilicon from being deteriorated by such alkali ions. In this case, the buffer layer 105 may be omitted.

Next, amorphous silicon is deposited on the buffer layer 105 to form an amorphous silicon layer (not shown), and an Excimer Laser Annealing (ELA) method or a sequential lateral solidification (SLS) crystallization method or heat treatment method using an excimer laser or A crystallization process such as metal induced lateral crystallization (MIL) is performed to crystallize the amorphous silicon layer (not shown) into a polysilicon layer (not shown). Thereafter, the polysilicon layer (not shown) is patterned by performing a mask process including a series of processes such as application of a photoresist, exposure using a mask, development, and etching of a material layer to be patterned, thereby switching region TrA. The first semiconductor layer 110 of polysilicon is formed, the second semiconductor layer 113 is formed in the storage region StgA, and the lower buffer layer 105 is exposed by removing it in the other regions. . In this case, it can be seen that the first semiconductor layer 110 and the second semiconductor layer 113 are in a broken state.

In addition, in the above-described process, the amorphous silicon layer (not shown) is crystallized with a polysilicon layer (not shown) and then patterned to form the first and second semiconductor layers 110 and 113, but the amorphous silicon layer Is first patterned to form first and second amorphous silicon patterns (not shown) having the same shape as the first and second semiconductor layers 110 and 113 of polysilicon described above, and then the first and second amorphous silicon patterns The first and second semiconductor layers 110 and 113 of the same type of polysilicon as described above may be formed by performing a crystallization process (not shown).

Next, as shown in FIGS. 11B and 12B, a photoresist is coated on the entire surface of the first and second semiconductor layers 110 and 113 formed in the switching region TrA and the storage region StgA, and the photoresist is exposed. And developing to form the photoresist pattern 181 in the switching region TrA. In this case, since the photoresist pattern 181 is not formed in the storage region StgA, the second semiconductor layer 113 is exposed to the outside.

Subsequently, the photoresist pattern 181 is used as a doping mask to conduct storage doping of n + or p + by ion implantation at a high dose, thereby conducting the second semiconductor layer 113 formed in the storage region StgA to be conductive. The first storage electrode 114 of the polysilicon is formed.

Next, as shown in FIGS. 11C and 12C, the photoresist pattern (181 of FIG. 11B) remaining on the substrate 101 on which the first storage electrode 114 is formed is stripped and removed. The gate insulating layer 117 is deposited on the entire surface of the first semiconductor layer 110 (hereinafter referred to as a semiconductor layer) and the first storage electrode 114 by depositing an inorganic insulating material (SiO ₂ ) or silicon nitride (SiNx). To form.

Subsequently, a mask process is performed on the gate insulating layer 117 so that the substrate 101 may be parallel with the gate wiring 125 of FIG. 11D formed in a later process of the first storage electrode 114 in the storage region StgA. A first storage electrode exposing groove 120 exposing a portion of the portion (114a of FIG. 4, which is a plan view) formed in the horizontal direction on the top is formed. This is for contact with the common wiring (130 of FIG. 11D) formed in a later process.

Next, as illustrated in FIGS. 11D and 12D, a metal material is deposited on the entire surface of the gate insulating layer 117 and the exposed first storage electrode 114 to form a metal layer (not shown). Proceeding to form a plurality of gate wiring 125 spaced apart from each other in the horizontal direction over the gate insulating film 117, at the same time branching from the gate wiring 125 in the switching region (TrA) for each pixel region (P) One gate electrode 127 is formed. In addition, the common wiring 130 is formed on the gate insulating layer 117 and the exposed first storage electrode 114 to be spaced apart from the gate wiring 125 by a predetermined distance in parallel with the gate wiring 125. In this case, the common wiring 130 contacts the portion 114a of the lower first storage electrode 114 parallel to the gate wiring through the first storage electrode exposed groove 120 formed in the gate insulating layer 117. This is a characteristic aspect of the present invention.

Next, as shown in FIGS. 11E and 12E, n + or p + doping through ion implantation having a high dose is performed on the first semiconductor layer 110 using the gate electrode 127 as a doping mask. An ohmic contact layer 110b is formed in the layer 110. In this case, an area of the semiconductor layer 110 that is not doped by the gate electrode 127 forms an active layer 110a. In this case, the doping for forming the ohmic contact layer 110b is preferably performed in the same series as the storage doping for forming the first storage electrode 114. That is, when the storage doping is n + doping, the doping degree for forming the ohmic contact layer 110b may be n + doping, and when the storage doping is p + doping, the doping degree for forming the ohmic contact layer 110b. p + doping may be performed. However, by varying the dose, that is, the storage doping and the doping for forming the ohmic contact layer may be doping having different properties.

In addition, although not shown in the drawing, in the case of configuring a CMOS-type inverter in the driving circuit section, both n + and p + doping should be performed. In this case, when n + doping is performed, p + is doped to form a p-type ohmic contact layer. After the doping mask is formed with a photoresist or the like on the semiconductor layer of the portion where the P-type thin film transistor having to be formed is n + doped, on the contrary, when p + doping, the n-type thin film transistor is formed on the portion After the doping mask is formed of a photoresist or the like, the n-type and p-type ohmic contact layers may be formed by performing p + doping.

Although not shown in the drawing, when the n-type ohmic contact layer is formed by n + doping, between the active layer 110a under the gate electrode 127 and the ohmic contact layer 110b on each side of the active layer 110a. It is desirable to further form a lightly dopped drain (LDD) layer (not shown) that is doped with a low dose.

Next, as illustrated in FIGS. 11F and 12F, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), which is an inorganic insulating material, is formed on the entire surface of the gate electrode 127, the gate wiring 125, and the common wiring 130. Or an benzocyclobutene (BCB) or photo acryl, which is an organic insulating material, is deposited to form an interlayer insulating film 135.

Next, the interlayer insulating layer 135 is patterned by performing a mask process to expose the ohmic contact layer 110b positioned at both sides of the active layer 110a in the switching region TrA. 137, 139). At this time, in the storage area StgA, the interlayer insulating layer 135 is formed without being removed.

 Next, as illustrated in FIGS. 11G and 12G, a metal material is deposited on the entire surface of the interlayer insulating layer 135 including the semiconductor layer contact holes 137 and 139, and patterned by performing a mask process. A data line 145 is formed on the insulating layer 135 to intersect the gate line 125 below and defines the pixel area P. At the same time, in the switching area TrA of each pixel area P, the data line 145 is formed. A source electrode 147 which is branched from the data line 145 and contacts the ohmic contact layer 110b through the semiconductor layer contact hole 137, and is spaced apart from the source electrode 147, and another semiconductor layer contact A drain electrode 149 is formed to contact the ohmic contact layer 110b through the hole 139.

Next, as shown in FIGS. 11H and 12H, silicon nitride (SiNx) or silicon oxide (SiO ₂ ), which is an inorganic insulating material, is deposited on the entire surface of the data line 145 and the source and drain electrodes 147 and 149. Alternatively, the protective layer 155 may be formed by applying benzocyclobutene (BCB) or photo acryl, which is an organic insulating material, and patterning the protective layer 155 by performing a mask process. A drain contact hole 157 is formed to expose the drain electrode 149, and at the same time, in the storage area StgA, the protective layer 155 and the lower portion of the protective layer 155 corresponding to the first storage electrode 114 are formed. The interlayer insulating layer 135 is continuously or collectively etched to form the gate insulating layer exposing groove 159 exposing the lower gate insulating layer 117. In this case, only the passivation layer 155 is removed from the drain contact hole 157 forming portion, and the interlayer insulating layer 135 including the passivation layer 155 is formed in the forming portion of the gate insulating layer exposing groove 159. Since the drain electrode 149 exposed by the drain contact hole 157 is a metal material, the drain electrode 149 is a metal material and thus does not react to the etching liquid for etching the inorganic insulating material or the organic insulating material. Even if it is etched and subsequently exposed to an etchant that can etch the lower interlayer insulating film 135, there is no problem because it does not occur.

In the exemplary embodiment of the present invention, the gate insulating layer exposed grooves 159 are formed by collectively or continuously etching the protective layer 155 and the interlayer insulating layer 135 under the protective layer 155. However, as a modified example, when the semiconductor layer contact hole is formed in the interlayer insulating layer, a first exposure groove is formed in the region to expose the gate insulating layer, and when the drain contact hole is formed in the protective layer, the first exposure groove is formed in the interlayer insulating layer. It may be formed by patterning a corresponding portion to form a second exposed groove connected to the first exposed groove to expose the gate insulating film. In this case, when the protective layer uses a photosensitive organic insulating material, the above-described gate insulating film exposed grooves may be formed in the developing step without an etching process.

Next, as shown in FIGS. 11I and 12I, in the switching region TrA, the drain contact hole 157 has a protective layer in which the gate insulating film exposing groove 159 is formed in the storage region StgA. 155) Indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material on the front surface, is deposited on the front surface, and patterned by performing a mask process, through the drain contact hole 157 through the drain electrode. A pixel electrode 165 in contact with 149 is formed. In this case, a portion of the pixel electrode 165 corresponding to the gate insulating layer exposed groove 159 forms the second storage electrode 167.

Accordingly, in the storage region StgA, the first storage electrode 114 made of a polysilicon semiconductor layer, the gate insulating film 117, and the gate insulating film (top) of the first storage electrode 114 are formed. 117 A second storage electrode 167 made of a transparent conductive material forming the pixel electrode 165 is formed thereon, and the first and second storage electrodes 114 and 167 transmit light to thereby open the aperture ratio. The present invention provides an array substrate for a liquid crystal display device capable of improving luminance and luminance.

As described above, in an array substrate for a liquid crystal display device using polysilicon according to an exemplary embodiment of the present invention, in a storage capacitor formed in a pixel region, each of the first storage electrodes constituting the storage capacitor may be formed along the edge of the pixel region. And forming a second storage electrode as a transparent conductive material for forming the pixel electrode in the step of forming the pixel electrode by forming the semiconductor layer material in the layer on which the layer is formed. There is an effect of improving the aperture ratio and the brightness.

Claims (12)

A substrate in which a pixel region is defined by crossing gate lines and data lines, a switching region in which a thin film transistor is formed, and a storage region in which a storage capacitor is formed; A semiconductor layer formed of polysilicon in the switching region on the substrate, and a first storage electrode formed in the storage region of the same material as the material of the semiconductor layer; A gate insulating film having a storage electrode contact hole exposing the first storage electrode over the semiconductor layer and the first storage electrode; A common wiring formed over the gate insulating layer and in contact with the first storage electrode through the storage electrode contact hole; A gate electrode formed on the gate insulating layer and overlapping with a central portion of the semiconductor layer; An interlayer insulating film formed with a semiconductor layer contact hole exposing the semiconductor layers on both sides of the gate electrode over the gate electrode and the common wiring, and a first storage groove exposing a gate insulating film corresponding to the first storage electrode; Source and drain electrodes spaced apart from each other and in contact with the semiconductor layer through the semiconductor layer contact hole on the interlayer insulating film; A protective layer formed on the source and drain electrodes to expose the drain electrode and at the same time having a second storage groove connected to the first storage groove to expose the gate insulating layer in the storage region; A second storage electrode formed on the passivation layer, the pixel electrode contacting the drain electrode through the drain contact hole, and a second storage electrode extending from the pixel electrode to a gate insulating layer exposed to the first and second storage grooves connected to each other; Array substrate for a liquid crystal display device comprising a. The method of claim 1, And the first storage electrode is spaced apart from the semiconductor layer. The method of claim 1, The first storage electrode may be formed to rotate in space with the gate line and the data line along an edge of the pixel area.

"), Translator form (" ㄱ "), mirrored translator form (" ┌ "), capital letter H form (" H "), subtypes of Korean vowels (" ㅏ "), or Korean forms of vowels (" ㅓ ") ") An array substrate for a liquid crystal display device formed in one of the forms. The method of claim 1, And the first and second storage grooves are formed in an entire area of the pixel area other than the switching area. The method of claim 1, And the first storage electrode is electrically conductive including a high amount of impurities. The method of claim 1, And the pixel electrode and the second storage electrode are made of a transparent conductive material. The method of claim 1, And the semiconductor layer in contact with the source and drain electrodes, respectively, is an ohmic contact layer containing n + or p + highly doped impurities. The method of claim 1, And a buffer layer formed between the semiconductor layer and the first storage electrode and the substrate. A semiconductor layer of polysilicon is formed in the switching region on the substrate on which the pixel region is defined by crossing the gate wiring and the data wiring, the thin film transistor is formed in the pixel region, and the storage region in which the storage capacitor is formed. Forming a first storage electrode on the storage area using the same material as the semiconductor layer; Forming a gate insulating layer having a storage electrode exposed groove exposing the first storage electrode over the semiconductor layer and the first storage electrode; Forming a common wiring on the gate insulating layer in contact with a center of the semiconductor layer and in contact with a first storage electrode exposed through the storage electrode exposure groove; Forming an interlayer insulating film having semiconductor layer contact holes respectively exposing the semiconductor layers on both sides of the gate electrode over the gate electrode and the common wiring; Forming source and drain electrodes on the interlayer insulating layer, the source and drain electrodes being in contact with and spaced apart from each other; A storage groove for patterning the drain electrode and the drain contact hole in the switching area over the source and drain electrodes, and in the storage area, successively patterning an interlayer insulating film corresponding to the first storage electrode to expose a lower gate insulating film. Forming a protective layer; Forming a pixel electrode on the protective layer, the pixel electrode contacting the drain electrode with a transparent conductive material, and the second electrode extending from the pixel electrode to the storage area and overlapping the first storage electrode; Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 9, The first storage electrode may be formed to rotate in space with the gate line and the data line along an edge of the pixel area.

"), Translator form (" ㄱ "), mirrored translator form (" ┌ "), capital letter H form (" H "), subtypes of Korean vowels (" ㅏ "), or Korean forms of vowels (" ㅓ ") The manufacturing method of the array substrate for liquid crystal display devices formed in one form of "). The method of claim 9, After the semiconductor layer and the first storage electrode are formed Forming a photoresist pattern covering the semiconductor layer; And performing a storage doping of the first storage electrode by implanting a high amount of ions using the photoresist pattern as a doping mask. The method of claim 9, After forming the gate electrode and the common electrode An ohmic contact layer doped with the semiconductor layer by doping by ion implantation having a high amount of n + or p + in a semiconductor layer region other than the region overlapping the gate electrode using the gate electrode as a doping mask, and the ohmic contact A method of manufacturing an array substrate for a liquid crystal display device comprising the step of forming an undoped active layer between layers.

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