KR101315501B1 - LCD and driving methode of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a driving method capable of reducing power consumption and minimizing an area of a capacitor, and to a structure of an array substrate for a liquid crystal display device.

A feature of the present invention is a method of driving an array substrate for a liquid crystal display device comprising a storage capacitor with a polycrystalline active layer as a first electrode and a storage wiring as a second electrode, the level of the storage voltage input to the storage wiring. Increase the storage inversion.

In this case, at this time, the voltage level input to the storage wiring is characterized in that it can be activated without doping the polycrystalline active layer dopant.

Therefore, the doping process can be omitted by activating the polycrystalline active layer that is not doped by the storage voltage applied to the storage wiring, and the storage capacity can be further secured, thereby reducing the storage area compared to the same capacity, thereby improving the aperture ratio. There are advantages to it.

Description

LCD and driving method {LCD and driving methode of the same}

1A is an enlarged plan view illustrating one pixel of an array substrate for a liquid crystal display device according to a first example of the related art;

FIG. 1B is a cross-sectional view taken along II-II of FIG. 1A;

2A and 2B are diagrams illustrating an equivalent circuit and a driving waveform according to the conventional LCD according to the related art.

3A is an enlarged plan view of a portion of an array substrate for a liquid crystal display device according to a second example of the related art, and FIG. 3B is a cross-sectional view taken along line III-III of FIG. 3A,

4A and 4B are diagrams showing an equivalent circuit and a driving waveform of a liquid crystal panel driven by a storage line inversion method,

5 illustrates a storage inversion driving waveform according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

Vst1, Vst2: Storage Voltage Vp1, Vp2: Pixel Voltage

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device. In particular, while driving a storage voltage while forming a vertical electric field, driving power is reduced, and the storage voltage of the storage storage capacitor is increased to thereby increase storage capacity. Accordingly, the present invention relates to reducing the area of the storage capacitor to enlarge the opening area of the liquid crystal display.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal.

The liquid crystal has an elongated shape, has directivity in the arrangement of molecules, and can control the direction of the molecular arrangement by applying an electric field to the liquid crystal artificially.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal by optical anisotropy to express an image.

The liquid crystal display includes a color filter substrate (upper substrate) on which a common electrode is formed, an array substrate (lower substrate) on which a pixel electrode is formed, and a liquid crystal filled between upper and lower substrates. The liquid crystal is driven by an electric field applied up and down by the pixel electrode, so that the characteristics such as transmittance and aperture ratio are excellent.

Currently, an active matrix liquid crystal display (AM-LCD: Active Matrix LCD) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner is attracting the most attention because of its excellent resolution and video performance.

1A is an enlarged plan view of a single pixel of a general array substrate for a liquid crystal display device, and FIG. 1B is a cross-sectional view taken along II-II of FIG. 1A. FIG. 1 is an example of using a polycrystalline thin film transistor as a switching element. to be)

As illustrated, in the array substrate 10 for a liquid crystal display device according to the present invention, the gate line 12 is formed in one direction, and the data line 30 is formed in a direction crossing the gate line 12. . A region defined by the crossing of the two wires 12 and 30 is referred to as a pixel region P.

The storage wiring 16 is configured to be spaced apart in parallel with the gate wiring 12.

The polycrystalline thin film transistor T including the polycrystalline active layer 20, the gate electrode 14, the source electrode 24, and the drain electrode 26 at the intersection of the gate wiring 12 and the data wiring 30. Is composed.

A storage capacitor Cst is formed in the pixel region P. The first electrode of the storage capacitor Cst is the first expansion part 18 extending the storage wiring 16, and the storage capacitor Cst. ) Is a second extension 28 extending from the drain electrode 26 to the upper portion of the first extension 18 with the gate insulating film 22 therebetween.

Although not shown, the array substrate for the liquid crystal display device configured as described above is combined with a color filter substrate including a color filter, a black matrix, and a common electrode, thereby forming a liquid crystal panel. .

Hereinafter, the driving method of the liquid crystal panel according to the first example will be described with reference to the driving circuit showing the equivalent circuit diagram and the line inversion method of FIGS. 2A and 2B.

As shown in FIG. 2A, the liquid crystal panel includes a plurality of gate lines GL1, GL2, GL3, and data lines DL1, DL2, DL3 perpendicular to the gate lines GL1, GL2, GL3. The pixel P is defined for each region where the two wires intersect.

The pixel P includes thin film transistors T and P, a pixel electrode in contact with the thin film transistor T, a common electrode, and a liquid crystal capacitor Clc formed by a liquid crystal layer therebetween. The storage capacitor Cst is configured in parallel with the liquid crystal capacitor.

In this case, as described with reference to FIGS. 1A and 1B, the first electrode of the storage capacitor Cst is a first expansion unit 26 that receives a signal from the drain electrode 24 of FIG. 1A of the thin film transistor T. The second electrode is the second extension 18 extending from the storage wiring 16 through which the same common signal as the common electrode (not shown) flows.

The liquid crystal panel configured as described above is driven by an inversion method of inversion of the polarity of the liquid crystal cell by a predetermined unit in order to prevent degradation of the liquid crystal and to improve display quality.

The inversion method may include a frame inversion in which the polarity of the liquid crystal cell is inverted in units of frames, a column inversion in which the polarity of the liquid crystal cell is inverted in units of vertical lines, and a unit of liquid crystal cells. There is a dot inversion in which the polarity of the liquid crystal cell is inverted.

Among these, the line inversion method of inverting the polarity of the liquid crystal cell in the horizontal line unit is advantageous in terms of power consumption compared to the column inversion and dot inversion methods.

Fig. 2B is a waveform diagram showing an example of the line-in version in which the common signal is AC-driven. (The P-type thin film transistor is an example.)

As illustrated, the signals driving the liquid crystal panel are gate high and low signals V _gh and V _gl flowing through the gate lines GL1, GL2, and GL3, and data signals flowing through the data lines by the gate signals. A common signal Vcom which simultaneously flows through V _d , the common wirings COM1, COM2, and COM3, and the storage wirings GL1, GL2, and GL3.

In this case, the gate lines GL1, GL2, and GL3 apply the gate high signal V _gh for the corresponding period, and apply the gate low signal V _{gl for the} remaining period, and the data signal V _d The signal is supplied to the pixel P according to the gate high signal V _gh , and is maintained by the liquid crystal capacitor Clc even when the next gate low signal V _gl is obtained.

In this case, the characteristic is to lower the driving voltage range of the data signal V _d by driving the common signal Vcom supplied to the liquid crystal cell as a reference voltage.

That is, when the common voltage Vcom is AC-driven, the pulse width of the common signal Vcom is moved up and down compared to the existing dot inversion, so that the pulse of the data signal V _d is as much as that. The width, i.e., the swing width of the data is reduced, and therefore, the power consumption can be lowered.

However, since the conventional first structure has to be driven at a high frequency by not only a liquid crystal capacitor but also a large resistance component such as a storage capacitor Cst, the power consumption is increased. There is a disadvantage that the reduction is small.

Accordingly, in the configuration of FIG. 1A, since the signal applied to the storage line 16 is varied to increase the capacity of the storage capacitor (Cst of FIGS. 1B and 2A), the first and the first and the storage capacitors Cst may be limited. The area of the second electrode had to be increased, and as a result, there was a problem that the opening area was encroached.

In order to solve this problem structurally, when forming the storage capacitor in the structure of the array substrate of FIG. 1, a structure in which two storage capacitors are configured in parallel has been proposed.

3A is an enlarged plan view of a portion of an array substrate for a liquid crystal display device according to a second conventional example, and FIG. 3B is a cross-sectional view taken along line III-III of FIG. 3A.

As illustrated, in the array substrate 10 for a liquid crystal display device according to the present invention, the gate line 12 is formed in one direction, and the data line 30 is formed in a direction crossing the gate line 12. . A region defined by the crossing of the two wires 12 and 30 is referred to as a pixel region P.

The storage wiring 16 is configured to be spaced apart in parallel with the gate wiring 12.

The polycrystalline thin film transistor T including the polycrystalline silicon layer ACT, the gate electrode 14, the source electrode 24, and the drain electrode 26 at the intersection of the gate wiring 12 and the data wiring 30. Is composed.

A storage capacitor Cst is formed in a portion of the pixel region P. The first electrode of the storage capacitor Cst is a polycrystalline silicon layer ACT doped with impurities on a surface thereof, and the second electrode is the storage wiring. A first extension 18 extending 16, the second electrode extending from the drain electrode 26 to the first extension 18 and contacting the polycrystalline active layer ACT, which is the first electrode; Is a second extension 28.

In this case, an insulating film 34 exists between the polycrystalline active layer ACT and the first extension part 18 and between the first extension part 18 and the second extension part 28 to be used as a dielectric material. do.

Such a configuration has an effect of increasing the auxiliary capacity due to the parallel connection of the storage capacitors Cst, and thus has an advantage of reducing the area of the storage capacitor, but doping impurities into the polycrystalline silicon layer. This has the disadvantage of requiring an additional mask process.

The present invention has a first object of reducing power consumption by realizing storage line inversion in a vertical field type liquid crystal display, and simultaneously increasing the level of the storage voltage (Vstg) to be used as a first electrode of the storage capacitor. The second object is to omit the doping step by activating the surface of the polycrystalline active layer. The third object is to further secure the storage capacity and to reduce the storage area to the same capacity to improve the aperture ratio.

In order to achieve the above object, the liquid crystal display according to the present invention comprises: a gate wiring and a data wiring formed on the substrate in a horizontal crosswise direction; A polycrystalline thin film transistor configured at an intersection point of the gate line and the data line; A storage wiring configured to be parallel to the gate wiring; A storage capacitor including the storage wiring as a first electrode, a undoped polycrystalline active layer formed under the first electrode as a second electrode, and a drain electrode in contact with the second electrode as a third electrode; do.

The above-described method for driving a liquid crystal display device includes applying a gate signal to the gate wiring; Alternately applying a storage voltage to the storage wiring; A thin film transistor is turned on by the gate signal, and a data signal is input to the drain electrode in the data line; The surface of the active layer is activated by the input storage voltage, the same signal is applied to the third electrode and the polycrystalline active layer, and the storage capacitor is charged to the storage capacitor.

In this case, when the thin film transistor is P-type, the low value of the storage voltage that can activate the surface of the polycrystalline active layer is -4V ~ -8V, the high value is -8V ~ -12V, characterized in that the thin film When the transistor is N-type, the low value of the storage voltage that can be activated on the surface of the polycrystalline active layer is 4V ~ 12V, the high value is characterized in that 12V ~ 16V.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

4A and 4B are equivalent circuit diagrams and waveform diagrams of a liquid crystal panel driven by a storage line inversion method.

As shown in FIG. 4A, a liquid crystal panel includes a plurality of gate lines GL1, GL2, and GL3, and data lines DL1, DL2, and DL3 that vertically cross the gate line, and the two lines cross each other. Pixels P1, P2, P3, and P4 are defined for each region.

The pixels P1, P2, P3, and P4 include a thin film transistor T, a pixel electrode in contact with the thin film transistor T, a common electrode, and a liquid crystal capacitor Clc formed by a liquid crystal layer therebetween. The storage capacitor Cst is configured in parallel with the liquid crystal capacitor Clc.

Referring to FIG. 3B, the configuration of the storage capacitor Cst is a first extension 26 receiving a signal from the drain electrode of the thin film transistor T, and the second electrode is the storage line SL1, The second extension 18 receives a signal from SL2, SL3.

Referring to the storage inversion driving through the above configuration, when the storage voltage is increased on the storage lines SL1, SL2, and SL3, the voltage of the pixel electrode in the floating state is increased by the storage capacitor Cst. Accordingly, the voltage charged in the liquid crystal capacitor Clc sharing the storage capacitor and the pixel electrode (drain electrode) increases.

As a result, when the storage voltage supplied to the storage voltage is varied, it can be seen that the voltage charged in the liquid crystal capacitor Clc can be varied by the coupling action of the storage capacitor Cst.

By using this, when the storage voltage is AC driven, it is possible to invert the polarity of the voltage charged in the liquid crystal capacitor.

The driving scheme of the above-described storage inversion through the driving waveform of FIG. 4B will be described in more detail as follows.

First, the first and second pixels P1 and P2 are connected to the first data line DL1 by the turn-on voltage supplied to the first gate line GL1 during the first horizontal period H1. from it charged with a positive first pixel voltage (Vp1) according to the supplied positive data signal (V _d).

In this case, the first storage voltage Vst is applied to the first storage line SL1.

In this case, the first storage line SL1 is raised to the second storage voltage Vst2 greater than the first storage voltage Vst1 in the third horizontal period H3 and supplied to the second horizontal period of the next frame. The second storage line ST2 is supplied from the fourth horizontal period to the first storage voltage until the third storage period of the next frame.

Accordingly, the positive first pixel voltage Vp1 charged to the first pixel voltage is increased to the second pixel voltage Vp2 by the coupling action of the storage capacitor so that the data signal is supplied in the first horizontal period of the next frame. It is held until it is.

The negative first pixel voltage -Vp1 charged in the third pixel and the fourth pixel P3 and P4 connected to the second gate line GL2 is lowered to the second pixel voltage -Vp2. It is held until the data signal V _d is supplied in the second horizontal period H2 in the second horizontal period of the frame.

Accordingly, the first pixel and the third pixel p1 and p3 implement grayscales according to the positive and negative pixel voltages Vp2 and -Vp2.

As described above, the liquid crystal panel varies the storage voltage supplied to the storage lines SL1, SL2, and SL3 so that the pixel voltage is varied, thereby reducing the voltage range of the data signal and inverting the polarity of the pixel voltage in units of horizontal lines. It can be driven by the storage line inversion method.

Therefore, since the voltage range of the data signal can be reduced, the power consumption can be reduced.

In the above driving type, when the level of the storage voltage is increased, the surface of the polycrystalline active layer ACT used as the first electrode of the storage capacitor in the aforementioned configuration of FIGS. 3A and 3B can be activated.

That is, when a high level storage voltage Vst is applied to the storage wirings SL1, SL2, and SL3 of FIG. 4A, channel induction occurs on the surface of the polycrystalline silicon layer, and thus it may be used as an electrode without a separate doping process.

5 illustrates a storage inversion driving waveform according to the present invention.

4B, the storage voltage Vst2 is higher than that of the conventional storage voltage Vst1.

Specifically, referring to the configuration of FIG. 3A, the first expansion unit (1) may be applied to the first expansion unit 18 of the storage wiring 16, which is the second electrode of the storage capacitor, by applying a storage voltage Vst2 higher than the conventional one. Located at the bottom of 18), the surface of the polycrystalline active layer ACT, which is the first electrode of the storage capacitor, may be activated.

That is, activation is possible without performing the doping process on the surface of the polycrystalline active layer, which has the advantage that the doping process may not be added compared to the prior art.

At this time, the storage voltage for activating the undoped polycrystalline active layer ACT is a P-type thin film transistor, the low value of the storage voltage is -4V ~ -8V, the high value is in the range of -8V ~ -12V In case of N-type thin film transistor, low value should be driven in the range of 4V ~ 12V and high value in the range of 12V ~ 16V.

On the other hand, it is possible to increase the storage capacity of the capacitor by increasing the storage voltage, it is possible to configure the area of the storage capacitor compared to the same capacity, there is an advantage to further secure the opening area.

According to the present invention as described above, in manufacturing the liquid crystal panel by the storage line inversion driving method, the level of the storage voltage is increased, so that the polycrystalline active layer, which is the first electrode of the storage capacitor, can be activated without impurity doping.

In addition, by activating the polycrystalline active layer, a separate doping process can be omitted, and a large capacity storage capacitor can be manufactured in a small area without the addition of a mask process, thereby producing an array substrate for a high aperture liquid crystal display device. have.

Claims (4)

Gate wirings and data wirings arranged longitudinally and horizontally on the substrate; A polycrystalline thin film transistor configured at an intersection point of the gate line and the data line; A storage wiring configured to be parallel to the gate wiring; A storage capacitor having the storage wiring as a first electrode, a undoped polycrystalline active layer formed under the first electrode as a second electrode, and a drain electrode in contact with the second electrode as a third electrode And the liquid crystal display device. Gate wirings and data wirings arranged longitudinally and horizontally on the substrate; A polycrystalline thin film transistor configured at an intersection point of the gate line and the data line; A storage wiring configured to be parallel to the gate wiring; A storage capacitor including the storage wiring as a first electrode, a undoped polycrystalline active layer formed under the first electrode as a second electrode, and a drain electrode in contact with the second electrode as a third electrode; In the driving method of the liquid crystal display device, Applying a gate signal to the gate wiring; Alternately applying a storage voltage to the storage wiring; A thin film transistor is turned on by the gate signal, and a data signal is input to the drain electrode in the data line; The surface of the active layer is activated by the input storage voltage, the same signal is applied to the third electrode and the polycrystalline active layer, the storage capacitor is charged in the storage capacitor And a driving method of the liquid crystal display device. The method of claim 2, When the thin film transistor is a P-type, the low value of the storage voltage to activate the surface of the polycrystalline active layer is -4V ~ -8V, the high value is -8V ~ -12V drive of the liquid crystal display device Way. The method of claim 2, And the low value of the storage voltage at which the surface of the polycrystalline active layer is activated is 4V to 12V and the high value is 12V to 16V when the thin film transistor is N type.

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