KR20050096669A - Storage driver for storage inversion - Google Patents

Abstract

The present invention provides a storage driver capable of independently driving storage lines for storage inversion.

In the storage driver of the present invention, an n-th storage driver for driving an n-th (n is a positive integer) storage line alternates first and second storage voltages to the storage line in response to first and second control signals. First and second transistors for supplying electrically; third and fourth transistors commonly controlled by an n + 1th or n + 2th gate line and configured to generate the first and second control signals using first and second clock signals, respectively; First and second capacitors for charging and holding the first and second control signals; The first to fourth transistors are transistors of the same polarity.

Description

Storage driver for storage inversion {STORAGE DRIVER FOR STORAGE INVERSION}

The present invention relates to a liquid crystal display, and more particularly, to a storage driver capable of independently driving a storage line suitable for a storage inversion scheme.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel (hereinafter referred to as a liquid crystal panel) for displaying an image through a liquid crystal cell matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel is driven by an inversion method of inverting the polarity of the liquid crystal cell by a predetermined unit in order to prevent degradation of the liquid crystal and to improve display quality. In Inversion method, Frame Inversion, in which the polarity of the liquid crystal cell is inverted in units of frames, Line Inversion, in which the polarity of liquid crystal cells are inverted in units of horizontal lines, and Liquid crystal cells in units of vertical lines. Column Inversion, the polarity of which is inverted, and Dot Inversion, in which the polarity of the liquid crystal cell is inverted in units of liquid crystal cells, are used.

Among these, the line inversion method of inverting the polarity of the liquid crystal cell in horizontal line units as shown in FIG. 1 is advantageous in terms of power consumption compared to the column inversion and dot inversion methods. This is because the driving voltage range of the data signal can be lowered by AC driving the common voltage Vcom supplied to the liquid crystal cell as the reference voltage. Recently, a method of lowering power consumption by alternatingly driving a storage line instead of a common voltage (Vcom) has been proposed.

FIG. 2 illustrates a liquid crystal panel 10 driven by a line inversion method using a storage line, and FIG. 3 illustrates driving waveforms of the liquid crystal panel 10 illustrated in FIG. 2.

The liquid crystal panel 10 illustrated in FIG. 2 includes gate lines GL1 to GLn and data lines DL1 to DLm that cross each other, storage lines STL1 to STLn parallel to the gate lines GL1 to GLm, and A liquid crystal cell formed in a pixel region defined by the intersection of the gate lines GL1 to GLn and the data lines DL1 to DLm, and a thin film transistor TFT for driving the liquid crystal cell.

The liquid crystal cell includes a liquid crystal capacitor Clc connected to the thin film transistor TFT. The liquid crystal capacitor Clc is formed such that a pixel electrode connected to the thin film transistor TFT and a common electrode formed on the upper substrate face each other with a liquid crystal interposed therebetween. According to the voltage charged in the liquid crystal capacitor Clc, the liquid crystal molecules having dielectric anisotropy rotate to control the light transmittance, thereby realizing gradation.

The liquid crystal cell further includes a storage capacitor Cst connected in parallel with the liquid crystal capacitor Clc. The storage capacitor Cst is formed when the pixel electrode shared with the liquid crystal capacitor Clc and the storage line STL face each other with an insulating layer therebetween. The storage capacitor Cst allows the voltage charged in the liquid crystal capacitor Clc to remain unchanged and stable due to the leakage current of the turned-off thin film transistor TFT.

The thin film transistor TFT is driven in units of horizontal lines by the gate lines GL1 through GLn. In other words, the thin film transistor TFT is turned on by the turn-on voltage from the gate line GL in the driving period of the corresponding horizontal line, and from the gate line GL in the period in which the other horizontal line is driven. It is turned off by the turn-off voltage.

When the thin film transistor TFT is turned on, the liquid crystal capacitor Clc charges the difference voltage between the data signal from the data line DL and the common voltage supplied to the common electrode, and the storage capacitor Cst is the data signal. And a difference voltage between the storage voltage supplied to the storage line STL. Subsequently, when the thin film transistor TFT is turned off, the pixel electrode is in a floating state so that the liquid crystal capacitor Clc and the storage capacitor Clc hold the charged voltage. In this case, when the storage voltage is increased through the storage line STL, the pixel electrode voltage in the floating state is increased by the storage capacitor Clc. Accordingly, the voltage charged in the liquid crystal capacitor Clc sharing the pixel electrode with the storage capacitor Cst increases. As a result, when the storage voltage supplied to the storage line STL is changed, it can be seen that the voltage charged in the liquid crystal capacitor Clc can be changed by the coupling action of the storage capacitor Cst. In this case, when the storage voltage is AC driven, the polarity of the voltage charged in the liquid crystal capacitor Clc may be inverted.

Specifically, FIG. 3 illustrates a method of causing the first to fourth subpixels (hereinafter, P1 to P4) shown in FIG. 2 to be line inverted by the AC driving of the first and second storage lines STL1 and STL2. This will be described with reference to the driven waveform.

First, P1 and P2 are supplied from the first and second data lines DL1 and DL2 by the turn-on voltage supplied to the first gate line GL1 in the first horizontal period H1 (common). The first pixel voltage PV1 of the positive polarity according to the data signal of the voltage reference) is charged. In this case, the first storage voltage Vst1 is supplied to the first storage line STL1.

In the second horizontal period H2, the P1 and P2 hold the voltage charged in the first horizontal period H1 by the turn-off voltage supplied to the first gate line GL1, and the second gate line ( The turn-on voltage supplied to GL2 causes P3 and P4 to have the positive first pixel voltage (according to the negative polarity (common voltage reference) data signal supplied to the first and second data lines DL1 and DL2, respectively. -Charge the PV1). In this case, the first storage voltage Vst1 is supplied to the first and second storage lines STL1 and STL2.

The first storage line ST1 is raised from the third horizontal period H3 to the second storage voltage Vst2 greater than the first storage voltage Vst1 and supplied to the second horizontal period H2 of the next frame. do. The second storage line ST2 is supplied from the fourth horizontal period H4 to the second storage voltage Vst1 to the third horizontal period H3 of the next frame. Accordingly, the first positive pixel voltage VP1 charged with P1 and P2 increases to the second pixel voltage VP2 due to the coupling action of the storage capacitor Cst, so that the first horizontal period H1 of the next frame is generated. Is held until the data signal is supplied. The negative first pixel voltage (-VP1) charged in the P3 and P4 drops to the second pixel voltage (-VP2) and is held until the data signal is supplied in the second horizontal period H2 of the next frame. do. As a result, P1 to P4 implement gradations according to the positive and negative second pixel voltages VP2 and -VP2.

As described above, the liquid crystal panel 10 illustrated in FIG. 2 varies the storage voltage supplied to the storage line STL so that the pixel voltage is variable, thereby reducing the voltage range of the data signal and maintaining the pixel voltage in the horizontal line unit. It can be driven by the line inversion method in which the polarity is inverted. In this case, the voltage supplied to the storage line STLi of the i-th horizontal line i increases or decreases from the period in which the i + 2th horizontal line i + 2 is driven, and thus the i + 2th horizontal line in the next frame. It remains until (i + 2) is driven. In other words, since the storage voltage is changed in units of frames, the storage voltage has a period of two frames.

In order to drive the storage inversion, a storage driver capable of independently driving the storage lines STL1 to STLn is required as described above. Furthermore, a storage driver having a simple configuration is required to be suitable for being incorporated into a liquid crystal panel in accordance with the trend toward becoming more compact. For this purpose, a storage driver composed of only transistors having the same polarity as the thin film transistor of the image display unit is required.

Accordingly, an object of the present invention is to provide a storage driver capable of independently driving storage lines for storage inversion.

Another object of the present invention is to provide a storage driver having a simple configuration so as to be suitable for being embedded in a liquid crystal panel.

Another object of the present invention is to provide a storage driver composed of transistors of the same polarity.

In order to achieve the above object, the storage driver according to an embodiment of the present invention is a storage driver including a plurality of storage driver for independently driving the storage line connected to the storage capacitor included in the liquid crystal cell, n (n Nth storage driver for driving the first storage line, the first and second for alternately supplying the first and second storage voltage to the storage line in response to the first and second control signals. 2 transistors; third and fourth transistors commonly controlled by an n + 1th or n + 2th gate line and configured to generate the first and second control signals using first and second clock signals, respectively; First and second capacitors for charging and holding the first and second control signals; The first to fourth transistors are transistors of the same polarity.

According to another exemplary embodiment of the present disclosure, a storage driver may include an nth storage driver configured to drive an nth (n is positive integer) storage line to the storage line in response to first and second control signals. First and second transistors for alternately supplying two storage voltages; Commonly controlled by an n + 1th or n + 2th output control signal of a gate driver driving an n + 1th or n + 2th gate line, the first and second signals being controlled using first and second clock signals. Third and fourth transistors respectively generating two control signals; First and second capacitors for charging and holding the first and second control signals; The first to fourth transistors are transistors of the same polarity.

The n + 1 th or n + 2 th output control signal of the gate driver is an output control signal boosted by a bootstrapping effect in the shift register driving the n + 1 th or n + 2 th gate line.

The nth storage driver may vary the storage voltage supplied to the nth storage line during a period of enabling the n + 1th or n + 2th gate line to change the data signal charged in the liquid crystal cell to a target value. do.

The nth storage driver varies the storage voltage as opposed to the n + 1th storage driver.

The first and second clock signals are opposite and have two horizontal period periods.

The nth storage driver is delayed by a predetermined interval from the start edge of the period when the n + 1th gate line is enabled when the third and fourth transistors are controlled by the n + 1th gate line. To vary.

The first and second clock signals are delayed in phase by a predetermined interval from the start edge portion.

Other objects and advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 4 to 12.

4 is an equivalent circuit diagram of a liquid crystal panel including a storage driver according to a first embodiment of the present invention, and FIG. 5 is a driving waveform diagram of the liquid crystal panel.

The liquid crystal panel illustrated in FIG. 4 includes a thin film transistor TFT formed at each pixel region defined by the intersection of the gate lines GL1, GL2,..., And the data lines DL1, ..., and a liquid crystal cell, that is, a liquid crystal capacitor. (Clc) and a storage capacitor (Cst).

When the thin film transistor TFT is turned on by the scan signal of the gate line GL, the liquid crystal capacitor Clc receives the difference voltage between the data signal from the data line DL and the common voltage Vcom, and the storage capacitor Cst) charges the difference voltage between the data signal and the storage voltage.

When the thin film transistor TFT is turned off, the pixel electrode floats and the liquid crystal capacitor Clc and the storage capacitor Clc hold the charged voltage. In this turn-off period, the storage driver 20 varies the storage voltage on the storage line STL so that the charging voltage of the liquid crystal capacitor Clc rises or falls to the target voltage by the coupling action of the storage capacitor Clc. do.

Specifically, the storage driver 20 stores the storage lines STL1 and STL2 in the order in which the gate lines GL1, GL2,... Are scanned, that is, enabled and then disabled, as shown in FIG. 5. , ...) will change the storage voltage. At this time, the storage driver 20 causes the odd storage lines STL1, STL3,... And even storage lines STL2, STL4,... To be changed to opposite storage voltages for line inversion. The storage driver 20 maintains the variable storage voltage until a period during which the gate line GL of the corresponding horizontal line is enabled in the next frame, and then reverses it again in the next disable period for inversion. Allow to vary with storage voltage. In this case, the storage driver 20 has a predetermined time interval d between the edge portion of the scan signal and the edge portion of the storage voltage as shown in FIG. 5 so that the enable period of each horizontal line and the variable time point of the storage voltage do not overlap. do. This is to prevent the data signal charged in the liquid crystal capacitor Clc and the storage capacitor Cst from being distorted due to the variable storage voltage in the enable period.

To this end, the storage driver 20 includes a plurality of storage drivers 22-1, 22-2,..., For independently driving the storage lines STL1, STL2,...

Each of the plurality of storage drivers 22-1, 22-2,..., The first and the second supplies alternately supplies the storage high voltage VH and the storage low voltage VL to one storage line STL. 2 PMOS transistors PT1 and PT2, third and fourth PMOS transistors PT3 and PT4 controlling the first and second PMOS transistors PT1 and PT2, respectively, and third and fourth PMOS transistors PT3, And first and second capacitors C1 and C2 for charging and holding each of the first and second control signals from PT4).

The first and second PMOS transistors PT1 and PT2 operate in opposite operations to alternately supply the storage high voltage VH and the storage low voltage VL to the storage line STL to which they are commonly connected.

The third and fourth PMOS transistors PT3 and PT4 generate first and second control signals for alternately driving the first and second PMOS transistors PT1 and PT2. In addition, the third and fourth PMOS transistors PT3 and PT4 control the timing at which the operations of the first and second PMOS transistors PT1 and PT2 are reversed by using the first and second control signals. The storage voltage will be varied.

To this end, the third and fourth PMOS transistors PT3 and PT4 are commonly controlled by the next gate line GLn + 1, and the first and second clock signals CLK1 and CLK2 are used to control the first and second PMOS transistors PT3 and PT4. Generate a second control signal. Accordingly, the third and fourth PMOS transistors PT3 and PT4 sample the first and second clock signals CLK1 and CLK2 whenever they are turned on by the scan signal of the next gate line GLn + 1. Supply with the first and second control signals.

In this case, the first and second control signals have polarities opposite to each other by the first and second clock signals CLK1 and CLK2 shown in FIG. 5. The first and second control signals are charged and maintained in the first and second capacitors C1 and C2, and their polarities are inverted every time the third and fourth PMOS transistors PT3 and PT4 are turned on. As shown in FIG. 5, it has a 2F period. Accordingly, the storage voltages of the corresponding storage lines supplied through the first and second PMOS transistors PT1 and PT2 also have the same period as the first and second control signals. In addition, the edges of the storage voltages supplied to the storage lines STL1, STL2,... With the phase delays d of the first and second clock signals CLK1 and CLK2 are delayed from the edges of the scan signal. It is possible to prevent the enable period of the horizontal line and the variable time point of the storage voltage from overlapping each other.

As shown in FIG. 5, the first storage driver 22-1 and the second storage driver 22-2 control the first and second controls that are opposite to each other by the first and second clock signals CLK1 and CLK2 having a 2H period. By using the signal, the storage voltage is changed to the opposite storage voltage at the variable time point. Accordingly, line inversion driving using the storage voltage can be performed.

As such, the storage driver 20 according to the present invention can independently drive each storage line to enable inversion driving using the storage line. In addition, since the storage driver 20 according to the present invention is composed of the same PMOS or NMOS transistors as the thin film transistor TFT formed in the image display unit, the configuration and the process can be simplified more than using a CMOS transistor. Here, when the transistors PT1 to PT4 constituting the thin film transistor TFT and the storage driver 20 are replaced with NMOS transistors, the polarity of the driving waveform shown in FIG. 5 may be reversed.

6 is an equivalent circuit diagram of a liquid crystal panel having a storage driver according to a second exemplary embodiment of the present invention, and FIG. 7 is a driving waveform diagram thereof.

The storage driver 30 illustrated in FIG. 6 is compared with the storage driver 20 illustrated in FIG. 4, and the third and fourth PMOS transistors PT3, of the storage drivers 32-1, 32-2,. Since PT4) includes the same components except that it is controlled by the n + 2th gate line GLn + 2, description of overlapping components will be omitted.

Since the third and fourth PMOS transistors PT3 and PT4 shown in FIG. 6 are controlled by the n + 2th gate line GL + 2, each of the storage lines STL1 and STL2, together with the first and second control signals, is controlled. The storage voltage on ...) is variable (inverted) at the time point where the n + 2th gate line GL + 2 is enabled as shown in FIG. 7. Accordingly, even when the first and second clock signals CLK1 and CLK2 are not phase delayed, it is possible to prevent the variable time point of the storage voltage from overlapping the scan period of the corresponding horizontal line. Therefore, the data signal charged in the liquid crystal capacitor Clc and the storage capacitor Cst in the enable period of each horizontal line can be prevented from being distorted due to the change in the storage voltage.

8 is an equivalent circuit diagram of a liquid crystal panel having a storage driver according to a third exemplary embodiment of the present invention, and FIG. 9 is a driving waveform diagram thereof.

The storage driver 50 illustrated in FIG. 8 is compared with the storage driver 20 illustrated in FIG. 4, and the third and fourth PMOS transistors PT3, of the storage drivers 32-1, 32-2,. Since PT4 has the same components except that the gate driver 40 is boosted above the clock level by the bootstrapping effect and then controlled by the output Q2, Q3, ... of the Q node, Description of overlapping components will be omitted.

The gate driver 40 shown in FIG. 8 includes a plurality of shift registers 42-1, 42-2, ... for sequentially driving the gate lines GL1, GL2, .... The shift registers 42-1, 42-2, ... of the multi-stage shift the start pulse Vst, which is input from the outside, sequentially by using the first and second clock signals GCLK1 and GCLK2. As shown in the drawing, scan signals for enabling the gate lines GL1, GL2, ... are sequentially generated. At this time, each of the shift registers 42-1, 42-2, ... of the multi-stage shifts the voltage of the Q node that controls the pull-up transistor of the output part to boost the voltage of the Q node by a boot-slap effect to a higher level than the clock level. I'm fast.

The third and fourth PMOS transistors PT3 and PT4 shown in FIG. 8 are controlled by the Q node output Qn + 1 of the shift register driving the next gate line GLn + 1. Accordingly, the third and fourth PMOS transistors PT3 and PT4 are controlled by the output Qn + 1 of the Q node having a swing width larger than that of the scan signal, thereby causing the third and fourth PMOS transistors PT3 and PT4 to malfunction due to the voltage drop of the threshold voltage Vth thereof. It can be prevented.

FIG. 10 is an equivalent circuit diagram of a liquid crystal panel having a storage driver according to a fourth exemplary embodiment of the present invention, and FIG. 11 is a driving waveform diagram thereof.

The storage driver 60 illustrated in FIG. 10 is compared with the storage driver 50 illustrated in FIG. 8, and the third and fourth PMOS transistors PT3, of the storage drivers 62-1, 62-2,. Since PT4) has the same components except that it is controlled by the Q node output Qn + 2 of the n + 2th shift register, a description of redundant components will be omitted.

Since the third and fourth PMOS transistors PT3 and PT4 shown in FIG. 10 are controlled by the Q node output Qn + 2 of the n + 2th shift register, each of the storage lines (1) together with the first and second control signals The storage voltages on STL1, STL2, ...) are variable (inverted) when the n + 2th gate line GL + 2 is enabled as shown in FIG. Accordingly, even when the first and second clock signals CLK1 and CLK2 are not phase delayed, it is possible to prevent the variable time point of the storage voltage from overlapping the scan period of the corresponding horizontal line. Therefore, the data signal charged in the liquid crystal capacitor Clc and the storage capacitor Cst in the enable period of each horizontal line can be prevented from being distorted due to the change in the storage voltage.

As described above, the storage driver for storage inversion according to the present invention may use the scan signal of the gate driver or the output of the Q node to vary the storage voltage on each storage line to suit the storage inversion.

In addition, the storage driver for storage inversion according to the present invention is configured of a transistor having the same polarity as the thin film transistor of the image display unit, thereby simplifying the circuit and the manufacturing process so as to be suitable for embedded in the liquid crystal panel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a view for explaining a line inversion method of a liquid crystal display panel.

Figure 2 shows a conventional storage inversion liquid crystal panel.

FIG. 3 is a driving waveform diagram of the liquid crystal panel shown in FIG. 2.

4 is an equivalent circuit diagram of a liquid crystal panel including a storage driver according to a first embodiment of the present invention.

FIG. 5 is a driving waveform diagram of the liquid crystal panel shown in FIG. 4.

6 is an equivalent circuit diagram of a liquid crystal panel including a storage driver according to a second embodiment of the present invention.

FIG. 7 is a driving waveform diagram of the liquid crystal panel shown in FIG. 6.

8 is an equivalent circuit diagram of a liquid crystal display panel including a storage driver according to a third embodiment of the present invention.

FIG. 9 is a driving waveform diagram of the liquid crystal panel shown in FIG. 8.

10 is an equivalent circuit diagram of a liquid crystal display panel including a storage driver according to a fourth embodiment of the present invention.

FIG. 11 is a driving waveform diagram of the liquid crystal panel shown in FIG. 10.

<Description of Symbols for Main Parts of Drawings>

10: liquid crystal panel 20, 30, 50, 60: storage driver

22-1 (2), 32-1 (2), 52-1 (2), 62-1 (2): Storage driver

40: gate driver 42-1 (2) (3): shift register

Claims (8)

A storage driver having a plurality of storage drivers for independently driving a storage line connected to a storage capacitor included in a liquid crystal cell, The nth storage driver for driving the nth (n is a positive integer) storage line First and second transistors for alternately supplying first and second storage voltages to the storage lines in response to first and second control signals; third and fourth transistors commonly controlled by an n + 1th or n + 2th gate line and configured to generate the first and second control signals using first and second clock signals, respectively; First and second capacitors for charging and holding the first and second control signals; The first to fourth transistors are transistors of the same polarity. A storage driver having a plurality of storage drivers for independently driving a storage line connected to a storage capacitor included in a liquid crystal cell, The nth storage driver for driving the nth (n is a positive integer) storage line First and second transistors for alternately supplying first and second storage voltages to the storage lines in response to first and second control signals; Commonly controlled by an n + 1th or n + 2th output control signal of a gate driver driving an n + 1th or n + 2th gate line, the first and second signals being controlled using first and second clock signals. Third and fourth transistors respectively generating two control signals; First and second capacitors for charging and holding the first and second control signals; The first to fourth transistors are transistors of the same polarity. The method of claim 2, The n + 1th or n + 2th output control signal of the gate driver And an output control signal boosted by a bootstrapping effect in the shift register driving the n + 1th or n + 2th gate line. The method according to any one of claims 1 and 2, The n th storage driver The storage driver may vary the storage voltage supplied to the nth storage line in a period during which the n + 1th or n + 2th gate line is enabled so that the data signal charged in the liquid crystal cell is changed to a target value. , The method according to any one of claims 1 and 2, The nth storage driver to vary the storage voltage as opposed to the n + 1th storage driver; The method according to any one of claims 1 and 2, And the first and second clock signals are opposite and have two horizontal period periods. The method according to any one of claims 1 and 2, The n th storage driver When the third and fourth transistors are controlled by the n + 1th gate line And varying the storage voltage by a predetermined interval from the start edge of the period in which the n + 1 th gate line is enabled. The method of claim 7, wherein And the first and second clock signals are delayed in phase by a predetermined interval from the start edge portion.